JPH04291544A - Data check method in data transmission system - Google Patents

Abstract

PURPOSE:To check a reply data from each slave set properly without increasing the hardware when a master set applies control to each slave sat simultaneously with respect to the data check method of the system implementing data transmission between the master set and plural slave sets connecting to the master set. CONSTITUTION:When a master set 30 applies simultaneous control to plural slave sets 401-40n in the data transmission system in which the plural slave sets 401-40n are connected to the master set 30 and data transmission is implemented between the master set 30 and the plural slave sets 401-40n, a time difference is given to the transmission of a reply data from each of the plural slave sets 401-40n and the master set 30 receives sequentially the reply data from each of the plural slave sets 401-40n to check each reply data sequentially.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a data transmission system that is composed of one main device that controls the entire system and a plurality of slave devices connected to this main device, for example in an electronic exchange. Regarding the check method.

0002

2. Description of the Related Art A transmission system as shown in FIG. 6 is an example of a system in which a plurality of slave devices are connected to one main device and data is transmitted between the master device and each slave device. be.

In FIG. 6, 1 is the main device, 21 to 2n
are slave devices, and each of these slave devices 21 to 2n is connected to a large number of terminal devices such as telephones, although not shown here.

In the main device 1, 11 is a selector (
SEL), 12 is a decoder (DEC), 13 is a parity generator (PG), 14 is a parity checker (PC
), 15 is a time checker (TC).

On the other hand, in the slave devices 21 to 2n, 2
1 is a parity checker (PC), 22 is a command analysis unit (CMDANL), and 23 is a response generator (R
SPGEN), 24 is a parity generator (PG).

[0006] From the main device 1 to each slave device 21 to 2n
The signals directed to are commands (CMD) 1 to (
CMD)n and command enable (CMDEN)1
〜(CMDEN)n, and the response (RSP) is the signal sent from the slave devices 21 to 2n to the main device 1.
1 ~ (RSP)n and response enable (RES
There are EN)1 to (RESEN)n.

In the following explanation, the names of the above-mentioned parts and signals will be explained using the abbreviations shown in parentheses above, for example, SEL 11 will be explained as follows. Next, the processing operation in such a configuration will be explained with reference to the time chart of FIG. 7. The CMD created by the main device 1 consists of 4 bits (the effective part in the figure) as shown in Fig. 7(a), and the P as shown in Fig. 7(b).
Parity (P) is assigned in G13, and each slave device 21 ~
2n, multiple signals are sent as CMD1 to CMDn. The reason why parity (P) is given here is to check the normality of transmission between the main device 1 and the slave devices 21 to 2n.

The effective portion of the above CMD including the parity (P) is CMDEN1, which is shown in FIG. 7(c). In the figure, the effective portion is shown at low (L) level. Incidentally, normally, the slave device to be controlled by the main device 1 is one of n slave devices. CMD is sent to each slave device 21 to 2n in multiple ways,
CMDEN is sent only to the slave device to be controlled. This control is performed by the slave device select signal S from the DEC 12 of the main device 1.
1, and sends CMDEN to the slave device corresponding to the select signal S1.

This example shows the case where the slave device 21 is selected as the slave device to be controlled. Therefore, the slave device select signal S1 brings the slave device 21 into a selected state as shown in FIG. 7(d), and as a result, only CMDEN1 goes to the "L" level as shown in FIG. 7(e), and the other CMDEN2 ~CMDENn remains at the high (H) level as shown in FIG. 7(f).

In the slave device 21, CMDEN1 is “L”
CMD1 corresponding to the level is taken in and a parity check is performed on the PC21. At the same time, CMDANL2
At step 2, the bit pattern of CMD1 is analyzed to determine the control content, and instructions are given to each subordinate block (not shown). Here, the parity check in the PC 21 is N.
If it is G, no command will be given.

[0011] Then, the "response" to the "instruction" from each block is input to the RSRGEN 23, and as shown in FIG. 7(g)
It is assembled as an RSP1 for the main device 1 as shown below. In the example shown in FIG. 7(g), the effective part is 4 bits. Then, parity P is added at PG24, and main device 1
sent to. RSPEN1 indicates the effective part of RSP1, including parity P, as shown in Figure 7(h).
This shows that RSP1 is an effective part when it is at the "L" level.

RSP1 and RS from the slave device 21
When PEN1 is input to the main device 1, the selector 11
It is sent to the PC 14 and TC 15 through. This selector 11 selects the slave device 21 by the slave device select signal S1.
is controlled to select.

[0013] In the PC 14, RSPEN1 is “L”
A parity check is performed by fetching RSP1 corresponding to . The above is the data transmission processing operation between the main device 1 and the slave device 21, and this is the processing operation for data transmission between the main device 1 and the slave device 21.
is also done in the same way.

In this way, the main device 1 and the slave devices 21 to 2n
As mentioned above, as a check regarding data transmission between P is assigned, and the main device 1 performs a parity check.

However, when the CMD from the main device 1 becomes parity NG in the slave device, the slave device sends the RSP
is not returned. In other words, although the main device 1 issues a CMD, since there is no RSP from the slave device, the main device side continues to wait for the RSP to be returned from the slave device, and cannot move on to the next process.

In order to eliminate this inconvenience, the main device side adopts a method in which a time limit is set for returning the RSP to the CMD, and if the RSP is not returned within the time limit, it is recognized as a failure. The TC15 does this. This TC 15 checks a predetermined time limit, and if the RSP is not returned within the time limit, it is recognized that some kind of failure has occurred.

[0017]

[Problems to be Solved by the Invention] As described above, data transmission and checking between the main device 1 and the slave devices 21 to 2n is performed, but depending on the control content, all the slave devices 2n
There is also a case where it is desired to send CMD to 1 to 2n all at once.

However, in the conventional configuration shown in FIG. 6, CMDEN is used to select only one slave device to be controlled, so-called "targeting", so that all slave devices 21 to 2n are It is not possible to send CMD all at once.

To make this possible, further signals are input to the DEC 12 of the main device 1 shown in FIG.
When transmitting D, the DEC 12 is controlled by the signal, and CMDEN to all slave devices 21 to 2n is changed to CMD.
One possible method is to make it the effective side.

However, in this case, all slave devices 21 to 2n
, RSP1 to RSPn will be returned at the same time, but since the RSP to be selected by the selector 11 is determined on the main device 1 side, all slave devices 21 to 2
The drawback is that it is not possible to check all of the RSPs from n. In order to solve this problem, it may be considered to provide a PC 14 and a TC 15 corresponding to all the slave devices 21 to 2n, but the amount of hardware is large and it is not preferable to provide a large number of these.

[0021] From these viewpoints, conventionally, CMD
When sending out RSP, there is a drawback that it is not possible to check all RSPs. According to the present invention, when a main device issues CMD to multiple slave devices all at once, responses from each slave device are sent with a time difference, and the responses are sequentially selected on the main device side. This makes it possible to check responses from all slave devices on the same PC and TC, and enables data transmission that enables proper data checking even when simultaneous CMD is specified, without increasing the hardware. This is an attempt to realize a data check method in the system.

[0022]

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram for explaining the principle of the present invention. In the figure, 30 is a main device, and 401 to 40n are a plurality of devices connected to this main device 30. This is a slave device.

From the main device 30 to each slave device 401 to 4
The signal going to 0n is CMD1 to CMD as in Figure 6.
n and CMDEN1 to CMDENn, and the signals from the slave devices 401 to 40n to the main device 30 are RS
P1 ~RSPn and RSREN1 ~RSRENn
There is.

For example, if the object to be controlled by the main device 30 is the slave device 401, CMDEN1 goes to the "L" level as in the previous period, and CMD1 is sent to the slave device 401. On the slave device 401 side, after receiving CMD1 and performing a parity check and processing according to the contents of CMD1, the “
It responds to the main device 30 during the L'' level.

Then, the main device 30 receives RSP1 from the slave device 401 and passes it through the selector 31 to the PC3.
At step 2, a parity check is performed, and at the same time, the time required for return is checked at TC33.

The above data transmission processing operation is similar to the conventional one shown in FIG.
Next, the response processing will be explained.

[0027]

[Operation] In the case of this simultaneous CMD designation, all slave devices 401
~40n, CMDEN is sent from the main device 30 on the valid side.

On the other hand, the slave devices 401 to 40n perform processing according to the above CMD1 to CMDn, but their responses are performed with a time difference. This will be explained with reference to FIG. In FIG. 2, at a certain time t1, the main device 3
From 0, a simultaneous CMD designation is issued, and CMD1 to CMD
n is simultaneously sent to each slave device 401 to 40n.

After the slave device 401 completes the processing according to the contents of CMD1, it sends RSP1 to the main device 30 after Δt1 from the arrival of the above CMD1, and the slave device 402 performs the processing according to the contents of CMD2. After completing Δt from the time when the above CMD2 arrived
2 later, RSP2 is sent to the main device 30, and the slave device 40n finishes processing according to the contents of CMDn, and then sends RSP2 after Δtn from the time when the above CMDn arrives.
RSP1 to RSPn are sent back with a time difference, such as sending SPn to the main device 30.

[0030] On the main device 30 side, the slave device 401
RSP1 sent out sequentially from ~40n ~RSP
n is selected by the selector 31 in synchronization with the sending timing of RSP1 to RSPn, and R
SP1 to RSPn are selected in sequence, and the PC32 and TC33 perform a parity check and a time check.

[0031] In this way, in the case of simultaneous CMD transmission, the slave devices 401 to 40n receive the signals with a time difference.
Since the response signal is configured to arrive at the main device 30 side, the main device 30 has one PC 32 that performs parity check and one TC 33 that performs time check to check the response signals of all slave devices 401 to 40n. Can be done.

[0032]

[Example] Next, an example of the present invention will be described. FIG. 3 shows the configuration of the same embodiment. Similar to FIG. 1, a plurality of slave devices 401 to 40n are connected to the main device 30.

[0033] These main device 30 and slave device 401
The signal between ~40n is the same as that shown in Figure 1,
From the main device 30 to the slave devices 401 to 40n, CMD
1 to CMDn and CMDEN1 to CMDENn, and RSP1 to RSPn and RSPEN1 to RSP are sent from the slave devices 401 to 40n to the main device 30.
ENn is sent.

Furthermore, the configurations of the slave devices 401 to 40n include a PC (parity checker) 41 and a CMDAN.
L (command analysis unit) 42, RSPGEN (response generator) 43, PG (parity generator) 4
It consists of 4.

On the other hand, the main device 30 has a SEL (selector) 3
1, PC (parity checker) 32, TC (time checker) 33, DEC (decoder) 34, response time designation bit inserter (hereinafter abbreviated as RTIN) 351 to 35n, PG (parity generator) )
361 to 36n.

The RTINs 351 to 35n are provided corresponding to each slave device 401 to 40n, and in the case of simultaneous CMD designation, RSP1 to RSPn and RSPEN1 to RSP from each slave device 401 to 40n are provided.
In order to provide ENn with a response time difference, information for specifying the time difference is added to the designated area bits of each CMD1 to CMDn.

The signal S2 for specifying the simultaneous CMD is as follows:
These RTIN351 ~ 35n and DEC34, SE
It is also input to L31. The operation of this configuration will now be described with reference to the time charts of FIGS. 4 and 5.

First, in this embodiment, FIG. 4(a)
As shown in , m-bit R of T1 to Tm is added to CMD.
An SP response timing specification area is added. This m-bit timing specification area may be provided at any part of the CMD, but in this embodiment, it is provided at the end of the CMD.

By the way, in the above-mentioned timing designation area, if there are, for example, four slave devices, four types of timing designation are required. In other words, if this is expressed as “0” and “1”,
For the slave device 401, the time is specified by “0” and “0”, for the slave device 402, the time is specified by “0” and “1”, and in the same way for the slave device 403, it is “1”. ，
It is necessary to specify four different times, such as "0" and "1" for the slave device 404, and 2 bits are required for the CMD specification area. Therefore, m of m bits is expressed as a natural number such that 2m≧n, where n is the number of slave devices.

FIG. 4B shows a signal obtained by adding a parity bit P to the CMD shown in FIG. The CMD indicates the effective part including the parity bit.
EN (the "L" level is the effective part), which is shown in FIG. 4(C). This CMDEN is sent by the DEC 34 to the slave device to be controlled by the main device 30. For example, slave device 40
1 is the control target, the slave device select signal S1 is supplied to the DEC 34, and only CMDEN1 becomes "L" level.

[0041] In addition, in the case of simultaneous CMD designation, simultaneous CM
The D designation signal S2 is supplied to the DEC 34, as shown in FIG. 4(d).
As shown in , CMDEN1 to CMDENn are all “
The signal becomes L'' level and is sent to each slave device 401 to 40n.

Next, the operation in the case of simultaneous CMD designation will be explained with reference to the time charts of FIGS. 4 and 5. First, in the case of simultaneous CMD designation, a simultaneous CMD designation signal S2 is supplied to the DEC 34 and the SEL 31. On the other hand, CMD is controlled by each RTIN351 to 35n.
Each slave device 401 ~
Timing information for providing a response time difference with respect to 40n is written. In other words, in order to respond immediately, the slave device 401 sets the response time to "0" and the slave device 402
The response time is “1” for the slave device 403, and the response time is “1” for the slave device 403.
2", and the slave device 40n specifies the response time as "n-1" and the response timing as times "0" to "n-1". ”, m of T1 to Tm shown in FIG. 4(B)
Write information to bits. For example, to specify time “0”, if m is 4 bits, T1 to Tm are “
0000”, T1 to Tm to specify time “1”
T1 to specify “0001” and time “2”.
~Write a code indicating the time, such as "0010", in Tm.

[0043] In this way, each RTIN 351 to 35n
After writing information on the timing specified time of the corresponding slave devices 401 to 40n, each PG361 to
A parity bit P is added to each of the bits 36n and 36n.

Since the CMD is designated here all at once, all of CMDEN1 to CMDENn go to the "L" level, and as a result, each of CMD1 to CMDn is simultaneously sent to the corresponding slave devices 401 to 40n.

[0045] Each slave device 401 to 40n is
After receiving the corresponding CMD1 to CMDn and processing according to their contents, R is sent at the specified time.
SP1 to RSPn are returned.

FIG. 5 shows the corresponding timing. In FIG. 5, the time axis is reduced compared to FIG. 4. Figure 5(a)
shows CMDEN1 to CMDENn sent from the main device 30 to each of the slave devices 401 to 40n at the same time.

[0047] The slave device 401 is CMDEN1.
The response time for the arrival of ``0'' is specified. This slave device 401 analyzes the timing specification area bit information written in CMD1, recognizes that the response time is "0", and immediately returns RSP1. However, when analyzing CMD1 or editing RSP1,
Since it takes a certain amount of time, in reality, as shown in Figure 5(b), RSP is activated after a time α after receiving CMD1.
1 (RSPEN1 is shown in the figure).

Furthermore, the response time of the slave device 402 to the arrival of CMDEN2 is designated as "1". This slave device 402 analyzes the timing designation area bit information written in CMD2 and determines that the response time is "1".
Recognize that. As a result, the slave device 402 receives CMD2 as shown in FIG. 5(c), and then
RSP2 is returned after a time of 1×β+α (RSPEN2 is shown in the figure). Here, β represents one unit of designated time.

[0049] As a result, the slave device 40n operates as shown in Fig. 5(d).
As shown in , after the arrival of CMDENn (n-1
)×β+α, RSPn is returned (RSPENn is shown in the figure).

In this way, simultaneous CMD from the main device 30
When CMD1 to CMDn are simultaneously sent to each slave device 401 to 40n according to the specification, RSP1 to RSPn from each slave device 401 to 40n is as shown in FIG. 5(e), and RSP1 is sent after α time. R.S.
P2 is after 1×β+α time, RSPn is (n-1)×
The data is returned sequentially with a delay of β such as after β+α time. In addition, in FIG. 5(e), RSPEN1 to R
SPENn is illustrated.

[0051] In the main device 30, the slave devices 401 to
RSP1 is sent sequentially with a time difference from 40n.
~RSPn is selected in SEL31, but this S
The timing of the select switching operation of EL31 is shown in Figure 5 (
f) The selection timing is switched using the time difference β as shown in FIG. This allows RSP1 to be selected first, then RSP2, and so on.
In response to the arrival of RSPn, RSP1 to RSPn
can be selected sequentially. RSP1 to RSPn that have passed this SEL31 are sequentially connected to the PC32 and TC.
A parity check and a time check are performed at 33.

By the way, the response time designation bit provided in CMD may be added only when simultaneous CMD is specified, or may be added even when simultaneous CMD is not specified. The reason is that each slave device 401 to 40n
At this time, the CMDANL 42 performs CMD analysis, and it can be determined there whether or not the CMD is specified all at once, and in the case of the simultaneous CMD specification, a specific area in the CMD is recognized as a timing specification area bit. On the other hand, when controlling only one slave device, it can be recognized that there is no bit such as a timing designation area bit in the CMD, and in this case, that bit is ignored.

As described above, when specifying CMDs all at once, by providing a time specification area in each CMD from the main device side, each slave device side can specify the timing according to the timing specification written in each received CMD. , responses are made sequentially with a time difference, and the main device side sequentially selects the responses from each slave device using a selector, and then performs a parity check and a time check, so the main device side does not have to specify simultaneous CMD. Even in this case, only one parity checker and one time checker are required, making it possible to specify CMD all at once without increasing the hardware. In this case, it is necessary to provide a response time designation bit writing unit (RTIN) for each slave device.
Since this can be realized with a simple gate circuit, the amount of hardware is much less than providing a parity checker and a timing checker for each slave device, as mentioned in the section on the disadvantages of the previous conventional example. It's over.

In the above embodiment, each slave device 401 to 40n
An area for specifying the response timing is provided in CMD1 to CMDn to be sent to each slave device 401 to 40n.
In the above, the received CMD1 to CMDn are returned at the specified timing, but the method is not limited to this method. When setting a work order so that the response timing is different for each slave device 401 to 40n, and specifying simultaneous CMD, RSP1 is sent from each slave device 401 to 40n according to the settings of each of these work notes.
~RSPn may be returned sequentially at each set time. In this case, RTIN351 ~ 3 shown in Figure 3
5n becomes unnecessary.

Furthermore, in addition to the method of the previous embodiment, for example, in the RTINs 351 to 35n shown in FIG.
D1 to CMDn may be sent to each slave device 401 to 40n with a preset time difference. In other words, when specifying CMD all at once, first enter RTIN35.
CMD1 is sent from 1 and RTIN is sent after a predetermined time.
352 to CMD2 are automatically sent out sequentially with a preset time difference.
may be sent. If you do this,
The slave devices 401 to 40n inevitably respond with a preset time difference. In this case, timing data specifying the response time is not required.

[0056]

According to the present invention, in a data transmission system in which a plurality of slave devices are connected to a master device and data is transmitted between the master device and each slave device, all of the slave devices can be transmitted from the master device to each slave device. When controlling all the slave devices all at once, the response time from each slave device was controlled to have a time difference, and the data was sent back from each slave device in sequence. You can perform checks such as parity check and timing check sequentially.
Even in the case of simultaneous control, which poses a problem in terms of the amount of hardware, there is no need to provide a timing checker for each slave device, and a data check method in a data transmission system that is extremely advantageous in terms of hardware configuration can be realized.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram for explaining the principle of the present invention.

FIG. 2 is a diagram for explaining the state of return of response data from each slave device in FIG. 1;

FIG. 3 is a configuration diagram of an embodiment of the present invention.

[Figure 4] CMD signal and CMDEN in the same embodiment
This is a timing chart showing the signals, and (a) is the CM
A diagram showing an example of adding a response timing designation area to the D signal, (b) is a diagram showing a CMD signal with a liberty bit added and actually sent to each slave device, (c)
is a diagram showing the CMDEN signal, and (d) of the same figure is a diagram showing the CMDEN signal actually sent to each slave device.

FIG. 5 is a timing chart showing the return timing of return data from each slave device in the same embodiment; FIG. ~(d) is R from each slave device
Diagram showing the SPEN signal, (e) in the same figure is (b) in the same figure
(d) is a diagram showing the RSPEN on the same time axis, and (f) of the same diagram is a diagram showing the selection switching state of the selector of the main device.

FIG. 6 is a configuration diagram of a main device and a slave device for explaining a conventional data transmission check method.

FIG. 7 is a timing chart for explaining the data transmission method in FIG. 6; FIG. Diagram showing the CMD signal sent to the device, same figure (c)
(d) is a diagram showing the select state of the selector in the main device; (e) is a diagram showing the CMDEN signal.
Figure 2 shows the status of the CMDEN signal sent to the slave device to be controlled, (f) shows the status of the CMDEN signal to slave units other than the slave device to be controlled, and (g) shows the status of the CMDEN signal to the slave device to be controlled. (i) is a diagram showing RSPEN.

[Explanation of symbols] 30 Main device 31 Selector 32 Parity checker 33 Time checker 34 Decoder

Claims (5)

[Claims] Claim 1: A plurality of slave devices (4
01 to 40n) are connected, and these main devices (30)
In a data transmission system that performs data transmission between the main device (30n) and each slave device (401 to 40n), the main device (30n)
) performs simultaneous control on each slave device (401 to 40n), a time difference is established between the transmission of response data from each slave device (401 to 40n), and the main device (30)
A data check method in a data transmission system, characterized in that a side receives response data from each slave device (401 to 40n) sequentially and checks each response data sequentially. [Claim 2] As a means for setting a time difference between transmission of response data, the main device (30) to each slave device (401 to 4
An area for specifying the response timing is provided in each control data sent to the slave device (0n), and response timing specification information for each slave device is written in this area and sent.
2. The data check method in a data transmission system according to claim 1, wherein the data transmission system (01 to 40n) responds at a timing corresponding to response timing designation information written in the received data. 3. As a means for setting a time difference in the transmission of response data, a manual is provided in each slave device (401 to 40n), and each slave device is set in advance for each slave device. 2. A data check method in a data transmission system according to claim 1, wherein the response timing is controlled according to the following. 4. As a means for setting a time difference between the transmission of response data, the main device (30) to each slave device (401 to 4
The timing of the control data to be sent to the main device (30) is set in advance, and each slave device (40) is transmitted at the preset timing by connecting each slave device to the main device (30).
1 to 40n). 5. Each response data from each slave device (401 to 40n) is selected by switching the selector (31) according to the response timing in the main device (30), and selecting the response data from each slave device (401 to 40n).
401 to 40n) and sequentially checks each response data.