JPH063591B2 - Control method of reception data in communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a communication control device for transmitting / receiving broadcast data or the like to / from another communication facility via a communication line, and the received data to a CPU. Control method for reference.

(Prior Art) Conventionally, as this type of communication control device, one using a two-bank memory for a broadcast data transmission / reception buffer as shown in FIG. 6 is known. That is, in the figure, 1'is a communication control device, 2 is a memory provided with memory 21,
Bank memory, 4 is a communication line, 5 is another communication facility (hereinafter referred to as a controller) such as a controller or a computer that sends and receives data via the communication line 4, 6 is a system bus, and 7 is a central processing unit ( Hereinafter referred to as CPU),
Reference numeral 11 is a memory switching control unit, 13 is a system bus control unit, and 17 is a reception flag. In addition, for convenience, the sixth
In the figure, the means for sending / receiving data to / from the communication line 4 and the interface means to the system bus 6 are omitted.

In this communication control device 1 ', the broadcast data is sent to and from the other controller 5 via the communication line 4.
The outline of the operation for receiving will be described. First, on the transmission side, as shown in the figure, the memory 21 connected to the communication line 4 side has the communication controller 1'currently connected to the controller 5
Memory 22 which stores the broadcast data being transmitted to the other side, and is connected to the system bus 6 on the other hand.
Is used as a work area for the CPU 7 to prepare new transmission data.

Here, as the operation of changing the broadcast data transmitted from the communication control device 1 ′ to the controller 5,
CPU 7 for memory 22 connected to system bus 6
Sets new transmission data, and then outputs a transmission memory switching request. The communication control device 1 ′ switches the memory connection via the memory switching control unit 11 in accordance with the switching request. That is, the memory 22 is connected to the communication line 4, and the memory 21 is connected to the system bus 6 side.

On the other hand, when receiving broadcast data, the memory 21 connected to the communication line 4 is used as a broadcast data reception buffer, and the memory 22 connected to the system bus 6 side is used as a reference area of the CPU 7.

The communication control device 1 ′ stores the broadcast data on the communication line 4 in the memory 21 only when the reception flag 17 is not set. At this time, if the reception of the broadcast data is completed normally, the reception flag 17 is set, and the memory switching can be immediately performed by the subsequent reception memory switching request from the CPU 7. Here, the memory switching is to connect the memory in the 2-bank memory 2 that was connected to the communication line 4 to the system bus 6 side, and conversely connect the memory that was connected to the system bus 6 to the communication line 4. It means to do.

When the reception flag 17 is set, the communication control device 1 ′ does not perform new broadcast data reception processing, but performs memory switching when receiving a reception memory switching request from the CPU 7. When the memory is switched, the reception flag 17 is cleared. In addition, between the last reception memory switching request and this reception memory switching request,
If new broadcast data is not received, or if any of them is not normally completed, the reception flag 17 is not set, and the communication control device 1'is The CPU 7 continues to refer to the same broadcast data as the previous time without switching the memory.

Here, the CPU 7 first outputs a reception memory switching request,
The communication control device 1 ′ refers to the broadcast data by accessing the 2-bank memory 2 after receiving it.

According to the above operation, the update state of the broadcast data that the CPU 7 can refer to when the CPU 7 outputs the reception memory switching request at a certain cycle is represented by the timing chart of FIG. In FIG. 7, focusing on the relationship between the reception timing of the broadcast data and the timing at which the CPU 7 can refer to the data, the data d ₁ that can be normally received for the first time after the reception bank switching request from the CPU 7 is output, d ₂ ,
It is clear that d ₄ , d ₆ and d ₇ can be referred to by the next reception memory switching request. In the figure, the symbol x indicates data that cannot be referred to.

From this fact, when the CPU 7 constantly outputs the reception memory switching request at a constant period that is not so long as the refresh period of the broadcast data,
It can be said that 7 can always refer to almost the latest broadcast data.

(Problems to be Solved by the Invention) Here, in a distributed processing system in which the CPU 7 attached to the communication control device 1 ′ only monitors and controls the operation of the controller 5, the CPU 7 operates when an event occurs. And communication line 4 for logging the status of controller 5
It is only necessary to refer to the broadcast data that is sent from time to time via the Internet, and in this case, the reception memory switching request may be output only once irregularly as needed.

However, in the conventional control method, as described above, C
It is impossible to refer to the most recent broadcast data unless the PU 7 always outputs the reception memory switching request at a constant cycle. When the PU 7 outputs the reception memory switching request only once when necessary. Causes a situation in which the CPU 7 can only refer to valuable data that has existed for a long time.

Therefore, in the conventional case, even when the broadcast data may be referred to as needed as in the above-described distributed processing system, the CPU 7 constantly switches the reception memory to the communication control device 1 ′ at a constant cycle. There is a problem that the load on the CPU 7 increases because the request must be output. In addition, in the method of outputting the reception memory switching request twice when referring to the broadcast data, it is necessary to set a sufficient time for receiving new broadcast data as the interval between the first and second switching requests. However, it has a drawback that the responsiveness is significantly lowered.

Further, as another method, a method in which the communication control device 1 ′ itself switches the reception memory voluntarily when the normal reception of the broadcast data is completed is conceivable. I can't get it, C
There is a problem that the PU 7 side needs to read the broadcast data twice.

The present invention has been proposed to solve the above problems, and an object of the present invention is to always output the latest broadcast data at that time if the CPU outputs a switching request only once as needed. CPU for reference
The purpose of the present invention is to provide a communication control method that reduces the load on the device and improves the responsiveness.

(Means for Solving the Problems) In order to achieve the above object, in the present invention, first, according to a data reception bank for storing reception data in a reception area in a communication control device and a reception timing of the reception data. And a data update bank that updates the latest received data
Data reference banks that are always referenced by U are set.

Then, each memory in the three-bank memory provided as a reception buffer is made to correspond to the data reception bank, the data update bank, and the data reference bank alternately according to the reception timing of data, and the above-mentioned is made by the reception bank switching request from the CPU. It is characterized in that the memory corresponding to the data update bank is switched to the data reference bank so as to correspond to the latest received data stored in the memory.

(Operation) In the present invention, the two banks not referred to by the CPU, that is, the data reception bank and the data update bank, always receive and update data, and the latest received data always corresponds to the data update bank. The latest received data can be referred to by storing the data in the memory and making the memory correspond to the data reference bank in response to the reception bank switching request output from the CPU when necessary.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a conceptual diagram of a communication control device 1 to which the present invention is applied. In this embodiment, a point that a 3 bank memory 3 is used as a reception buffer for broadcast data is different from the conventional example shown in FIG. There is.

That is, in FIG. 1, the 3-bank memory 3 is a memory.
31-33, one of these memories 31-33 according to the reception timing of broadcast data.
One is connected to the communication line 4, another one is connected to the CPU 7 via the system bus 6, and the remaining one is not connected to any one. In the illustrated example, the memory 31 is now connected to the communication line 4 and the memory 33 is connected to the system bus 6, but such a connection configuration is not fixed.

The other configurations are the same as those in FIG. 6, 5 is another controller, 11 is a memory switching control unit, 12 is a communication line control unit,
Reference numeral 13 is a system bus control unit, and 17 is a reception flag.

Next, the function of the 3-bank memory 3 will be described with reference to FIG. In the figure, A is a data reception bank connected to the communication line 4 for storing received data, B is a data reference bank connected to the system bus 6 and the received data is referred to by the CPU 7, and C is the communication line 4 and the system bus. 6 shows data update banks which are not connected to any of 6 and always store the latest received data in the data reception bank A. Here, as described above, the banks A to C do not correspond to the memories 31, 33 and 32 in FIG.

In these bank A to, bank A has a communication line 4
The above broadcast data is always stored. If the data reception ends normally, the reception flag
17 is set, and bank switching 300 is performed between bank A and bank C. Here, the bank switching means switching the memory corresponding to the bank A so as to correspond to the bank C as described later.

Thereafter, each time new data is sent to the communication line 4, the data is stored in the bank A, and the reception flag 17 is continuously set when the reception is normally completed. Here, if the reception flag 17 is set in advance, the set state is maintained. When the reception flag 17 is set in this manner, the broadcast data is always stored in the memory corresponding to the bank C.

On the other hand, when the reception bank switching request is output from the CPU 7 to the communication control device 1, the communication control device 1 checks the reception flag 17. At this time, if the reception flag 17 is set, bank switching 301 is performed between the bank C and the bank B to clear the reception flag 17. By this processing, the latest broadcast data stored in the memory corresponding to the bank C corresponds to the bank B connected to the system bus 6, and the CPU 7 can refer to this data.

FIG. 3 corresponds to FIG. 7 described above and is a timing chart showing a data update state in each of the memories 31 to 33 of the 3-bank memory 3. In the figure, at the timing of receiving the broadcast data d ₁ , bank A in FIG. 2 corresponds to the memory 32, bank B corresponds to the memory 31, and bank C corresponds to the memory 33. When the reception of the data d ₁ is completed normally, the reception flag 17 is set and the memory corresponding to the banks A and C is set.
Bank switching is performed between 32 and 33. And CPU7
The receiving bank switching request is output from the memory, the memory corresponding to the banks C and B is confirmed after confirming the set state of the receiving flag 17.
Bank switching between 33 and 31 and reception flag 17
Is cleared. As a result, the CPU 7 can refer to the data d _{1 of the} bank B.

Similarly, the bank A corresponds to the memory 33 when the data d ₂ sent after the data d ₁ is received, and the bank A corresponds to the memory 31 when the data d ₃ is received. The memory corresponding to B and C also changes sequentially, but in any case CP
If there is a reception bank switching request from U7, reception flag 1
It is possible to refer to the latest data d ₄ , d _7, ... Etc. in the bank B after checking 7.

Next, the configuration of the communication control device 1 in this embodiment will be described in detail with reference to FIG. In the figure, the memories 31 to 33 of the three-bank memory 3 are allocated so as to overlap with each other at the same address, and the bank switching control unit 11 performs selection control as to which of the banks A to C they correspond to. The communication line controller 12, the system bus controller 13, and the CPU 7 do not need to be aware of which memory 31-33 is being accessed.

When the communication line control unit 12 receives the broadcast data on the communication line 4, the communication line control unit 12 performs exclusive control of the access right of the system bus control unit 13 and the three-bank memory 3 and then
The received broadcast data is written to the bank memory 3. Further, reference numeral 14 is a bank switching unit designating unit, and this bank switching unit designating unit 14 judges from the accessed address of the three-bank memory 3 which of the blocks, which is a unit for performing bank switching, is being accessed. The block number is output to the bank switching information memory 15 so as to prepare the bank switching information. It should be noted that the bank switching unit designating section 14 is not necessary when the whole is configured by one switching unit as described above.

On the other hand, the bank switching control unit 11 checks which one of the communication line control unit 12 and the system bus control unit 13 is accessing the three-bank memory 3, and normally terminates the reception.
It is checked whether 100 and the reception bank switching request 101 from the CPU 7 are output. If the normal reception end 100 is detected, the memory 31 of the 3-bank memory 3
Send a select signal to any of ~ 33. Also, CP
When the reception bank switching request 101 from U7 is detected, new bank switching information is created and the contents of the bank switching information memory 15 are updated.

Next, FIG. 5 shows the format of the bank switching information memory 15. This memory 15 is composed of bank switching state information 16 and the reception flag 17, and the bank switching state information 16
Indicates that the memories 31 to 33 of the three bank memory 3 correspond to the banks A to C in FIG. 2, respectively.

Note that the operation when transmitting data to another communication control device 5 is the same as the control method in the case of the conventional two-bank memory, assuming that bank C in FIG. 2 does not exist. Omitted.

As described above, in this embodiment, the memory capacity increases due to the use of the three-bank memory 3 and the bank switching information memory 15 and the like, and the operation of the bank switching control unit 11 becomes slightly complicated. There is no concern that the increase in memory capacity will be a major factor in increasing the cost of hardware against the background of the price decrease of the bank switching information memory 15 and the memory 31 actually selected.
The selection sequences of ~ 33 can be regarded as a kind of conversion table, and can be easily realized by a ROM or the like, so that the usefulness of the present invention is not impaired.

(Effects of the Invention) As described in detail above, according to the present invention, the three-bank memory is made to correspond to the data reception bank, the data update bank, and the data reference bank, respectively, and the data reception bank and the data update bank not referred to by the CPU. Is used to receive and update data, the CPU
Can output the reception bank switching request as necessary to always refer to the latest reception data in the data reference bank.

Therefore, when the communication control device is used in a distributed processing system or the like, there is no need for wasteful processing such that the CPU always outputs a switching request as in the conventional case, and the load on the CPU is reduced.
The processing capacity can be improved.

In addition, it is possible to shorten the delay time from when the data is received until the CPU can refer to the data as in the conventional case, and it is possible to improve the responsiveness.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a communication control device to which the present invention is applied, FIG. 2 is a conceptual explanatory diagram of a 3-bank memory, and FIG. 3 is a C diagram according to the timing of received data.
A timing chart for explaining data that can be referred to by a PU, FIG. 4 is a block diagram showing a detailed configuration of a communication control device, FIG. 5 is an explanatory diagram of a format of a bank switching information memory, and FIG. 6 is a conventional example. FIG. 7 is a block diagram of the communication control device shown, and FIG. 7 is a timing chart for explaining the data that can be referred to by the CPU according to the timing of the received data. 1 ... Communication control device, 3 ... 3 bank memory 31, 32, 33 ... Memory, 4 ... Communication line 7 ... CPU, A ... Data receiving bank B ... Data update bank, C ... Data reference bank

Claims (1)

[Claims] 1. A communication control device capable of transmitting / receiving data to / from another communication facility via a communication line and making it possible to refer to the received data by a request from a CPU, the reception in the communication control device. A data reception bank for storing reception data in the area, a data update bank for updating the latest reception data according to the reception timing of the reception data, and a data reference bank constantly referred to by the CPU are set, and The three memories provided in the reception area are made to correspond to the data reception bank, the data update bank, and the data reference bank alternately according to the reception timing, and the data update bank is set to the data update bank in response to the reception bank switching request from the CPU. The corresponding memory is switched to the data reference bank to make it correspond to the latest reception data in the memory. A method of controlling received data in a communication control device, characterized in that the data is referred to.