JPH04289468A - Method for testing lsi - Google Patents

Abstract

PURPOSE:To certainly identify the inferior place of an LSI without missing the place and to reduce the cost of an LSI test. CONSTITUTION:An input register 5 receiving the test pattern of a circuit 3 to be inspected, an output register 6 receiving the output of the operation result of the circuit 3 to be inspected, a comparator having the expected value at the time of the normal operation of the circuit 3 to be inspected and comparing said expected value with the content of the output register 6 and an encoder 8 outputting a code knowing the presence of an inferior place and the inferior place from the comparison result are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an improvement in an LSI testing method.

0002

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional LSI testing method. In the figure, 1 is an input register into which a test pattern is input from an external tester (not shown) via bus 2, 3 is a circuit under test to be tested, and 4 is a binary number obtained from the operation result of this circuit under test 3. This is an output data compression circuit that counts and outputs the number of "1"s.

Next, the operation of the LSI testing method with the above configuration will be explained. First, a test pattern of the circuit under test 3 and an expected value when the circuit under test 3 operates normally are prepared in advance in an external tester (not shown). When a test pattern is input from this external tester (not shown) to the input register 1 via the bus 2, the circuit under test 3 operates based on the contents of the input register 1. The results of this operation are compressed by the output data compression circuit 4, sent to an external tester via an external pin, and tested by comparing them with expected values when the circuit under test operates normally.

0004

[Problem to be solved by the invention] In the conventional LSI testing method, it is sufficient that the operation result of the circuit under test matches the number of binary 1s, so (A) there is an even number of defective locations. In other words, the expected value is "0" and the action result is "1", and the expected value is "1" and the action result is "0".
(B) To overlook defects when paired with
There were problems such as (C) the fact that even if it was found that there was a defect, the location of the defect could not be identified; and (C) expensive external testing was required.

[0005] The present invention is aimed at solving the above-mentioned problems.
The present invention provides an LSI testing method that can easily identify defective locations without overlooking defects in the circuit under test, even when the SI is installed in the system or with a hardware debugger.

[0006]

[Means for Solving the Problems] The LSI testing method according to the present invention includes a comparator that compares the operation result of the circuit under test with an expected value, and a code that can determine the presence or absence of a defective part and the defective part from the comparison result. It has an encoder that outputs .

[0007]

[Operation] According to the LSI testing method of the present invention, the LSI
The encoder of the internal comparator allows the defect location to be identified without overlooking the defect, and the LSI can be easily tested without an expensive external tester, thereby reducing the cost of LSI testing.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of an LSI testing method according to the present invention, and shows, as an example, a case where an external tester is not used. In the figure, 5 is an input register that receives a test pattern from a linear feedback register (not shown) that generates a test pattern, 6 is an output register that receives the output of the operation result of the circuit under test 3, and 7 is an input register that receives the test pattern from a linear feedback register (not shown) that generates a test pattern. A comparator that compares the expected value and the operation result when it operates; 8 is an encoder that outputs a code that indicates the presence or absence of a defective location and the location of the defect based on the comparison result output from the comparator 7; 9 is an encoder that outputs a code that indicates whether the circuit under test 3 is operating normally. A memory 10 is a test bus that stores the expected value when the test is performed.

Next, the operation of the LSI testing method with the above configuration will be explained. First, a test pattern of the circuit under test 3 is inputted to the input register 5 from a linear feedback register (not shown). Therefore, the circuit under test 3 operates based on the contents of the input register 5, and outputs the operation result to the output register 6. Then, the comparator 7 compares the contents of the output register 6 with the expected value stored in the memory 9, and encodes the comparison result with the encoder 7, and sends a code via an external pin that indicates the presence or absence of a defective part and the defective part. can be output.

FIG. 2 is a block diagram showing another embodiment of the LSI testing method according to the present invention, and shows a case where an external test is used as an example. In the figure, 11 is a bus that sends a test pattern to the input register 5. Next, the operation of the LSI testing method with the above configuration will be explained. First, an expected value in the case of normal operation is input in advance to the comparator 7 via the bus 11. Then, a test pattern of the circuit under test 3 is input from an external tester to the input register 5 via the bus 4. The circuit under test 3 operates based on the contents of the input register 5 and outputs the operation result to the output register 6. Then, the comparator 7 compares the contents of the output register 6 with the expected value, encodes the comparison result with the encoder 8, and outputs a code that indicates the presence or absence of a defective part and the defective part via an external pin. In the embodiment described above, external pins were used to output the code, but it goes without saying that the same effect can be achieved either by providing a test bus 10 exclusively for testing and outputting the code, or by outputting to the bus 11. Furthermore, it goes without saying that the input/output of test patterns, codes, and expected values can be performed in the same manner regardless of whether the transfer is performed using a shift register or a bus, regardless of the type of parallel or serial transfer.

[0011]

Effects of the Invention As described above in detail, according to the LSI testing method according to the present invention, the output of the LSI operation result based on the test pattern is compared with the expected value by the comparator, and the comparison result is encoded by the encoder. In addition, we have made it possible to output a code that shows the presence or absence of a defective part and the location of the defect without using an expensive external tester, so the defective part can be identified without overlooking the defective part of the LSI, reducing the cost of LSI testing. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of an LSI testing method according to the present invention.

FIG. 2 is a configuration diagram showing another embodiment of the LSI testing method according to the present invention.

FIG. 3 is a configuration showing a conventional LSI testing method.

[Explanation of symbols]

5 Input register 6 Output register 7 Comparator 8 Encoder 9. Memory 10 Test bus

Claims (1)

[Claims] Claim 1: An input register that receives a test pattern of the circuit under test, an output register that receives the output of the operation result of the circuit under test, and an expected value when the circuit under test operates normally, and the expected value and the output. A method for testing an LSI, comprising: a comparator that compares the contents of a register; and an encoder that outputs a code that indicates the presence or absence of a defective location and the location of the defect based on the comparison result.