JPH04307500A - Memory ic test device - Google Patents

Abstract

PURPOSE:To simplify the configuration and to reduce the size by deciding a nondefective parity pattern which corresponds to the address outputted from a pattern memory and an addition pattern and the corresponding pattern which is operated from the read out output of the memory to be tested via an exlusive logical sum processing. CONSTITUTION:Corresponding to the address from an address generating circuit 1, plural word unit non defective memory IC parity pattern DTP and sum patterns DTS are read out from a pattern memory 2. The output of an IC memory 4 to be tested is supplied in accordance with the address, an arithmetic circuit 9 operates a word unit parity pattern DP and a sum pattern DS. And patterns DTP and DD and DTS and DS are logically processed at exclusive adding circuits 8P and 8S of a decision circuit 8 and a normal/defective decision is performed. By using this two kinds test patterns only, the memory IC test device becomes simpler and smaller.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory IC testing device.

0002

2. Description of the Related Art In a conventional memory IC testing apparatus, for example, when performing a function test of a ROMIC under test (hereinafter abbreviated as DUT), a read output signal SR of a DUT 4 is converted into a digital signal by a comparator 5 as shown in FIG. After converting to DR, it is compared with the expected value data DT (hereinafter referred to as test pattern) from expected value memory 2 (hereinafter referred to as pattern memory).
This method determines that UT4 is a defective product.

[0003] Furthermore, in this test device, the pattern memory 2 stores ROM information, which is data of non-defective products of the DUT 4, as a test pattern DT, and in the function test, this test pattern DT is compared with the output of the DUT 4 for each address.

0004

[Problems to be Solved by the Invention] This conventional memory IC
In testing equipment, it is necessary to store the same data as the DUT's ROM information in the pattern memory as a test pattern in advance, so when measuring ROM products whose capacity has recently increased, (a) large capacity pattern memory is required. (b) It takes a long time to input the test pattern into the pattern memory, and (c) The media for supplying the test pattern also has a large capacity and becomes expensive. there were.

[0005]

[Means for Solving the Problems] The memory IC testing device of the present invention inputs an address signal to test a non-defective memory under test.
a pattern memory that outputs a parity pattern and an addition pattern of an address corresponding to the address signal of C; and a parity calculation circuit that inputs a digital signal corresponding to a read data signal from the memory IC under test and outputs a parity calculation signal. and an arithmetic circuit having an adder circuit that outputs sum data, a logic gate that inputs the parity pattern and the parity operation signal and outputs a first exclusive OR signal, and inputs the sum pattern and the sum data. The judgment circuit includes a logic gate that outputs a second exclusive OR signal, and a determination circuit that has an OR gate that inputs the first and second exclusive OR signals.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. The memory IC testing apparatus includes a pattern memory 2 which inputs an address signal DA from an address generation circuit 1 and outputs a parity pattern DTP and an addition pattern DTS of the corresponding address of a non-defective DUT 4, and a pattern memory 2 which receives an address signal DA from an address generation circuit 1 and outputs a parity pattern DTP and an addition pattern DTS of the corresponding address of a non-defective DUT 4. An arithmetic circuit 9 having a parity circuit 6 that inputs a digital signal DR and outputs a parity arithmetic signal DP, and an adder circuit 7 that outputs sum data DS, and a parity pattern DT.
Logic gate 8P outputs an exclusive OR signal XORP of P and parity output DP, logic gate 8S outputs an exclusive OR signal XORS of sum pattern TDS and sum data DS, and a sum signal O of these signals XORP and XORS.
and a determination circuit 8 having an OR gate that outputs R.

Address signal D from address generation circuit 1
A is input to the pattern memory 2, and the pattern memory 2 sequentially outputs test patterns corresponding to the addresses to the determination circuit 8. Also, the address signal DA is passed through the driver 3
The read signal SR is input to the UT4, and the read signal SR is output from the DUT4. This is converted into a digital signal DR by a comparator 5.

This read digital signal DR is converted into a parity signal DP for each address (word) in a parity calculation circuit 6, and is compared with a test pattern DT from the pattern memory 2 in a logic gate 8P of a determination circuit 8 to obtain defect information. Outputs XORP as

Furthermore, the output of the comparator 5 is sent to the adder circuit 7.
The read digital signal DR is added bit by bit in units of a fixed address section to obtain sum data DS. This sum data DS is compared with the test pattern DT from the pattern memory 2 by the logic gate 8S of the logic circuit 8 of the determination circuit 8, and a signal XORS is obtained as defect information. The sum data DS is calculated and compared for each fixed address section.

[0010] Even if either XORP or XORS of these defective information becomes defective, DUT4 is considered defective and OR
The gate OR outputs defect information ORF. The pattern memory 2 also stores parity data DP as a test pattern,
Sum data DS for each address section is stored in advance.

FIG. 2 is a diagram for explaining the operation of the blocks in FIG. 1. This is an example of performing a sum check in units of 4 words and a parity check in units of words of the DUT output data SR. In this case, the test pattern is parity pattern D
The capacity of the TP is 1/8 of the conventional pattern, and the sum data DTS is 1/4 of the capacity of the conventional pattern.In total, it is possible to measure the capacity of the pattern of the conventional pattern memory 2a by 3/8.

0012

[Effects of the Invention] As explained above, the present invention
Performs a word-by-word parity check of the output data from the MIC and a sum check for each multiple word to check whether the DUT is good or not.
Since defects are determined, there are two types of test patterns: parity data and sum data, which are significantly smaller than the test patterns of conventional methods. Therefore, (a) the pattern memory can be configured with a small capacity, making the system inexpensive; (b) the time required to input test patterns to the pattern memory is shortened; and (c) the test pattern supply medium is small. It has the effect of requiring only a small capacity and being simple.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the blocks in FIG. 1;

FIG. 3 is a block diagram of an example of a conventional memory IC testing device.

[Explanation of symbols]

1 Address generation circuit 2 Pattern memory 3 Driver 4 DUT 5 Comparator 6 Parity calculation circuit 7 Adder circuit 8 Judgment circuit 8P, 8S Exclusive OR circuit 9 Arithmetic circuit 10 Logical operation/judgment circuit

Claims (1)

[Claims] 1. A pattern memory that receives an address signal and outputs a parity pattern and an addition pattern of an address corresponding to the address signal of a non-defective memory IC under test, and corresponds to a read data signal from the memory IC under test. an arithmetic circuit having a parity arithmetic circuit that inputs a digital signal to output a parity arithmetic signal and an adder circuit that outputs sum data; , a logic gate that inputs the sum pattern and the sum data and outputs a second exclusive OR signal, and an OR gate that inputs the first and second exclusive OR signals. A memory IC testing device comprising: a determination circuit.