JP2994267B2 - Scan test equipment for semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a scan test apparatus for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional scan test apparatus for a semiconductor integrated circuit. Referring to FIG. 7, a semiconductor integrated circuit 701 of the conventional example has a test data input terminal (TS) 702 for externally inputting test data, a test mode switching signal, and a clock signal.
A test mode switching signal input terminal (MD) 703 and a clock input terminal (CK) 704 and a circuit under test (UTS
T) 706a, 706b, 706c, and a data selection circuit (SEL) 70 for selecting one of the two input data.
8aa, 708ab, ..., 708an, 708ba, 7
, 708bn and SELs 708aa, 708ab,..., In synchronization with the clock signal from CK704.
708an, 708ba, 708bb, ..., 708bn
Scan register (RE
G) 707aa, 707ab, ..., 707an, 707
, 707bb, and REG in the last stage
And a test result output terminal (OT) 705 for outputting a test result of the output of 707bn.

[0003] Each SEL selects either the output data of the preceding UTST or the output data of the preceding REG according to the test mode switching signal input to the MD 703.
That is, SEL 708aa selects one of the test data from TS 702 and the output data of UTST 706a, SEL 708ab selects one of the output data of REG 707aa and the output data of UTST 706a,
Hereinafter, similarly, each SEL performs a selection operation.

Next, the operation of the conventional example will be described.
First, in the SEL 708aa, a test mode switching signal to be input to the MD 703 is set so that the test data from the TS 702 is selected and applied to the REG 707aa.

At this time, the REG 707ab and the like at the subsequent stage are passed through the SEL 708ab and the like, respectively, and
Output data such as 7aa is applied.

Next, the test data input to the TS 702 is synchronized with the clock signal applied to the CK 704 by the RE.
G707aa,..., 707an are written one bit at a time.

[0007] Then, all REG707aa, ...,
When data writing to 707an is completed, each REG7
The data of 07aa, ..., 707an is converted to UTST706b.
, And all REGs 707ba, ..., 707bn
When the data writing to the REG 707b is completed,
, 707bn are input to the UTST 706c.

Next, in SEL708aa, UTS
A test mode switching signal to be input to the MD 703 is set so that the output data of T706a is selected and applied to the REG 707aa.

At this time, one clock signal is input to CK 704 and data from UTST 706a is
Write to aa.

[0010] Thereafter, in SEL708aa,
Select test data from TS702 and REG702a
A test mode switching signal to be input to the MD 703 is set so as to be input to a.

Next, the test result data written in the REG 707bn is output to the OT 705 in synchronization with the clock signal applied to the CK 704, and the TS 70
The test data input to 2 is set in the REG 707aa one bit at a time.

The test result output from the OT 705 is compared with expected value data outside the semiconductor integrated circuit 701,
The presence or absence of a failure in the semiconductor integrated circuit 701 is investigated.

As an example of a conventional technique for shortening the scan time, there is a "scan test apparatus" described in JP-A-63-157073.

FIG. 8 is a block diagram of an example of a conventional scan test apparatus, which is equivalent to the basic configuration diagram described in the above publication.

Referring to FIG. 8, an LSI 801 of the conventional scan test apparatus includes a plurality of scan registers FF1 ', FF2',
A plurality of scan chains 8 composed of FFs 3 ',.
, 805 and the circuit under test (UTS) connected to the input / output terminal of the scan register of each scan chain.
T) 806,..., 814 and test data input terminals (T
S) 815,..., 818 and test result output terminal (OT)
819,..., 822.

The operation of one scan chain in this conventional example is the same as the operation described with reference to FIG. 7, and the test time is reduced by configuring a plurality of scan chains in the LSI 801.

[0017]

However, the conventional scan test apparatus has a problem that the amount of test data is large because the data set in the scan register is handled without compression.

Further, since data is written into the scan register one bit at a time, there is a problem that this writing takes time.

An object of the present invention is to provide a scan test apparatus for a semiconductor integrated circuit in which the test time of the semiconductor integrated circuit is reduced and the number of test data is reduced.

[0020]

According to the present invention, a test data input means for inputting compressed test data, a test data restoring circuit for restoring test data from the compressed test data from the test data input means, A scan test apparatus for a semiconductor integrated circuit having a test result compression circuit for compressing and outputting test result data from a circuit under test.
Dividing the circuit under test into a plurality of circuits under test,
Test data from a road and the test data restoration circuit
Select one of the test data from
A plurality of selection circuits for each circuit and the plurality of selection circuits
Write the output data of each of the plurality of
A plurality of scan registers for each circuit;
The test data written to the scan registers
Each output from the selection circuit applied to the circuit under test
Testing means for testing the circuit under test;
Selection circuit selects test data of the test data restoration circuit.
The plurality of scans from the test data restoring circuit
In synchronization with the parallel storage in the
The output of the plurality of scan registers is output to the test result compression circuit.
Synchronous readout means for reading out force data in parallel;
The test data of the test data restoration circuit is stored in the plurality of scans.
When the data has been stored in all the register registers, the selection circuit is selected.
The test result data from the circuit under test
Simultaneous write method to write to a number of scan registers at once
And a scan test apparatus for a semiconductor integrated circuit characterized by having a step .

[0021]

Further, an expected value data ROM in which expected value data is written, and an expected value for comparing test result compressed data from the test result compression circuit with the expected value data read from the expected value data ROM. A scan test apparatus for a semiconductor integrated circuit, comprising: a verification circuit;

[0023]

[0024]

Next, the present invention will be described with reference to the drawings.

First, the operation of the present invention will be described.
In the present invention, since the compressed test data is restored by the test data restoration circuit, the test data input to the semiconductor integrated circuit can be compressed.

Further, since the test result is compressed by the test result compression circuit, it is possible to compress the expected value data and reduce the data amount.

Furthermore, since data is written to a plurality of scan registers at once, the time for writing data to all scan registers can be greatly reduced.

FIG. 1 is a block diagram showing a first embodiment of a scan test apparatus for a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a scan register group in FIG.

Referring to FIG. 1, a semiconductor integrated circuit 101 of the present embodiment has a test data input terminal (TS) for inputting test data (compressed test data), a test mode switching signal, and a clock signal which are externally compressed. 10
2. a test mode switching signal input terminal (MD) 103 and a clock input terminal (CK) 104;
ST) 112a, 112b, 112c and a data selection circuit (SEL) 1 for selecting one of two input data
Scan register group (RGG) 1 into which data selected by SELs 109a and 109b are written in synchronization with clock signals from 09a and 109b and CK104, respectively.
, 111x, and RGG111a,
All scan registers (REG) 115a, 115 in 111b, 111x (RGG 111 shown in FIG. 2)
b,..., 115n, the test data restoring circuit (RE
S) 106, a test result selection circuit (RSL) 114 for selecting and outputting test results written in one RGG of the RGGs 111, and a test result written in the RGG selected by the RSL 114 for x minutes. A test result compression circuit (RCP) 107 for compressing to 1
Output terminal (OT) 1 for outputting test results from
05.

The SEL 109a selects either the test data 108 from the RES 106 or the output data of the UTST 112a, and the SEL 109b selects the test data 10
8 and the output data of the UTST 112b.

Each of the RGGs 111a, 111b, 11
1x (RGG 111 shown in FIG. 2) is a clock signal 113
In synchronization with the test data 108 and the UTST 112a,
A plurality of scan registers (REG) 115a, 115 for writing a plurality of test results of 112b, 112c, respectively.
, 115n, and a plurality of selection data 117a, 1 from each of the SELs 109a, 109b (SEL 109 shown in FIG. 2) according to the write instruction signal 110 from the RES 106.
, 117n or REGs 115a, 115
, 115n, held data selection circuits (SL) 116a, 116b,.
116n.

Now, all the Rs included in the semiconductor integrated circuit 101
Assuming that a data compression ratio obtained by compressing data to be set in the EG is “x”, the number of REGs included in one RGG is “y”, and the number of REGs included in the semiconductor integrated circuit 101 is “z”, RGG in the semiconductor integrated circuit 101
Becomes “x”, and REG included in one RGG
The number “y” = “z” / “x”.

Here, when “z” is not an integral multiple of “x”, the value of “y” is rounded up to the decimal point, and “x” is rounded up.
Only the number of REGs included in the RGG is a fraction thereof.

For example, when the number of REGs included in the semiconductor integrated circuit 101 is “z” = 23, and the data compression ratio “x” = 5
Then, the number of RGGs becomes 5, the number of REGs contained in one RGG becomes 5 (23/5 = rounded up to the decimal point of 4.6), and the number of REGs contained in the first to fourth RGGs Is "5", and the number included in the fifth RGG is "3".

Next, the operation of the present embodiment will be described with reference to FIGS. 1, 2 and 3. FIG. 3 is a time chart for explaining the operation in FIG.

First, RES10 is selected in SEL109a.
6 selects the test data 108 output from RGG1
A test mode switching signal to be input to the MD 103 is set so as to be applied to 11a (in FIG. 3, the signal level of the test mode switching signal is set to "0").

Next, data obtained by compressing test data to be set in all REGs included in the semiconductor integrated circuit 101 into 1 / x (“y” bits) is input to the TS 102.

Regarding this test data compression method, when the number “z” of all REGs included in the semiconductor integrated circuit 101 is not an integral multiple of the data compression rate “x”, the smallest integer “x” exceeding the total number of REGs The surplus data (all "0" in the example of FIG. 3) is added and compressed so that the number becomes double.

For example, if “z” = 23 and “x” = 5, the surplus data is set so that the number of bits of the test data is larger than “23” and becomes “25” which is a minimum multiple of “5”. Is compressed by adding 2 bits.

The data applied to TS102 is CK10
In addition to being taken in by the test data restoring circuit 106 in synchronization with the clock signal 113 applied to No. 4, the test data is restored in “x” times by “y” bits.

First, the test data 108 to be set in the first RGG 111a is restored with the clock signal 113 following the clock signal 113 when the test data applied to the TS 102 is fetched, and a write instruction is issued to the RGG 111a. The signal 110 is output.

RGG1 receiving write instruction signal 110
11 (for example, RGG 111a) are SL 116a,.
16n, the selected data 117a,..., 117n selected by the SELs 109a, 109b are transferred to the REG 115.
, 115n. Other RGG111
In SL, b,..., 111x return the data written in the REG to the REG and hold the data.

At the next clock signal 113, the RGG 111a
Write the test data 108 to the REG in
6, the second RGG 111 is output from the clock signal 113.
b and RGG1
A write instruction signal 110 is output to 11b.

In the same manner, this operation is repeated until the test data 108 has been written to all the RGGs.

Then, test data 10 is added to all RGGs.
8 is completed, the test data 108
Apply to TST112a. Next, the test result output from the UTST 112a is selected in the SEL 109a, and the MD10 is selected so that it is applied to the RGG 111a.
3 is set (the signal level of the test mode switching signal is set to "1" in FIG. 3).

At the same time, the RES 106 outputs a write instruction signal 110 to all the RGGs 111a, 111b, 111x, selects the selected data selected by SEL in SL, and applies the selected data to REG.

Thereafter, the clock signal 113 is applied to the CK 104.
Is input once and the test results output from the UTST 112b are written to all REGs, and then SEL10
At 9b, a test mode switching signal to be applied to the MD 103 is set so that the test data 108 from the RES 106 is selected and applied to the RGG 111b.

Next, in the RCP 107, all the R
The test result written in the EG is output to the clock signal 113.
In synchronization with “x”, “y” bits are divided into “x” times and compressed to “x” times, the next compressed test data is taken in from TS 102, restored by RES 106, and test data 108 is transferred to RGG 111. Write in.

First, the test result written in the first RGG 111a is selected by the RSL 114 by the clock signal 113 for taking in the test data from the TS 102, and the RCP 114 selects the test result.
107.

At the next clock signal 113 (ie, the output timing of the first write instruction signal 110), the RGG 11
The test result written in 1a is taken into the RCP 107, and the test result written in the second RGG 111b is selected by the RSL 114 and applied to the RCP 107.

At the next clock signal 113 (ie, the output timing of the second write instruction signal 110), the RGG 11
The test result written in 1b is taken into the RCP 107, and the test result written in the third RGG is selected by the RSL 114 and applied to the RCP 107.

At this time, the RCP 107
1a and the test result (“y” bit) received from RGG1
Then, the data is multiplied by the test result (“y” bit) received from 11b and compressed to produce “y” bit compressed data 1.

Next, when the test result from the third RGG is taken in, the compressed data 1 and the third RGG
And the test result (“y” bit) received from the second device to generate compressed data 2.

The same operation is repeated until the test result written in the x-th RGG 111x is fetched.

When the total number of REGs “z” is not an integral multiple of the data compression rate “x”, the x-th RGG 111
The test data received from x is compressed with the same surplus data as the test data.

When the test result is output from the OT 105, the test result data is compared with the expected value data to test whether the semiconductor integrated circuit 101 has a failure.

FIG. 4 is a block diagram showing a second embodiment of the scan test apparatus for a semiconductor integrated circuit according to the present invention, and FIG. 5 is a block diagram showing an example of the test data automatic generation circuit in FIG.

Referring to FIG. 4, the semiconductor integrated circuit 401 of the first embodiment is replaced with the semiconductor integrated circuit 101 of the first embodiment.
1 are given the same reference numerals as in FIG.

That is, in the present embodiment, the TS in FIG.
It has a configuration in which 102 is deleted and the RES 106 is replaced with an automatic test data generation circuit (DTG) 402.

Referring to FIG. 5, DTG 402
Are "y" registers (RG) 404a, 404b,
, 404y connected in series (SHT
R) 403, an EX-OR circuit (EXOR) 405 that receives an output signal of an arbitrary RG 404i as an input, and a counter (CNT) 406 that counts from “0” to “x−1”.
And a decoder (DCR) 407 that decodes the count value of the CNT 406 and generates the write instruction signal 110. Each time the clock signal 113 is input, “y” bit data other than all “0” is arbitrarily changed. Can be generated.

Next, the operation of this embodiment will be described. In the above-described first embodiment, the test data 108 is restored by the RES 106 based on the data input from the TS 102 and supplied to the RGG. However, in the semiconductor integrated circuit of the second embodiment, the test data 108 is generated by the DTG 402. The functions of the other parts are the same as those of the first embodiment except that they are supplied to the RGG, and a detailed description thereof will be omitted.

FIG. 6 is a block diagram showing a third embodiment of the scan test apparatus for a semiconductor integrated circuit according to the present invention.

Referring to FIG. 6, the semiconductor integrated circuit 601 of the first embodiment is replaced with the semiconductor integrated circuit 101 of the first embodiment.
1 are given the same reference numerals as in FIG.

That is, the semiconductor integrated circuit 6 of the present embodiment
01 is an expected value data ROM (ROM) for storing expected value data in the semiconductor integrated circuit 101 in FIG.
602, test results compressed by RCP107 and ROM
An expected value matching circuit (CM) that determines whether or not the semiconductor integrated circuit 601 has a failure by checking the expected value data from the
P) 603, and the RCP 107
The expected value data is extracted from the ROM 602 by the expected value address signal 604 indicating the storage location of the expected value data stored in the OM 602.

Next, the operation of the third embodiment will be described. The operation up to the compression of the test result is the same as in the first embodiment, and a description thereof will be omitted.

The present embodiment is different from the first embodiment in that the expected value is compared in the CMP 603 and the result of the comparison is output to the OT 105.

First, expected value data is written in the ROM 602 in advance. The RCP 107 outputs an expected value address signal 604 to the ROM 602 every time the compression of the test result is completed, and extracts the expected value data of the address.

The CMP 603 collates the expected value data from the ROM 602 with the test result output from the RCP 107, and outputs the determination result from the OT 105.

[0069]

As described above, the present invention provides a test data input means for inputting compressed test data, a test data restoring circuit for restoring test data from the compressed test data from the test data input means, and a test result. And a test result compression circuit for compressing and outputting a plurality of scan registers for selecting one of the test result data from the circuit under test and the test data from the test data restoring circuit and writing them at a time. By having
Further, an expected value data ROM for writing expected value data, and an expected value matching circuit for comparing the test result compressed data from the test result compression circuit with the expected value data read from the expected value data ROM are provided. Further, the compression test data input means is either a test data automatic generation circuit for automatically generating compression test data in the semiconductor integrated circuit or a test data input circuit provided outside the semiconductor integrated circuit. As a result, the test data can be set in "x" scan registers for all the scan registers at a time, so that the test time can be reduced to 1 / x that of the conventional device. And the test data compressed to 1 / x in the semiconductor integrated circuit can be restored, and the test result can be reduced to 1 / x It is possible to shrinkage, has the effect that it is possible to reduce the test data expected value data to the first x minutes.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a scan test apparatus for a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a scan register group in FIG.

FIG. 3 is a time chart for explaining the operation in FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the scan test apparatus for a semiconductor integrated circuit according to the present invention.

FIG. 5 is a block diagram illustrating an example of an automatic test data generation circuit in FIG. 4;

FIG. 6 is a block diagram showing a third embodiment of the semiconductor integrated circuit scan test apparatus of the present invention.

FIG. 7 is a block diagram illustrating an example of a conventional scan test apparatus for a semiconductor integrated circuit.

FIG. 8 is a block diagram illustrating an example of a conventional scan test apparatus.

[Explanation of symbols]

101, 401, 601, 701 Semiconductor integrated circuit 102, 702, 815, ..., 818 Test data input terminal (TS) 103, 703 Test mode switching signal input terminal (M
D) 104, 704 Clock input terminals (CK) 105, 705, 819, ..., 822 Test result output terminal (OT) 106 Test data restoration circuit (RES) 107 Test result compression circuit (RCP) 109a, 109b, 707aa, 707ab , ..., 7
07an, 707ba, 707bb, ..., 707bn
Data selection circuit (SEL) 110 Write instruction signal 111, 111a, 111b,..., 111x Scan register group (RGG) 112a, 112b, 112c, 706a, 706b,
706c, 806,..., 814 circuit under test (UTS
T) 113 clock signal 114 test result selection circuit (RSL) 115a, 115b, ..., 115n, 707aa, 70
7ab, ..., 707an, 707ba, 707bb,
, 707bn Scan registers (REG) 116a, 116b, ..., 116n Holding data selection circuit (SL) 117a, 117b, ..., 117n Selection data 402 Automatic test data generation circuit (DTG) 403 Shift register (SHTR) 404a, 404b, ..., 404y register (R
G) 405 EX-OR circuit (EXOR) 406 Counter (CNT) 407 Decoder (DCR) 602 ROM for expected value data (ROM) 603 Expected value matching circuit (CMP) 604 Expected value address signal 801 LSI 802,. chain

Continuation of the front page (56) References JP-A-7-98356 (JP, A) JP-A-6-186295 (JP, A) JP-A-7-294606 (JP, A) JP-A-4-165644 (JP) JP-A-57-64991 (JP, A) JP-A-63-317787 (JP, A) JP-A-7-198791 (JP, A) JP-A-5-134007 (JP, A) 6-130135 (JP, A) JP-A-2-22579 (JP, A) JP-B-6-60933 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01R 31/28 -31/3193 G06F 11/22-11/277

Claims (2)

(57) [Claims] 1. Test data input means for inputting compressed test data, a test data restoration circuit for restoring test data from the compressed test data from the test data input means, and compression of test result data from a circuit under test. Of a semiconductor integrated circuit having a test result compression circuit
In the testing device, the circuit under test is divided into a plurality of circuits under test,
Test result data from the circuit and the test data
Select one of the test data from the
Writing a plurality of selection circuits for each test circuit and output data from each of the plurality of selection circuits.
A plurality of scan registers for each of the plurality of circuits under test.
And test data written to the plurality of scan registers.
Is applied to the circuit under test, and
Output means for testing the circuit under test, and the selecting circuit outputs test data of the test data restoring circuit.
When selected, the plurality of test data
Synchronous with storing data in parallel in the scan register
The plurality of scan registers in the test result compression circuit.
Reading means for reading output data of the data in parallel
And transmitting the test data of the test data restoring circuit to the plurality of scans.
When the data has been stored in all of the scan registers, the selection circuit
Select the test result data from each circuit under test
Simultaneous write to multiple scan registers at once
And a scan test apparatus for a semiconductor integrated circuit. 2. An expected value data ROM in which expected value data is written, and an expected value for comparing test result compressed data from the test result compression circuit with the expected value data read from the expected value data ROM. 2. The scan test apparatus for a semiconductor integrated circuit according to claim 1, further comprising a verification circuit.