JPH04288653A - Microcomputer - Google Patents

Abstract

PURPOSE:To shorten the DMA transfer time of a microcomputer having the DMA transfer function. CONSTITUTION:A DMAC consists of a main DMAC 5 and a local DMAC 6, and the DMA transfer address of a memory 2 is designated through a main address bus 21 by the main DMAC 5, and the DMA transfer address or an I/O 3 us designated through a local address bus 22 by the local DMAC 6 synchronously with this operation. Since DMA transfer which requires two memory cycles in the conventional method is performed in one memory cycle without temporarily storing data in an internal register or the like, the DMA transfer time is shortened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a DMA function for directly transferring data between memory and peripheral devices.

0002

2. Description of the Related Art FIG. 3 is a block diagram showing the inside of a conventional microcomputer having a DMA function.

As shown in the figure, a CPU 1, a memory 2,
An input/output device 3 (hereinafter referred to as "I/O") and a DMA controller 4 (hereinafter referred to as "DMAC") are commonly connected to a data bus 11 and an address bus 12, respectively. DMAC4 follows the instructions from CPU1.
Controls MA transfer.

In such a configuration, DMA transfer of data from the I/O 3 to the memory 2 is performed as shown below.

First, the CPU 1 outputs a control signal S1 instructing DMA transfer to the DMAC 4. Furthermore, CPU1
sequentially outputs the transfer destination address of the memory 2 and the transfer source address of the I/O 3 to the DMAC 4 via the address bus 12.

[0006] Upon receiving this, the DMAC 4 outputs the transfer source address to the I/O 3 via the address bus 12, and then
Data output from I/O 3 is taken into an internal register via data bus 11.

After that, the transfer destination address is output to the memory 2 via the address bus 12, and then the data stored in the internal register of the memory 2 is transferred to the transfer destination address of the memory 2 via the data bus 11.

On the other hand, DMA transfer from memory 2 to I/O 3 is performed in the same way, after the data stored at the transfer source address in memory 2 is transferred to the internal register of DMAC 4,
The data stored in the internal register of MAC4 is output to the transfer destination address of I/O3.

In this way, by providing the DMA function for direct data transfer between the memory 2 and the I/O 3 under the control of the DMAC 4, the CPU 1 can perform other processing during that time, so the effective use of the CPU 1 can be reduced. It can be used.

0010

[Problems to be Solved by the Invention] A conventional microcomputer having a DMA function is configured as described above, and DMA transfer between the memory 2 and I/O 3 is performed by first transferring data from the transfer source to the internal register of the DMAC 4. After that, D
Data was transferred from the internal register of the MAC4 to the transfer destination in two memory cycles.

[0011] During execution of a DMA transfer, the data bus 11 is occupied, and if the DMA transfer time is long, the CPU 1 cannot perform processing using the data bus 11 during that time, resulting in a problem that the processing speed of the entire microcomputer system becomes slow. There was a point.

The present invention was made to solve the above problems, and an object of the present invention is to provide a microcomputer in which the DMA transfer time is shortened.

[0013]

[Means for Solving the Problems] A microcomputer according to the present invention has a DMA function for directly transferring data between a memory and a peripheral device, and has a DMA function that is commonly connected to a CPU, the memory, and the peripheral device. data bus,
a first address bus connected to the memory; a second address bus connected to the peripheral device independently of the first address bus; a first DMA control unit that specifies the address of the memory via the second address bus in synchronization with the address specification of the first DMA control unit according to instructions from the CPU; and a second DMA control section that performs specification.

[0014]

[Operation] In this invention, the first DMA control section
The memory is addressed via the first address bus according to the instructions of the PU, and the second DMA controller
Because the addressing of the peripheral device is performed via the second address bus in synchronization with the addressing of the A control unit,
During DMA transfer, addresses can be specified for memory and peripheral devices at the same time.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the internal structure of a microcomputer having a DMA transfer function, which is an embodiment of the present invention.

As shown in the figure, a CPU 1 and a memory 2
are commonly connected to the data bus 11 and the main address bus 21, respectively. The main DMAC 5 is connected to the main address bus 21.

On the other hand, I/O 3 and local DMAC 6 are commonly connected to data bus 11 and local address bus 22, respectively. Note that, unlike usual, the data bus 11 is connected to the address terminal of the local DMAC 6, and the data bus 11 is unidirectional (data bus 11 → local DMAC 6).
Only 6) is valid.

[0018] Main DMAC 5 and local DMAC 6
follow instructions from CPU 1 and cooperate with each other to store memories 2 and I.
Controls DMA transfer between /O3. At this time, memory 2
Addressing to I/O3 is done by main DMAC 5 via main address bus 21, and addressing to I/O3 is done by local DMAC 6 via local address bus 21.
This is done in synchronization with the address designation to the memory 2 by the main DMAC 5 via the main DMAC 2.

In such a configuration, DMA transfer of data from the I/O 3 to the memory 2 is performed as shown below.

First, the CPU 1 sends a control signal S1 instructing DMA transfer to the main DMAC 5 and the local DMAC 6.
Output to. Furthermore, CPU1 has main address bus 2.
It outputs the transfer destination address of the memory 2 to the DMAC 5 via the data bus 11, and outputs the transfer source address of the I/O 3 to the local DMAC 6 via the data bus 11.

Upon receiving this, the main DMAC 5 outputs the transfer destination address to the memory 2 via the address bus 21.
In synchronization with this, the local DMAC 6 outputs the transfer source address to the I/O 3 via the local address bus 22.

As a result, the DMA between memory 2 and I/O3
At the time of transfer, the transfer source address of I/O3 and the transfer destination address of memory 2 are specified at the same time, so
The data output from the I/O 3 is transferred to the destination address of the memory 2 in one memory cycle via the data bus 11 without being temporarily transferred to the internal registers of the main DMAC 5 or the local DMAC 6.

Similarly, DMA transfer from memory 2 to I/O 3 is performed by main DMAC 5 and local DMAC 6.
Under the control of the main DMAC 5, the transfer source address to the memory 2 is specified via the main address bus 21, and in synchronization with this, the transfer destination address to the I/O 4 is specified by the local DMAC 6 using the local address. By performing this via the bus 22, data stored at the transfer source address in the memory 2 can be input/output in one memory cycle.
It will be forwarded to the forwarding address of 3.

In this way, by performing DMA transfer of data between the memory 2 and I/O 3 under the control of the main DMAC 5 and the local DMAC 6, one memory can be transferred without temporarily storing it in a register etc. inside the DMAC. DMA transfer can be performed by recycling. As a result, the DMA transfer time can be reduced by one memory cycle, and the processing speed of the entire microcomputer system can be improved by reducing the time during which the data bus 11 is occupied by DMA transfer.

FIG. 2 shows a DMA which is another embodiment of the present invention.
FIG. 2 is a block diagram showing the internal configuration of a microcomputer with a transfer function.

As shown in the figure, CPU 1 and memory 2
are commonly connected to the main data bus 13 and main address bus 21, respectively. And the main DMA
C5 is connected to the main address bus 21.

On the other hand, I/O 3 and local DMAC 6 are commonly connected to local data bus 14 and local address bus 22, respectively. In addition, local DM
A local data bus 14 is connected to the address terminal of AC6, and only one direction (local data bus 14→local DMAC6) is valid.

A bus switch 15 is provided between the main address bus 13 and the local address bus 14. When this bus switch 15 is turned on, the configuration can be equivalent to that shown in FIG. 1.

On the other hand, by setting the bus switch 15 to a non-conducting state, it is possible to make the data bus in addition to the address bus independent between the memory 2 side and the I/O 3 side.
/If there is a sub CPU on the O3 side, the main CPU
The address bus and data bus can be used independently by U1 and the sub CPU, thereby improving the usage efficiency of the microcomputer system.

[0030]

As explained above, according to the present invention, the first DMA control section specifies the address of the memory via the first address bus, and the second DMA control section specifies the address of the memory via the first address bus. Since the addressing of the peripheral device is performed via the second address bus in synchronization with the addressing of the memory by the DMA control unit, the addressing of the memory and the peripheral device can be done simultaneously during DMA transfer.

As a result, DM between memory and peripheral devices can be performed without intermediate transfer to a temporary storage device such as a register.
Since the A transfer is performed in one memory cycle via the data bus, the DMA transfer time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of a microcomputer having a DMA transfer function, which is an embodiment of the present invention.

FIG. 2 is a block diagram showing the internal configuration of a microcomputer having a DMA transfer function, which is another embodiment of the present invention.

FIG. 3 is a block diagram showing the internal configuration of a conventional microcomputer with a DMA transfer function.

[Explanation of symbols]

1 CPU 2. Memory 3 I/O 5 Main DMAC 6 Local DMAC 11 Data bus 13 Main data bus 14 Local data bus 15 Bus switch 21 Main address bus 22 Local address bus

Claims (1)

[Claims] 1. A microcomputer having a DMA function for directly transferring data between a memory and a peripheral device, the microcomputer comprising a CPU, a data bus commonly connected to the memory and the peripheral device, and a data bus connected to the memory. a second address bus connected to the peripheral device independently of the first address bus;
a first DMA control unit that specifies an address of the memory via the first address bus in accordance with an instruction from the CPU; a second DMA control unit that specifies the address of the peripheral device via a second address bus.