JPH04287966A - Semiconductor ic - Google Patents

Abstract

PURPOSE:To reduce the delay time of an output signal by the variation of the value of a variable resistance, which is disposed in a semiconductor IC for draining electric charges from a base, in response to an output electric potential. CONSTITUTION:P-channel MOS transistors 6 are connected in parallel with a source terminal 10, and the gates of these transistors are connected to a first input terminal 4 and a second input terminal 5, respectively. N-channel MOS transistors 7 are connected in series, and the gates of these transistors are connected to the input terminals 4 and 5, respectively. A variable transistor 3 is connected between the P-channel MOS transistor pairs 6 and the N-channel MOS transistor pairs 7. An output, from the emitter of an output bipolar transistor 8, is supplied to the control electrode of the variable resistance 3 through an inverter 7, thereby varying the value of the variable resistance 3. This results in the reduction of a delay time at the leading and trailing edges of an output signal.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, it relates to a BiCMOS type semiconductor integrated circuit.

0002

2. Description of the Related Art A conventional semiconductor integrated circuit includes a CMOS circuit section 1 constituting a CMOS logic gate, as shown in FIG.
A BiCMOS circuit is constructed by combining a bipolar circuit section 2 having a base charge extraction resistance element between a base and an emitter for driving an output load.

[0003] This BiCMOS semiconductor integrated circuit has a first
2, including a P channel MOS transistor 6 and an N channel MOS transistor 7 connected to the input terminal 4 and the second input terminal 5 of the It constitutes an input NAND logic gate. here,
When “L” level is input to either one of the first input terminal 4 and the second input terminal 5, or
When “L” level is input to both, the two Ps connected to the gate from the first input terminal 4 and the second input terminal 5
At least one of the channel MOS transistors 6 is turned on, and the transistor 2 connected to the input terminal
When at least one of the two N-channel MOS transistors 7 is turned off, current first flows from the power supply terminal 10 through the P-channel MOS transistor 6 and the resistor 9, which are turned on, and the output load capacitance 1
Start charging 1. Next, due to the current flowing through the resistor 9,
Approximately 0 between the base and emitter of bipolar transistor 8
．． When a potential difference of 7V is generated, the bipolar transistor 8 is turned on for the first time, and the output load capacitor 11 is rapidly charged using the large driving ability of the bipolar transistor, and the output rises to the "H" level. In addition, the first input terminal 4
Considering the case where "H" level is input to both input terminals 4 and 5, the P channel MOS transistors 6 connected to the gates from the two input terminals 4 and 5 are both turned off, and the two input terminals 4 and 5 are turned off. Both N-channel MOS transistors 7 connected from 5 to the gate are turned on. The charge accumulated in the base of the bipolar transistor 8 is extracted through the resistor 9 and the N-channel MOS transistor 7, so that the bipolar transistor 8 is completely turned off, and then the output load capacitor 11
By extracting the accumulated charge through N-channel MOS transistor 7, the output drops to the "L" level. By performing such circuit operation, the desired 2
It was supposed to obtain a logic circuit with input NAND.

0004

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit, a resistor is used as an element for extracting the base charge, so if this resistance value is large, it takes time to extract the base charge, so the bipolar The transistor is slow to turn off, and the output to the "L" level is slow. Furthermore, if the resistance value is small, it takes time for the potential difference between the base and the emitter to reach about 0.7V, and the output becomes slow to reach the "H" level. In this way, from “L” level to “H”
If the delay time for changing from "H" level to "L" level is made faster, the delay time for changing from "H" level to "L" level increases, and if the delay time for changing from "H" level to "L" level is made faster, from "L" level to " There is a problem in that the delay time for changing to the H'' level increases.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes a P-channel MOS transistor and an N-channel MOS transistor constituting a CMOS logic gate, a bipolar transistor whose base is connected to the drain of the P-channel transistor, and a bipolar transistor whose base is connected to the drain of the P-channel transistor. A resistor element for extracting base charge of the bipolar transistor that is connected between the P-channel transistor and the N-channel transistor and whose resistance value is varied by the potential of the control electrode, and a control electrode of the resistor element that is connected to the emitter output signal of the bipolar transistor. and an inverter that applies a potential to.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

As shown in FIG. 1, a P-channel MOS transistor 6 has a gate connected to a first input terminal 4 and a second input terminal 5 and is connected in parallel to a power supply terminal 10; N-channel MOS connected in series
A transistor 7, a variable resistor 3 for extracting base charge connected between the P-channel MOS transistor 6 and the N-channel MOS transistor 7, a bipolar transistor 8 connected to the connection point between the P-channel MOS transistor and the variable resistor 3, and a bipolar It has an inverter 17 that applies the output signal of the transistor 8 to the variable resistor 3 to control the resistance value of the variable resistor 3, and an output load capacitor 11, and is a 2-input NAND.
Configure logic gates.

FIG. 2 is a sectional view showing an example of a variable resistor for extracting base charges used in the present invention.

As shown in FIG. 2, the P layer provided in the N-type layer 13
type diffusion layer 14 , a silicon oxide film 15 provided on the surface including the P type diffusion layer 14 , a control electrode 16 provided on the silicon oxide film 15 on the P type diffusion layer 14 , and a control electrode 16 provided on the silicon oxide film 15 on the P type diffusion layer 14 . The wiring 12 is connected to the P-type diffusion layer 14 through the openings provided in the silicon oxide film 15 at both ends, and by changing the potential of the control electrode 16, the P-type diffusion immediately below the control electrode 16 is The spread of the depletion layer of the layer 15 is changed, so that when the potential of the control electrode 16 is at a low level, the resistance value is made small, and when the potential of the control electrode 16 is at a high level, the resistance value is made large. When a resistor having the characteristics described above is used, when the output level of the circuit is "H", the potential of the control electrode 16 goes to a low level via the inverter 17, and the variable resistor 3 takes a small resistance value. Therefore, the next time the output level is about to change to "L", the base charge can be quickly extracted, and the output level can be quickly changed to "L".
Conversely, when the output level of the circuit is "L", the control electrode 16 goes to a high level via the inverter 17, and the variable resistor 3 takes on a large resistance value.For this reason, the next output When the level is about to change to “H”,
A potential difference of about 0.7V can be quickly applied between the base and emitter, and the output level can be set to "H" quickly.

[0011]

[Effects of the Invention] As explained above, the present invention is capable of reducing the delay time of an output signal by changing the resistance ground of a variable resistor for extracting base charges provided in a semiconductor integrated circuit according to the output potential. have an effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a sectional view showing an example of a variable resistor for base charge extraction used in the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 CMOS circuit section 2 Bipolar circuit section 3 Variable resistor 4 First input terminal 5 Second input terminal 6 P-channel MOS transistor 7 N
Channel MOS transistor 8 Bipolar transistor 9 Resistor 10 Power supply terminal 11 Output load capacitance 12 Wiring 13 N-type layer 14 P-type diffusion layer 15 Silicon oxide film 16 Control electrode 17 Inverter

Claims (1)

[Claims] 1. A P-channel MOS transistor and an N-channel MOS transistor constituting a CMOS logic gate, a bipolar transistor whose base is connected to the drain of the P-channel transistor, and a bipolar transistor connected between the P-channel transistor and the N-channel transistor. a resistance element for extracting base charge of the bipolar transistor whose resistance value is varied by the potential of a control electrode;
A semiconductor integrated circuit comprising: an inverter that applies a potential to a control electrode of the resistor element based on an emitter output signal of the bipolar transistor.