JPH04282177A - Microcomputer for game machine control - Google Patents

Abstract

PURPOSE:To prevent inconvenience to operate a game machine 21 for microcomputer control delivered in a game shop 24 by a malfeasant program other than an acceptable program from occurring. CONSTITUTION:A means 62 to decide the normal/defective condition of read-only memory 10c in which a control program to control the game machine is stored and packaged is provided at a microcomputer 23 for game control. When a prescribed condition is satisfied (for example, a power source is applied), it is decided whether or not the control program stored in the read-only memory 10c is a proper program by the normal/defective condition decision means 62, and ordinary control is performed on the game machine only when it is decided that the program is the proper one.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for controlling gaming machines such as pachinko gaming machines, arranged pachinko gaming machines, and slot machines.

0002

[Prior Art] Conventionally, a game machine control microcomputer program for controlling a game machine is developed by a development and manufacturing company and stored in the read-only memory (ROM) of the microcomputer. Take a test conducted by a third-party organization to determine whether or not you pass a certain standard. Only microcomputers with read-only memory that store programs that have passed tests by third-party organizations are installed in gaming machines and delivered to gaming parlors. Only gaming machines that allow players to play games will be installed.

0003

[Problem to be Solved by the Invention] However, even if the gaming machines shipped to gaming parlors are only those that have passed certain standards and can be played in a healthy manner, there are In some cases, it is possible to create a malicious program other than the passed program and use that malicious program to perform unauthorized modification to operate the central processing unit, and if such unauthorized modification is performed, it may be necessary to take the trouble to have a third-party organization conduct the test. However, there is a disadvantage in that in actual gaming parlors, gaming machines that do not operate in accordance with certain standards are sold.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, it is an object of the present invention to provide a microcomputer for controlling a gaming machine that can prevent, as much as possible, the control of a gaming machine by an illegally modified program other than a passing program.

[0005]

[Means for Solving the Problems] A gaming machine controlling microcomputer according to the present invention is a gaming machine controlling microcomputer including a read-only memory in which a control program for controlling the gaming machine is stored. The control program includes a suitability determining means for determining whether or not the control program stored in the only memory is appropriate; The apparatus is characterized in that a suitability judgment is made by the suitability judgment means, and when the judgment result is proper, a predetermined control operation is performed according to a control program stored in the read-only memory.

[0006]

According to the present invention, a read-only memory storing a control program for controlling a gaming machine is installed in a microcomputer for controlling the gaming machine. When a predetermined condition is satisfied, the appropriateness determining means of the gaming machine control microcomputer determines whether the control program stored in the read-only memory is appropriate. Then, if the judgment result is appropriate,
Predetermined control operations for the gaming machine are performed according to a control program stored in the read-only memory.

[0007]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall system block diagram showing a security system using a one-chip microcomputer for gaming according to the present invention.

A microcomputer chip according to the present invention is manufactured by a semiconductor chip manufacturer 1. Semiconductor chip maker 1 manufactures MPUs in microcomputers.
(Micro Processing Unit)
, RAM (Random Access Memo
ry), manufacturing a semiconductor chip with input/output ports (I/O ports) integrated into one chip. The chips manufactured by this semiconductor chip maker 1 include a development chip 23a and a development chip 23b, which will be explained in detail later. The mass-production chip 23a has a determination function that determines whether the program stored in the ROM connected to the mass-production chip 23a is appropriate and has passed a test by a third-party testing organization 11, which will be described later. It has the following. The development chip 23b is a chip that does not have the above-described determination function, and is the same as the mass-production chip 23a except that it does not have the determination function.

Among the chips delivered from the semiconductor chip manufacturer 1 to the chip distribution company 2, the mass-produced chips 23a are distributed by the mass-produced chip distribution department 28 and delivered to the chip distribution management organization 3. On the other hand, the development chip 23b is distributed by the development chip distribution department 29 of the chip distribution company 2 and delivered to the chip distribution management institution 3. Note that this chip distribution company 2 may be a completely private company,
It may also be a public business organization created with funding from the state. The chip distribution management organization 3 is an organization that manages whether or not chips are distributed properly and mediates the distribution of chips to a predetermined gaming machine manufacturer or the like. This chip distribution management institution 3 may be omitted and the chips may be delivered directly from the chip distribution company 2 to the gaming machine manufacturer.

The mass production chips 23a and the development chips 23b delivered to the chip distribution management institution 3 are delivered to the mass production department 6 and the development department 5 of the game machine manufacturer 4, respectively. The development department 5 of the game machine manufacturer 4 develops a program using the development chip 23b brought in as shown in FIG. 7, and develops a product. The development department 5 has an application master ROM 10a in which the developed development program is stored.
At the same time, create an application game machine with the application master ROM 10a installed, create the application documents, submit the application submission 8 consisting of the application game machine equipped with the application master ROM 10a, the created documents 9, etc. Apply for the test to the three-party testing organization 11.

[0012] The third party testing agency 11 is comprised of, for example, a commissioned agency of a public supervisory agency such as the police. This third-party testing organization 11 has a testing department 12 and an appraisal department 13, and the test submission 8 is delivered to the testing department 12, and the test application is accepted as shown in FIG. The testing department 12 tests the received test submission 8 as shown in FIG. 15, and determines whether the test result is acceptable or not as shown in FIG. If it is determined that the application has failed, the testing department 12 returns the application submission 8 to the game machine manufacturer and notifies the gaming machine manufacturer of the failure, as shown in FIG. 17.

On the other hand, the competent supervisory authority 25 consisting of the police of each prefecture also inspected the game machine for application, and the third party testing institute 11 determined that the game machine passed, and the competent supervisory authority 25 determined that it was appropriate. In this case, a security code will be issued as shown in Figure 18 and the master R for mass production will be issued.
Perform the work to store it in the OM10b. The third-party testing agency 11 and the competent supervisory agency 25 constitute a third-party agency that tests whether the development program stored in the read-only memory (ROM) passes a certain standard. ing. The above-mentioned security code refers to whether the program stored in the ROM installed in a gaming machine that has been judged to have passed by a third-party institution and put on the market is the correct one that has passed the test of the third-party institution. This is security information used to determine whether the

[0014] This security code may be obtained by, for example, converting the program data of the passed program according to a predetermined conversion format. In this case, all of the program data may be used as the standard for creating the security code, or particularly important parts of the program data (for example, data parts such as jackpot probability and opening time of the variable winning ball device) may be used as the standard for creating the security code. You can also use it as This security code may be issued at the time when a third-party testing agency determines that the test has been passed, without waiting for the test results from the competent supervisory agency 25.

The mass production master ROM 10b to which a security code has been added by the testing department 12 of the third party testing organization 11 is delivered to the mass production department 6 of the gaming machine manufacturer 4. The mass production department 6 copies the storage information stored in the mass production master ROM 10b as shown in FIG. A ROM in which the storage information of the mass production master ROM 10b has been copied is mounted on the board 22. Furthermore, the mass-produced chips brought in from the chip distribution management organization 3 are shown at 20.
It is mounted on the board 22 as shown in FIG. The mounted chip 23 and mounted ROM 10c mounted on this board 22 constitute a microcomputer for controlling the gaming machine.

After mounting the chip 23 and ROM 10c on the board 22, when the power is turned on for the first time, the mounting RO
The security code included in the storage information of M10c is stored in the mounting chip 23 as described later. The mounting chip 23 consisting of the mass-produced chip 23a is mounted on the substrate 22.
It has a function of storing only the security code stored in the ROM 10c that is installed in the ROM 10c and connected first. Then, based on the stored security code, it is determined whether the program stored in the mounted ROM 10c is a proper program that has passed a test by a third-party organization. Once the ROM is installed, the program stored in the ROM may be tampered with, or the installed ROM1
If 0c is replaced with a ROM in which an illegally created program is stored, the security code stored in the mounting chip 23 and the security code stored in the ROM may become inconsistent due to a discrepancy. lose. Therefore, it becomes possible to determine whether the program has been illegally modified.

Instead of having the gaming machine manufacturer 4 carry out the work of copying this program and security code to the ROM and mounting it on the board, the master ROM 1 for mass production is
0b may be delivered to the chip distribution company 2, where the chip distribution company 2 performs ROM copying and mounting of the ROM onto the board, and then the board is delivered to the gaming machine manufacturer 4. This gaming machine manufacturer 4 constitutes a development and manufacturing company that develops a program for operating the central processing unit of a microcomputer for controlling the gaming machine and stores the developed program in the read-only memory of the microcomputer. ing. Note that this development and manufacturing company is not limited to the game machine manufacturer, but may also be a program development and manufacturing company that is a subcontractor of the game machine manufacturer.

As mentioned above, the mass-produced chip 23a is
If the program stored in the connected ROM is modified so that it is different from the original program, it will be determined that the program has been illegally modified and the microcomputer will not operate under normal conditions. It has the function of Therefore, when the aforementioned development department 5 performs development using the mass-produced chip 23a,
Each time the program stored in the ROM is debugged or otherwise changed, it is determined that the program is inappropriate, causing the inconvenience that the microcomputer no longer operates normally. However, as described above, the development chip 23b does not have the security check function. Therefore, if the development chip 23b is used for debugging, etc., the microcomputer operates in a normal state, which is convenient for program development. In addition, mass production chip 23
The package a is made of plastic, for example, and the package of the development chip 23b is made of ceramic, for example, so that the mass-produced chip 23a and the development chip 23b can be distinguished from each other based on the appearance of the chips.

The game machine 21 with the board mounted with the chip and the ROM mounted thereon is carried into the game hall 24. In the gaming hall 24, a plurality of gaming machines 21 that have been brought in are installed so that players can play games.

[0020] The competent supervisory authority 25 randomly inspects the gaming machines 21 installed in the gaming parlor 24, and performs a process of checking the ROM of the gaming machine that seems to be malfunctioning, as shown in the diagram 26. If the ROM cannot be determined to be suitable even after verification, the third-party testing organization
An appraisal request is made to the appraisal business department 13 of No. 1. for example,
If both the mounted chip 23 and the mounted ROM 10c are replaced with different ones made illegally, the game machine will operate according to the modified program without the aforementioned security check being performed. In such cases, an appraisal request is made to the appraisal business department 13.

[0021] In the appraisal business department 13, the board 2 on which the mounted chip 23 and the mounted ROM 10c that have been requested for appraisal are mounted.
2 is inspected and gaming machine verification/verification is performed as shown at 33 in the figure. This gaming machine verification/verification 33 involves removing the ROM 10c mounted on the board 22 and replacing it with a master ROM 10b for mass production in which a proper program is stored, and checking whether the mounted chip 23 operates normally. This is done by verifying and collating. As a result, as shown in the diagram 28, appraisal work and document preparation are performed, and the appraisal results are reported to the competent supervisory authority 25. Application master RO mentioned above
M10a, mass production master ROM10b, mounting ROM10
c is composed of, for example, an EPROM.

FIG. 2 is a block diagram showing a mass-produced chip mounted on a substrate and various devices and circuits connected thereto.

This mounted chip 23 has a central processing unit, that is, a CP, which can execute control operations according to a predetermined procedure.
U (Central Processing Un)
IT) 40, a RAM 41 that can write and recall necessary data, and an I/O port 44 that receives input signals and provides input data to the CPU 40, receives output data from the CPU 40, and outputs it to the outside on a single chip. It is structured and organized. A crystal oscillation signal from an externally provided crystal oscillator 45 is input to a clock generation circuit 46 provided on the mounted chip 23 . The crystal vibration signal from this crystal oscillator 45 has a frequency twice that of the operating clock. Note that instead of the crystal oscillator 45, a vibration signal generated by a ceramic oscillator using a ceramic as an oscillator may be input to the clock generation circuit 46.

The programmable clock frequency divider circuit 47 to which the clock signal from the clock generation circuit 46 is input,
The frequency of the input clock signal is divided and a predetermined clock signal is output to the sound generator 48 and the variable display device display driving IC 49. This sound generator 48 outputs a control signal for generating sound to a speaker 97 (see FIG. 7) provided in the gaming machine. Further, the variable display device display driving IC 49 is for controlling the variable display device 90 (see FIG. 7) provided in the gaming machine, and is for controlling the variable display device 90 (see FIG. 7).
, RAM, ROM, and I/O ports all integrated into one chip. Note that the variable display device display driving IC 49 may be provided in a state connected to the programmable interrupt request timers 50 and 51 as shown by the dashed line in the figure, or the variable display device display driving IC 49 may be provided in a state connected to the programmable interrupt request timers 50 and 51. The display device 90 can be connected directly to the I/O port 44.
The control may be performed using an output signal from.

Programmable interrupt request timer 0 (50)
, 1 (51) is composed of a 16-bit programmable counter timer, and includes a free running counter and a compare register (two sets). This programmable interrupt request timer 0 (50), 1 (5
1) has an interval timer function as its main functions,
Event count function, one-shot output function, PW
It not only has an M (pulse width modulation) output function, but also a pulse width measurement function and a time difference measurement function.

[0026] The pulse width measurement function is, for example, the start winning switch 101a, 101b, 10 provided in the gaming machine.
This function measures the waveform length of the detection signal of the 1c or 10 count detection switch 102 (see FIG. 8). The time difference measurement function is a function that measures the time from when a detection signal is received from the various switches described above until the next detection signal is received. What is this pulse width measurement function and time difference measurement function?
Programmable interrupt request timer 0 (50), 1 (51)
This can be achieved if the clock source of the counter is selected as an external input.

As the clock source of the counter, the clock can be selected and used as a refresh counter, or the output from the other programmable interrupt request timer can be selected as the clock source and used as a 32-bit counter. You can also do it. As a method of selecting these clock sources, a method of selecting them within the program is adopted. That is, there is a register at a certain address, a predetermined number is written there, and a clock source is selected depending on the type of the written number.

This programmable interrupt request timer 0 (5
0) and 1 (51) can set interrupts using counter outputs and compare outputs, and can route interrupts to any one of user reset, maskable interrupt, and non-maskable interrupt exception processing. Further, by the function of the prescaler, the clock unit time of the timer can be arbitrarily set, and the values of the compare registers (two sets) can be arbitrarily set. Output signals from the programmable interrupt request timers 0 (50) and 1 (51) are input to the reset/interrupt controller 52.

The reset/interrupt controller 52 has a system reset function and a user reset function. System reset means initializing the entire mounted chip 23 including the I/O port 44 and restarting from the power-up state. On the other hand, user reset means to reset only the CPU 40 and perform a warm restart of the mounted chip 23. This user reset is performed once every 2 msec, for example, to enable interrupt processing. This reset/interrupt controller 5
2, a system reset signal, a user reset signal for performing a warm restart, a non-maskable interrupt request signal, and a maskable interrupt request signal are inputted from the interrupt request signal generation circuit 54. A system reset output signal is output from the reset/interrupt controller 52 to the interrupt request signal generation circuit 54.

The system reset signal input to the reset/interrupt controller 52 is a low active level input. In other words, it is reset when the input signal switches from high level to low level. Similarly, the user reset signal input to the reset/interrupt controller 52 is a low active level input. Note that this interrupt request signal generation circuit 54 may not be provided.

The mounted chip 23 is provided with an address decode circuit 57 and a data output time adjustment circuit 58. The address decode circuit 57 includes an external I/O 67
and an external ROM 10c are connected. This mounted chip 23 and external ROM 10c constitute a microcomputer. This microcomputer may include the mounting chip 23, the external ROM 10c, and the sound generator 48 in one chip. The address decode circuit 57 has an address decode (chip select signal generation) function that sets an external input/output map area and an external ROM area in a space on a memory (physical address).

The external input/output map area size can be set from 256B to 2KB, and the chip select signal (6
books) can be assigned. Further, the external ROM area generates a chip select signal for the external ROM 10c.

Data output time adjustment circuit 58 provides a wait function to extend the machine cycle in order to interface with low speed input/output equipment. Depending on the settings, a wait state of up to four machine cycles is possible. The output signal from the address decode circuit 57 is also input to the I/O port 44, and the configuration is such that the input/output port can be specified by specifying the bit of the I/O port 44 according to the output address. There is.

The I/O port 44 has 8 bits (port A
It has one port each for peripheral device interface ports (PIP) and 4-bit (for port B). In addition to the general-purpose input/output port function, these port terminals also serve as external input/output chip select terminals and handshake terminals (for one port). As shown in Figure 4,
It has three modes, a, b, and c, and a selection command for selecting one of the three modes is given to the I/O port 44 from the external ROM 10c via the CPU 40. When mode c is selected, an 8-bit general-purpose input/output port and a 6b
It provides a chip select function. If you want to have a handshake function, select mode a or b. Then, 8b which can input/output settings in byte units.
It provides general purpose input/output ports. However, two terminals (P8, P9) are set as handshake terminals for port A, and timing signals and read and write signals are input and output to these handshake terminals P8 and P9. This handshake terminal can be set for interrupts. Additionally, handshake terminal interrupts can be routed to maskable interrupt exception handling. Also, mode a
When mode b is selected, the terminals P10 to P13 become chip select signal ports, and when mode b is selected, the terminals P10 to P13 become PIPs without a handshake function for port B.

Various drive circuits 55 and various switch circuits 56 of the game machine are connected to this I/O port 44. Signals from various switch circuits 56 are applied to the CPU 40 via the I/O port 44, and control signals from the CPU 40 are applied to various drive circuits 55 via the I/O port 44.

The watchdog timer 60 provided in the mounted chip 23 provides a function of detecting malfunction (runaway) due to causes such as noise or a drop in power supply voltage, and restoring the circuit to a normal state. A signal from watchdog timer 60 is applied to system check circuit 61 and reset/interrupt controller 52. This watchdog timer 60 is configured to output a watchdog timer signal when the reset timing of the timer exceeds the maximum allowable reset interval time. This maximum allowable reset interval time can be set to a desired time by the gaming machine manufacturer 4. Furthermore, this watchdog timer 60 has an 8-bit
The prescaler function allows the clock unit time of the timer to be set. The output of this watchdog timer signal can be routed to any one of user reset, maskable interrupt, and non-maskable interrupt exception processing. Note that the system check circuit 61 may not be provided.

Address bus terminals (16 terminals) and data bus terminals (8 terminals) are connected to the external bus interface 43 provided on the mounting chip 23, and address bus signals and data bus signals are output respectively. Ru. In addition, from the external bus interface 43, a signal indicating that the data bus is in a read cycle, a signal indicating that the data bus is in a write cycle, a signal indicating that the memory space is being accessed, and a signal indicating that the operation code fetch cycle is being executed. A signal is output indicating that there is. These output signals are output to the one-chip microcomputer ICE adapter board 59 (see FIG. 5) during program development. All the input/output terminals of this mounted chip 23 except the output terminal from the security check circuit 62 to the monitor device 60 are connected to this one-chip microcomputer ICE adapter board 59. In addition, the address bus signal from the address bus terminal and the data bus signal from the data bus terminal are respectively external I/O
It is also output to port 67 and external ROM 10c. Also,
The variable display device display driving IC may be operated by inputting a data bus signal from the data bus terminal to the I/O port and data bus of the variable display device display driving IC 49. In this case, the content of the signal input to the variable display device display driving IC may be, for example, a command signal for causing a game machine to hit a jackpot. On the other hand, the output signal from the I/O port 44 may be input as the command signal to the variable display device display driving IC 49.

In the figure, 69 is a large capacity capacitor, R
This is for backing up the power supply of AM41. Note that this capacitor 69 may not be provided in some cases. This R
The AM 41 is configured to be able to switch banks in response to a bank switching signal from the security check circuit 62. This will be explained based on FIG. 3.

FIG. 3 is an explanatory diagram showing a memory map. As shown in FIG. 3, addresses 0000 to 7FFF are addresses allocated to the external ROM 10c, and 8
Addresses from 000 to 81FF are allocated to RAM 41, and addresses from F000 to F7FF are for external I/O 6.
This is the address assigned to 7, from FF00 to FFFF
The addresses up to are the addresses allocated to the internal I/O 44. And RAM41 is from address 8000 to 81FF
256/512B (capacitor 6) to the same address up to
9) and 256B. However, the capacity of RAM41 is 256B
, the address is from 8000 to 80FF. In the case of general user mode, which will be described later, 25
A working area of 6/512B is used, and in the case of a user test mode to be described later, bank switching is performed and a working area of 256B is used. Note that among 256/512B, 256 is for pachinko gaming machines, and 512 is for slot machines.

Furthermore, addresses 0000 to 7FFF are assigned to the external ROM 10c as described above.
A suitable program is created to fit within this address. If a program is created to execute an instruction outside this address, it is determined that this program has been illegally modified. In such cases,
The CPU 40 is configured to automatically stop and not execute any instructions.

The RAM 41 is backed up by a capacitor 69. However, if there is a momentary power outage for some reason, CPU operation will become unstable and R
There is a possibility that data in RAM 41 may be destroyed due to abnormal access to AM 41. Therefore, the RAM 41 is provided with an access control function for prohibiting access to the RAM 41 in response to the output from the backup power supply when the power supply is momentarily cut off.

That is, the RAM 41 is provided with an access control register, and access to the RAM 41 is controlled depending on the value of a predetermined bit. This bit is rewritten while the CPU 40 is still operating stably in response to a non-maskable interrupt generated by the backup power supply when the power supply is momentarily cut off. When this bit has a value indicating that access is prohibited, data cannot be read from or written to the RAM 41, and it is possible to prevent the gaming machine from operating abnormally.

The security check circuit 62 provided in the mounting chip 23 includes a CPU 63, a ROM 64, an R
It has an AM65, and a ROM64 stores a program shown in FIG. 5, which will be described later.

Further, the program will be explained based on FIG. 5. The power is turned on, the system is reset, and in step S (hereinafter simply referred to as S) 1, the external ROM 1 is
Security code written in 0c and external RO
Processing is performed to check consistency with the program data of M10c. The security code written in this external ROM 10c is as explained in Fig. 1.
This is a security code added to a development program that is deemed to have passed by a third-party testing agency or competent supervisory agency 25, and is, for example, a code obtained by converting program data in the external ROM 10c according to a certain conversion format. The conversion format has already been stored in the ROM 64 of the security check circuit 62, and the consistency between the security code written in the external ROM 10c and the program data is checked according to the stored conversion format. Note that instead of writing the conversion format in advance in the ROM 64 of the security check circuit 62, the conversion format may be written in the ROM 10b that has been determined to be acceptable by a third-party testing organization or the like. In that case, the security check circuit 62 checks the consistency between the security code written in the ROM and the program data based on the conversion format and the security code. Next, the process proceeds to S2, where it is determined whether the check result is appropriate, and if the result is appropriate, the process proceeds to S3, where it is determined whether or not the security code is written in the security check circuit 62. It will be done. When the power is turned on for the first time after the ROM 10c is mounted on the same board as the board 22 on which the mounted chip 23 is mounted, the process proceeds to S6 because the security code has not yet been written in the security check circuit. In S6, a process of writing a security code into the security check circuit 62 is performed, and then the process advances to S7. In this case, the program data in the ROM may be written directly as security data into the security check circuit. In S7, a process is performed in which the CPU 40 is activated without a time limit and placed in a general user mode in which normal gaming machine control is performed. Even in this case, if there is a system runaway, the system is reset and the processes from S1 onwards are performed again. Note that in this embodiment, the substrate 22 on which the mounted chip 23 is mounted is
The security code is written in the security check circuit 62 when the power is turned on for the first time after the ROM 10c is mounted on the same board as the ROM 10c. It is also possible to receive a master chip for mass production in which the security code is written, copy it to the mass production chip 23a, and mount it on the board 22. In addition, the mounted chip 23 (
A security code may be written in the mass-produced chip 23a).

On the other hand, if the security code has already been written in the security check circuit, a YES determination is made in S3, and control proceeds to S4, where the ROM 10 is
The consistency between the security code c and the security code already written in the security check circuit is checked. Next, the control proceeds to S5, where it is determined whether the check result is appropriate or not. If the result is appropriate, the control proceeds to S7, but if not, the control proceeds to S8, where the CPU 40 is A certain period of time (for example, 60
2 seconds), that is, transition to user test mode. If a certain period of time has elapsed or if the system goes out of control, the system is reset again and the processes from S1 onwards are performed. This S1,S
2, S4, and S5 constitute a suitability determining means for determining whether the control program stored in the read-only memory is appropriate and has passed the test of the third party organization. On the other hand, if the results of the checks by S2 and S5 are determined to be appropriate, the ROM 41 will use the 256/512B working area as described above; If it is determined that it is inappropriate, the security check circuit 62 sends a message to the RAM 41 as shown in FIG.
A bank switching signal is output as shown in
is switched to the working area of 256B. When the CPU is activated only within the time limit set by S8 (for example, 60 seconds), the operation of the microcomputer within the time limit is limited to 25
This will be done in the working area of 6B.

One of the reasons why the CPU 40 is activated only for a predetermined period of time (for example, 60 seconds) even if the result of this check is incorrect is that, for example, the gaming machine 24 of the gaming machine indicated by 21 in FIG. There are cases where the board is checked again and the control of the variable display device installed on the game board is checked again before shipping to the game board. In that case, the mounted ROM 10c already mounted on the board 22 is pulled out and other checks This is to perform a check by inserting a ROM that stores a program for the test, and even if a ROM that stores a program different from the passing program is installed, the microcomputer will not operate for a predetermined period of time (for example, 60 seconds). This is to enable the above-mentioned check to be performed. Another reason is that after a gaming machine control program development company creates a program and passes the test by a third-party testing organization 11, the ROM 10c and chip 23 in which the passed program is stored are installed on the board 22. This is because the board may be checked before being mounted and shipped to the gaming machine manufacturer 4. In this case, the board check is performed by replacing the passing ROM with a test ROM containing a test program that shortens the control time, such as by shortening the opening period of the variable winning ball device at the time of a jackpot than usual. A short time limit (for example, 60 seconds) after mounting on the board 22
Enables quick input/output testing within the system. In such a user test mode, the reason for switching the working area of RAM 41 to 256B is that if the working areas for general user mode and user test mode are the same, programs for program modification will not be stored. The ROM is illegally inserted into the board 22, and the microcomputer is operated according to the program for modifying the program for a limited time (for example, 60 seconds).
Various constants etc. stored through AM41 were rewritten, and later the external ROM where the passing program was stored
Even if 10c is mounted on the board 22, the constants etc. have already been rewritten, causing the inconvenience of the microcomputer operating incorrectly.In order to prevent such inconvenience, in the case of user test mode, This is to enable operation in a working area different from the general user mode.

Furthermore, S1 to S5 or S1 shown in FIG.
The time required for the security checks in S3 and S6 is set to, for example, about 3 to 5 seconds. 3~ like this
The reason why it is configured to take a relatively long time of about 5 seconds is that when a ROM in which an illegally modified program other than a passing program is stored is mounted on the board 22, each time the time limit elapses, Perform a security check for about 5 seconds and make the CPU inoperable during that time.
This is to prevent the CPU from operating normally for a long period of about 5 seconds, so that the game machine does not operate normally, and to prevent illegally modified programs from playing the game.

[0048] Note that in S8, the time limit (for example, 6
0 seconds) have elapsed, the CPU may not be activated until the next power is turned on. In addition, after repeating the system reset process a predetermined number of times after the time limit has elapsed, the CPU 40 is stopped, and depending on the incorrect ROM, the system will not operate in user test mode again even if the power is turned on again. It may be configured.

The security check processing time of about 3 to 5 seconds and the above-mentioned time limit (for example, 60 seconds) become shorter as the oscillation frequency of the crystal oscillator 45 becomes higher, and become longer as the oscillation frequency becomes lower. . When the monitor device 60 is connected to the security check circuit 62 as shown in FIG. 2, it becomes possible to determine whether the current mode of the chip is the general user mode or the user test mode. Note that 66 and 68 in the figure are data buses.

The development chip 23b is the same as the mass-production chip 23a except that the security check circuit 62 shown in FIG. 2 is not present. In addition,
The security check circuit 62 is also included in the development chip 23b.
The program for performing the security check may not be stored in the ROM 64.

[0051] This mass production chip 23a and the development chip 2
3b is a so-called ASIC (application
specific integrated ci
rcuit), which is a chip dedicated to pachinko and slot machines. Alternatively, it may be a chip that limits the gaming machine manufacturer 4. In the above-described embodiments, various functions are integrated into one chip, but each of these functions may be configured as a single component.

FIG. 6 is a block diagram showing part of a microcomputer development system used in the development department of a gaming machine manufacturer to develop a program using a development chip.

In the figure, 80 is a CPU ICE, which is a commercially available product. ICE (in-circuit emulator)
or) stands for MDS (microcomputer
It emulates the hardware of a microcomputer system under the development system. This ICE80 for CPU is an ICE for a microcomputer for controlling gaming machines before it was integrated into a single chip, and this commercially available ICE80 for a CPU, which has been commonly used in the past, can be used effectively to develop microcomputer programs. For this purpose, a one-chip microcomputer ICE adapter board 59 is required. This one-chip microcomputer IC
The E adapter board 59 is sold by the chip distribution company 2 shown in FIG. The CPU probe 81 of the CPU ICE 80 and the CPU socket 84 of the one-chip microcomputer ICE adapter board 59 are connected, and the one-chip microcomputer probe 82 of the one-chip microcomputer ICE adapter board 59 and the product development board 83 are connected. It becomes possible to develop microcomputer programs by connecting the one-chip microcomputer socket 84. Note that 10 is a ROM connected to the development chip 23b.

FIG. 7 is an overall front view showing a pachinko game machine 21, which is an example of a game machine incorporating a microcomputer for controlling the game machine. When the player operates the ball-striking operation handle 92 provided at the lower right corner of the pachinko game machine 21, the ball-launching device 93 (see FIG. 8) is activated, and the pachinko balls are shot one by one into the gaming area 94. It will be done. The pachinko ball hit into the gaming area 94 enters the starting prize opening 96a.
, 96b, or 96c, the variable display device 90 that can variably display multiple types of identification information starts changing. This variable display device is equipped with a plurality of drums (three in the drawing). Variable display is performed by rotating the drums with a stepping motor, etc., and variable display is performed by stopping the stepping motor. Display can be stopped. Note that the variable display device 90 may be configured with a digital display using a liquid crystal display, segment LED, dot matrix LED, electroluminescence, etc. instead of using a drum. When the display result when the variable display device stops is a predetermined combination of identification information (for example, 777), the variable winning ball device 95 is opened and the pachinko ball is advantageous for the player who is likely to win. The first state is reached, and a jackpot state occurs. Whether or not to generate this jackpot state is determined based on the picked up value of a random number counter that is counted up using the reset waiting time of the microcomputer at the time of starting winning. In this embodiment, a pachinko game machine is shown in which a game is played by inserting pachinko balls, but a card processing device including a card reader/writer etc. is installed to provide a card etc. on which information that can identify a predetermined value is recorded. It may also be a card-type gaming machine in which a recording medium of 1 is inserted into the card processor and games can be played within the range of value specified by the recording medium. In this case, the card processing device may be provided separably from the pachinko gaming machine 21, or may be incorporated into the pachinko gaming machine 21. In the case of this card-type gaming machine, the points earned through the game are displayed, and at the end of the game, a prize recording medium on which the value corresponding to the points is recorded is paid out to the player. This recording medium for prizes may be composed of a recording medium different from the storage medium inserted into the card processor at the start of the game, or the recording area of the storage medium inserted at the start of the game may be divided into two, and one The value required at the start of the game may be recorded in one recording area, and the value corresponding to the points obtained at the end of the game may be recorded in the other recording area and paid out to the player. Reference numeral 97 in the figure is a speaker, which generates sound effects and the like when a jackpot is won based on a signal from the sound generator 48 (see FIG. 2).

FIG. 8 is an overall rear view showing the internal structure of the pachinko game machine 21. As shown in FIG.

[0056] The starting prize openings 96a, 96b, 96c (
(See Figure 7) When the winning ball is detected by the winning ball detection switch 10
1a, 101b, and 101c, and the detection signals are sent to various switch circuits 56 (
(see Figure 2). Further, the winning balls that have won in the variable winning ball device 95 are detected by the 10 count detection switch 102, and the detection signal is input to the various switch circuits 56 of the game control main board 22. The game control main board 22 has a chip 23 and an external ROM 10c mounted thereon, and has a connector 103, through which the detection signal is input. In the figure, 180 is a solenoid for opening and closing the variable winning ball device 95, and is controlled based on drive control signals from each drive circuit 55 of the game control main board 22. The game control main board 22 is housed in the board case 104 and is provided on the mechanism board side of the gaming machine 21. In the figure, 108 is a game control sub-board, on which the aforementioned variable display device display driving IC 49 is mounted. This game control sub-board 108 is provided with a connector 107, and this connector 107 is connected to the connector 103 of the game control main board 22 via connection wiring 105. Furthermore, pachinko game machine 2
1 is provided with a relay terminal board 111, and the connector 110 of this relay terminal board 111 and the connector 103 of the game control main board 22 are connected via connection wiring 105. Furthermore, the connector 103 of the game control main board 22 and the locking device 113 are connected via the ground wire 112, and the game control main board 22 is in a grounded state.

FIG. 9 is an exploded perspective view showing the structure of a board case for housing the game control main board 22.

The external ROM 10c is mounted on the game control main board 22 on which the mounting chip 23 is mounted (see the arrow in the figure), and then the connector 1 of the game control main board 22 is mounted.
03, the game control main board 22 is mounted and fixed inside the board storage box main body 120 with the connection wiring 105 and the ground wire 112 connected. After that, the transparent cover body 12
1 covers the substrate storage box main body 120. The board storage box body 120 is provided with an engagement hole 124, and the claw portion 1 provided on the transparent cover body 121 side.
25 inserted into the engagement hole 124, screw the transparent cover body 121 onto the substrate storage box body 120 using the screws 126.
Fixed to. Next, the opening/closing cover body 122 is attached to the substrate storage box body 120 so as to be openable and closable. This opening/closing cover body 122 is provided with a support shaft 128, and an insertion hole 127 provided on the board storage box body 120 side.
This support shaft 128 is inserted through the opening/closing cover body 122 to be supported on the board storage box body 120 side so as to be freely openable and closable. On the other hand, an engagement claw portion 123 is formed in the board storage box body 120, and an engagement hole 129 that engages with this engagement claw portion 123 is formed on the opening/closing cover body 122 side. The opening/closing cover body 122 is fixed to the substrate storage box main body 120 by fitting and engaging the opening/closing cover body 129 onto the engaging claw portion 123 . Then, the opening/closing cover body 12
2, it can be easily opened by releasing the engagement between the engaging claw portion 123 and the engaging hole 129.

In the figure, reference numeral 132 denotes a sealing seal, and with the transparent cover body 121 attached to the substrate storage box 120, the sealing seal 132 is pasted across the transparent cover body 121 and the substrate storage box body 120. In this way, for example, in order to replace the external ROM 10c with another external ROM, the transparent cover body 121 can be attached to the board storage box main body 1.
If the transparent cover body 121 is removed from the transparent cover body 20, the seal 132 will be broken, so by looking at the seal seal 132, it is possible to determine whether or not the transparent cover body 121 has been removed. Also,
Reference numeral 130 is a notch, in which the connection wiring 105 and the ground wire 11 are connected.
2 to the outside of the board case 104.

Transparent cover body 121 and opening/closing cover body 122
is provided with a large number of heat radiation holes 131, and is configured to allow heat from the game control main board 22 housed in the board case 104 to escape to the outside. In addition, a board storage box main body 120 and an opening/closing cover body 12 are also provided.
2 is made of a synthetic resin made of polypropylene mixed with carbon, for example, in order to improve conductivity. The color of this resin is black. In addition, the transparent cover body 121 is transparently made of polycarbonate or the like, and the opening/closing cover body 121 is made of transparent material such as polycarbonate.
By opening 2, the game control main board 22 can be seen from outside the transparent cover body 121, and the game control board 22 can be viewed without removing the transparent cover body 121 from the board storage box body 120. It is configured so that you can check to some extent whether there is an abnormality by looking at it. Further, carbon may also be mixed into the polycarbonate or the like constituting the transparent cover body 121. This transparent cover body 121 does not need to be completely transparent, but only needs to be such that the inside can be seen through. In addition,
The board storage box main body 120 and the opening/closing cover body 122 may be made of metal plates.

[0061]

[Effects of the Invention] The present invention relates to a one-chip microcomputer for controlling a gaming machine brought into a gaming parlor, and has been illegally modified to operate using a read-only memory in which a fraudulent program other than a passing program is stored. In this case, the suitability determining means determines that the game is not proper and the game is not played, making it easier to prevent unauthorized programs from controlling the gaming machine.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram schematically showing a security system using a gaming machine control microcomputer according to the present invention.

FIG. 2 is a block diagram showing a mounted chip constituting a gaming machine control microcomputer according to the present invention and a circuit of peripheral devices connected thereto.

FIG. 3 is an explanatory diagram showing a memory map of the gaming machine control microcomputer according to the present invention.

FIG. 4 is an explanatory diagram for explaining functions corresponding to modes of an I/O port.

FIG. 5 is a flowchart showing a program stored in a ROM provided in a security check circuit of a gaming machine control microcomputer.

FIG. 6 is a block diagram showing part of a development system for a microcomputer for controlling gaming machines.

FIG. 7 is an overall front view showing a pachinko game machine as an example of the game machine.

FIG. 8 is an overall rear view showing the internal structure of the pachinko game machine.

FIG. 9 is an exploded perspective view for explaining the structure of the board case.

[Explanation of symbols]

21 Pachinko game machine 23 as an example of a game machine
Mounted chip 10c Mounted ROM 4 Game machine manufacturer 11, which is an example of a development and manufacturing company
Third-party testing agency 25 Competent supervisory agency 24 Amusement hall

Claims (1)

[Claims] 1. A gaming machine control microcomputer including a read-only memory storing a control program for controlling a gaming machine, wherein the control program stored in the read-only memory is proper. The method includes a suitability judgment means for judging whether or not the suitability judgment is carried out, and the suitability judgment means makes a suitability judgment based on the establishment of a predetermined condition for making the suitability judgment, and the judgment result is judged to be proper. A microcomputer for controlling a game machine, characterized in that, when a game machine is detected, a predetermined control operation is performed according to a control program stored in the read-only memory.