JPH04280469A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the memory cell structure of a dynamic RAM which can reduce the memory cell intervals and enlarge a capacitor area in the same memory region. CONSTITUTION:A dielectric layer 11 is installed to the lower part of an active layer which comprises a P-type single crystal layer 2. A bit line is formed below the layer and connected with an n-type diffusion layer 10 from the lower part, which eliminates a contact region between the bit line and the n-type diffusion layer. This construction makes it possible to reduce the interval between the word line of the adjacent memory cell and the capacitor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM, which is a type of semiconductor device, and particularly to a dynamic RAM with an improved memory cell structure.

0002

2. Description of the Related Art FIG. 3 is a schematic cross-sectional view of an example of a stacked capacitor type memory cell structure of a conventional dynamic RAM up to bit line formation. In the figure, 1b is a P-type Si substrate, 3 is an element isolation and interlayer Si oxide film having a thickness of, for example, 0.3 to 0.4 μm, and 4 is, for example, 0.2 μm thick.
The word line 5 has a thickness of 0.2 μm and is usually made of polycrystalline Si, and the word line 5 has a thickness of 0.2 μm and is usually made of polycrystalline Si.
A capacitor electrode 6 has a thickness of, for example, several tens of angstroms, and is usually made of a Si oxide film or a Si nitride film. 7 has a thickness of, for example, 0.2 μm, and is usually made of polycrystalline material. The other electrode of the capacitor made of Si, 8 is an interlayer insulating film between the capacitor electrode 7 and the bit line 13, usually made of a Si oxide film, and 9 is usually made of P.
Alternatively, it is an n-type diffusion layer in which As is diffused at a high concentration, and is in contact with the electrode 5 of the capacitor. 10
Similarly to the diffusion layer 9, this is an n-type diffusion layer that is in contact with the bit line. 13b is a bit line usually made of metal, silicide, etc., and 14b indicates the distance between a word line and an adjacent memory cell, which is, for example, 2 μm in this conventional example.

The stacked capacitor type memory cell structure of a conventional dynamic RAM has a bit line 13 as shown in FIG.
b was formed above a capacitor structure consisting of electrodes 5, 7 and dielectric film 6. Therefore, a contact region between the bit line 13b and the diffusion layer 10 was required on the surface of the substrate 1b, and an opening for passing the bit line 13 through the capacitor electrode 7 was required.

0004

[Problems to be Solved by the Invention] Conventional semiconductor devices are
With the above structure, a contact area between the bit line and the diffusion layer was required on the surface of the Si substrate, and an opening area for passing the bit line was required for the capacitor electrode, but these were required for each memory cell. Dynamic RAM
This has been an obstacle in achieving high integration.

The present invention was made to solve the above-mentioned problems, and it is possible to reduce the distance between adjacent memory cells and to expand the capacitor area in the same memory cell area. The object is to obtain a semiconductor device having a memory cell structure.

[0006]

[Means for Solving the Problems] A semiconductor device according to the present invention has a memory cell structure in which a dielectric layer is provided below a P-type single crystal Si layer that is an active layer, and a bit line is further formed below the dielectric layer. However, the bit line and the n-type diffusion layer of the transistor section are connected through the dielectric layer and the active layer. Note that the lower region of the dielectric layer forming the bit line is made of an additive-free Si substrate.

[0007]

The bit line in the present invention is formed below the active region with a dielectric layer in between, and is connected to the n-type diffusion layer from below. Therefore, there is no need to form a contact between the bit line and the n-type diffusion layer on the surface of the active layer, and the word line interval 14 between adjacent memory cells can be reduced. Furthermore, since there is no need to form contact holes,
There is no need to form an opening region in the electrode 7 of the capacitor. This allows the capacitor area to be expanded.

[0008] This dielectric layer is similar to the upper P type single crystal S.
It has the role of separating the i-layer and the lower doped-free single-crystal Si region. By forming the bit line in an additive-free single crystal region below the dielectric layer, signal delay due to junction capacitance can be prevented when the bit line is formed of an n-type diffusion layer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the invention. In the figure, numerals 3 to 10 and 14 are the same as those in the conventional example shown in FIG. 1a is an additive-free Si substrate, 2 is, for example, 0.2
A P-type single crystal Si layer having a thickness of μm, 11 a Si oxide layer having a thickness of, for example, 0.2 μm and separating the Si substrate 1a and the single crystal Si layer 2, 12 a bit line 13a and an n-type diffusion The n-type diffusion region 13a connecting the layer 10 is a bit line made of an n-type diffusion layer, and is formed under the Si oxide layer 11 to a thickness of, for example, 0.2 μm.

In this embodiment, as shown in the figure, the bit line 13
a is formed below the P-type single-crystal layer 2, which becomes the active layer, via a Si oxide layer 11, and is connected to the n-type diffusion layer 10 from below. There is no need to form a contact region between the line and the diffusion layer. Therefore, the word line interval 14a between adjacent memory cells becomes narrow as shown in the figure, for example, 1 μm or less. Therefore,
The size can be reduced significantly compared to the conventional example. Furthermore, since there is no need to form a contact hole, as shown in the figure, there is no need to form an opening area in the electrode 7 of the capacitor, and the other electrode 5 can be extended close to the adjacent memory cell. This makes it possible to expand the capacitor area and increase the capacitor capacity. Further, the silicon substrate below the bit line 13a is free of additives, so that the junction capacitance of the bit line can be reduced and signal delay due to the junction capacitance can be prevented.

In the above embodiment, the upper side of the bit line 13a is in contact with the Si oxide layer 11, and the lower side is in contact with undoped single crystal Si, but as shown in FIG.
Further, a Si oxide layer 15 of, for example, 0.2μ is formed under the layer 3a.
The bit line may be formed to have a thickness of m, and may have a structure in which the bit line is sandwiched between the Si oxide layers 11 and 15 from above and below. Furthermore, a structure may be adopted in which a Si oxide layer is also formed on the side wall of the bit line and the bit line is wrapped in the Si oxide film, or the bit line is formed in the Si oxide layer. By adopting these structures, the junction capacitance is further reduced. Note that when a structure is adopted in which the bit line is covered with an oxide film, the single crystal Si1a does not need to be additive-free.

Further, in the above embodiment, the bit line 13a is
Although it is formed of a type diffusion layer, it may be formed of metal or silicide.

Furthermore, in the above embodiment, the dielectric layer 11 or 15 is formed of a Si oxide film, but Ta2O5
Other dielectric materials such as the like may also be used.

[0014]

[Effects of the Invention] As described above, the semiconductor device according to the present invention has a structure in which the bit line is formed below the active layer and the contact between the bit line and the n-type diffusion layer is eliminated from the substrate surface. This makes it possible to reduce the memory cell spacing and increase the capacitor area.
This has the effect of increasing the degree of integration of the dynamic RAM.

[Brief explanation of the drawing]

FIG. 1 Dynamic RAM according to an embodiment of the present invention
FIG. 2 is a schematic cross-sectional view showing a part of the structure of a stacked capacitor type memory cell.

FIG. 2 Dynamic RAM according to an embodiment of the present invention
FIG. 2 is a schematic cross-sectional view showing a part of the structure of a stacked capacitor type memory cell.

FIG. 3 is a schematic cross-sectional view showing a part of the structure of a stacked capacitor type memory cell of a conventional dynamic RAM.

[Explanation of symbols]

1a Added Si substrate 1b
P-type Si substrate 2
P-type single crystal Si layer 3
Element isolation and interlayer insulation film 4
Word line 5 Capacitor electrode 6 Capacitor dielectric film 7 Capacitor counter electrode 8 Interlayer insulating film 9 Capacitor electrode 5
n-type diffusion layer 10 in contact with bit line 13 n-type diffusion layer 11 in contact with bit line 13 dielectric layer 12
Diffusion regions 13a and 13b connecting the diffusion layer 10 and the bit line 13 Bit line

Claims (1)

[Claims] 1. A semiconductor device characterized in that, in a memory cell portion of a dynamic RAM, a dielectric layer is provided below an active layer, and a bit line is arranged under the dielectric layer.