JPH04278746A - Intra-system serial data receiving circuit - Google Patents

Abstract

PURPOSE:To prevent the bit deviation of output data in spite of the dispersion of the delay of a clock and a transmission system by selecting coincident data in its pattern for checking from input data, data deviated by half-cycle of the input data, data deviated by one fourth-cycle, and data deviated by three fourth-cycle. CONSTITUTION:FF14 executes the retiming of reception data by an input clock delaying one fourth-cycle and FF15 delays it by half-cycle again so as to permit it to match the reading timing of FF16. FF16 executes the retiming by delaying three fourth-cycle. A data comparing circuit 61 compares the both outputs of FF15 and FF16 so as to detect coincidence/noncoincidence. When it is coincidence (noncoincidence), the changing point of reception data is regarded to be in a phase near the rising of the input (opposite phase) clock so that the selection of the output data of FF11 (13) which executes the retiming by the opposite phase (input) as against a selector 41 is instructed from a selector control circuit 71. The output of the circuit 41 is deviated by one period in FF17 and FF18 and transmitted to the selector 42 so as to select data which is coincident in the pattern for checking.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-device serial data transmission circuit, and more particularly to an in-device serial data receiving circuit for receiving serial data transmitted between units in an apparatus.

0002

2. Description of the Related Art In a conventional in-device serial data receiving circuit of this type, the phase of a block for retiming received data is set in advance, and data is read.

0003

[Problems to be Solved by the Invention] In the conventional serial data receiving circuit described above, in order to prevent errors due to read timing deviations, it is necessary to reduce clock delays in gate circuits that distribute phase-set clocks to each unit, cables between units, etc. There is a problem in that it is necessary to strictly control variations in data delay due to gate circuits and inter-unit cables that transmit serial data between units, and a large number of man-hours are required during design and manufacturing.

0004

Means for Solving the Problems The in-device serial data receiving circuit of the present invention receives serial received data and a clock signal instructing the reading timing thereof, and reads the received data at the reading timing of the clock signal. a second reading circuit that reads the received data at a timing shifted by half a cycle from the clock signal; and a first reading circuit that selectively outputs one of the read data of the first and second reading circuits. and a selector of
Comparing third and fourth reading circuits that read the received data at timings shifted by one quarter period and three quarters from the clock signal, respectively, and the read data of both the third and fourth reading circuits. and a first control means for controlling the selection of the first selector depending on whether or not the two match.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The received data is sent to flip-flops 11, 13, 14.
, 16, and the input clock is sent to a delay device 31, an inverter 21, and a flip-flop 13. The delay device 31 delays the input clock by 1/4 period and sends it to the inverter 22 and the flip-flop 14. Therefore, the inverted output from the inverter 22 is the input clock delayed by 3/4 period. Further, the inverted output of the inverter 21 becomes a reverse phase clock obtained by shifting the input clock by half a cycle.

[0007] The flip-flop 14 converts the received data into 1/
Retiming is performed using an input clock delayed by four periods, and the flip-flop 15 retimes this to further delay it by a half period to match the reading timing of the flip-flop 16. The flip-flop 16 converts the received data into 3
Retiming is performed using an input clock delayed by /4 cycles. The data comparison circuit 61 compares both retiming outputs of the flip-flops 15 and 16 to detect whether they match. If there is a match (mismatch), it is assumed that the change point of the received data is in a phase close to the rising edge of the input (reverse phase) clock, and the flip-flop 11 (13) retimes the selector 41 using the reverse phase (input) clock. Control is applied from the selector control circuit 71 to select the output data.

The output data of the selector 41 is shifted by one clock period by flip-flops 17 and 18 and is applied to the selector 42, and is also sent to pattern check circuits 51-53. Pattern check circuits 51-5
3 is a selector control circuit 7 so as to check the check pattern inserted into the empty bit of the data on the transmitting side and cause the selector 42 to select the one that matches the check pattern.
Control from 2. This selection control can prevent bit shifts from occurring in output data due to skipped reading or double reading due to data or clock timing jitter or the like.

[0009]

As explained above, the present invention compares retiming data at intermediate timings of positive-phase and negative-phase clocks to determine whether the data change point is closer to the read timing of the positive-phase or negative-phase clocks. After determining this, select the data that is retimed at the read timing that is farther away from the data change point, and then select the data that matches the check pattern from among the multiple data that are shifted by one clock synchronization. This selection has the effect of being able to prevent bit shifts in output data and eliminating the need to take into account variations in delay in the clock and data transmission systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

[Explanation of symbols]

11-18 Flip-flops 21, 22 Inverter 31 Delay devices 41, 42 Selectors 51-53 Pattern check circuit 61
Data comparison circuits 71, 72 Selector control circuit

Claims (2)

[Claims] 1. A first reading circuit that receives serial received data and a clock signal instructing its read timing, and reads the received data at the read timing of the clock signal; a second reading circuit that reads data at shifted timing; a first selector that selectively outputs one of the read data of the first and second reading circuits;
Comparing third and fourth reading circuits that read the received data at timings shifted by one quarter period and three quarters from the clock signal, respectively, and the read data of both the third and fourth reading circuits. and a first control means for controlling selection of the first selector depending on whether or not the two match. 2. A delay unit having a check pattern inserted into empty bits in the received data, and generating a plurality of read data by shifting the selected output data of the first selector by one cycle of the clock signal. a second selector for selectively outputting one of the plurality of read data from the delay means; and a second selector for detecting the appearance timing of the check pattern among the plurality of read data from the delay means. 2. The in-device serial data receiving circuit according to claim 1, further comprising second control means for controlling selection of said second selector in accordance with said second selector.