JPH04277619A - Method for annealing semiconductor wafer - Google Patents

Abstract

PURPOSE:To provide an annealing method which develops no slip lines or the like by uniforming temperature distribution in a wafer face during annealing. CONSTITUTION:Support bars (5) fitted to a quartz tray (2) extend toward the center point from four ways of its through hole (7), which bars support a wafer susceptor (8). This wafer susceptor (8) is loaded with a guard ring (6) having the same heat conductivity as that of the semiconductor wafer (1), and this wafer (1) is set up inside the through hole (7a). Using this guard ring (6) allows the semiconductor wafer (1) to increase the area effectively and to prevent temperature differences due to heat release from edges.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of annealing semiconductor wafers made of Si, GaAs, InP, or the like.

0002

2. Description of the Related Art When manufacturing semiconductor devices on a semiconductor wafer, the semiconductor wafer is annealed for various purposes. In particular, when manufacturing a semiconductor device on a compound semiconductor substrate such as GaAs, Si ions are implanted to selectively create areas with good electrical conductivity on the substrate and activated by annealing. There are two methods for this activation: one is annealing by indirect heating in an N2 atmosphere in an electric furnace, and the other is annealing by direct heating with radiant heat from a tungsten lamp (referred to as RTA).
method; called Rapid Thermal Anneal method. ) are used in two ways. In the former indirect heating method, it takes time to raise and lower the temperature in the electric furnace, and the time required for annealing is as long as 1 to 2 hours. Therefore, the implanted Si ions diffuse perpendicularly and horizontally to the surface of the semiconductor wafer, deteriorating the characteristics of the semiconductor device, and at the same time, there are problems in that the Si ions become difficult to activate.

In comparison, the latter RTA method using direct heating uses radiant heat from a tungsten lamp, so it can be annealed in a few seconds and the implanted Si ions can be highly activated. This method uses the apparatus shown in FIG. 6(a). A plurality of tungsten lamps 4 are installed side by side in the upper and lower parts of the furnace 3, and the semiconductor wafer 1 is placed on a quartz tray 2. During annealing, the semiconductor wafer 1 is directly heated by these tungsten lamps 4. The quartz tray 2 used in this apparatus 3 includes the one shown in FIG. 6(b). As shown in the figure, support bars 5 are provided from all sides of the through hole 7 of the quartz tray 2 toward the center, and the semiconductor wafer 1 is supported here. Using such a jig, the semiconductor wafer 1 is directly heated by the tungsten lamp 4.

0004

FIG. 7 shows the temperature distribution state within the surface of a semiconductor wafer when annealing is performed by the above-mentioned RTA method. In the figure, the horizontal axis indicates the distance from the center of the surface of the semiconductor wafer, and indicates the temperature distribution in each stage of the temperature increase stage, temperature control stage, and stable state inside the furnace 3. As can be seen from this figure, when the semiconductor wafer 1 is directly heated by radiation only from the top and bottom, a large temperature difference occurs between the edges and the center of the semiconductor wafer during the temperature control stage and in the stable state. . This causes problems such as generation of slip lines in which the crystal itself of the semiconductor wafer is distorted, and activation of ions implanted within the plane of the semiconductor wafer 1 becomes uneven.

Accordingly, the present invention provides a method for annealing semiconductor wafers that solves the above problems.

[0006]

[Means for Solving the Problems] The present invention uses a guard member made of a material having the same thermal conductivity as the semiconductor wafer to closely surround the side surface of the semiconductor wafer, and irradiates the semiconductor wafer and the guard member with radiation. It is characterized by annealing by direct heating.

[0007]

[Operation] According to the present invention, the guard members are disposed so as to surround the side surfaces of the semiconductor wafer during annealing, and since these are placed close to each other, they are effectively covered as one body when radiant heating is performed. It becomes a heating element. For this reason, even if the temperature distribution over the entire surface of the heated object is the same as in the conventional annealing method, the temperature distribution over the entire surface of the heated object is almost uniform on the surface of the semiconductor wafer, which corresponds to the area other than the surrounding area of the heated object. Temperature distribution can be obtained.

[0008]

Embodiments Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a perspective view showing the arrangement on a jig used in an annealing method according to an embodiment of the present invention, and FIG. 2 is a top view and a sectional view taken along the line A--A. A support bar 5 attached to the quartz tray 2 extends from all sides of the through hole 7 of the quartz tray 2 toward the center point, and a wafer susceptor 8 using a Si wafer that is not involved in annealing is supported by the support bar 5. I feel supported. When annealing is performed, the semiconductor wafer 1 to be annealed is placed on the wafer susceptor 8, and the surrounding area is made of a material having approximately the same thermal conductivity as the semiconductor wafer 1 described above, and having the same shape as the semiconductor wafer 1. A guard ring 6 having a slightly larger through hole 7a is installed. Note that it is important to keep the gap between the inner surface of the guard ring 6 and the side surface of the semiconductor wafer 1 at this time to about 1 mm or less, for example, so that the radiant heating can be performed integrally.

By installing the above-mentioned guard ring 6 close to the periphery of the semiconductor wafer 1, the area of the object to be heated by radiation is effectively made larger than the area of the semiconductor wafer 1 to be originally processed. be able to. Therefore, the portion where an undesirable temperature difference occurs can be localized to the guard ring 6.

FIG. 3(a) shows temporal temperature changes inside the furnace 3 during annealing. FIG. 2B schematically shows the temperature distribution of the semiconductor wafer 1 when annealing is performed in the furnace 3 using the above-mentioned guard ring 6. Note that the horizontal axis indicates the distance from the center of the semiconductor wafer 1.

First, in the temperature raising stage in the furnace 3, the upper and lower tungsten lamps 4 are turned on, temperature raising is started, and the temperature of the semiconductor wafer 1 rises (as shown in FIG. 3(a)). At this time,
The temperature of the guard ring 6, which has the same thermal conductivity as the semiconductor wafer 1, also increases. Since the guard ring 6 corresponds to the effective end of the object to be heated including the semiconductor wafer 1, there is no temperature difference between the end of the semiconductor wafer 1 and the guard ring 6 when the inside of the furnace 3 enters a stable state. However, there is no temperature difference between the center and the edges of the semiconductor wafer 1 (see figure (b)).
). FIG. 4 shows temporal temperature changes within the surface of the semiconductor wafer 1. As shown in FIG. As shown,
Since the semiconductor wafer 1 itself corresponds to the central part of the object to be heated by radiation, once it is in a stable state, the temperature distribution over the entire surface becomes almost uniform.

In this example, a guard ring having a shape as shown in FIG. 2 was used, but a guard ring molded into a quarter circle shape as shown in FIG. 5, for example, is used in accordance with the shape of the semiconductor wafer to be annealed. Accordingly, the object of the present invention can be achieved.

[0014]

According to the present invention, it is possible to eliminate temperature differences within the surface of a semiconductor wafer during annealing, thereby eliminating the occurrence of slip lines and warping of the semiconductor wafer. Further, activation of implanted ions, formation of an Si-MOS insulating film, etc. can be performed uniformly within the surface.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing the arrangement on a jig according to an embodiment of the present invention.

FIG. 2 is a top view and a sectional view showing the arrangement on a jig according to an embodiment of the present invention.

FIG. 3 is a diagram showing temporal temperature changes in the furnace during annealing.

FIG. 4 is a diagram showing the temperature distribution within the surface of a semiconductor wafer during annealing.

FIG. 5 is a diagram showing an example of a guard ring used in the present invention.

FIG. 6 is a diagram showing the state inside a furnace in a conventional annealing method.

FIG. 7 is a diagram showing the temperature distribution within the surface of a semiconductor wafer according to a conventional annealing method.

[Explanation of symbols]

1...Semiconductor wafer 2...Quartz tray 5...Support bar 6...Guard ring 7, 7a...Through hole 8...Wafer susceptor

Claims (1)

[Claims] [Claim 1] A guard member made of a material having approximately the same thermal conductivity as the semiconductor wafer is used to closely surround the side surface of the semiconductor wafer, and the semiconductor wafer and the guard member are directly heated by irradiating the semiconductor wafer with radiation. A method for annealing a semiconductor wafer, the method comprising: annealing a semiconductor wafer.