JPH08241871A - Method of manufacturing semicoductor device - Google Patents

Abstract

PURPOSE: To control the resistance value of a semiconductor device to be a desired value by a method wherein a step of holding a substrate at such a temperature that ions are not substantially activated when a temperature of the substrate increases is provided. CONSTITUTION: After a photoresist layer is formed on a semi-insulation GaAs substrate 30, Si ions are implanted to form a first ion implanted layer 34. Next, the photoresist film 34 is removed, a SiN passivation layer 36 is formed on the substrate 30 by plasma CVD. At that time, the substrate 30 implanted with Si ions is heated up to a temperature included in a first temperature zone (300 deg.C to 500 deg.C) of which a width is within 100 deg.C by illuminating it with a radiation or light (for example, infrared rays). Next, after a photoresist layer 38 is formed on the SiN passivation layer 36, S ions are implanted to form a low resistance layer 40. At that time, after the substrate 30 is kept for a specific period (for example, within 60sec.) by the illumination with a radiation or light, the substrate 30 is heated up to a second temperature (800 deg.C to 900 deg.C) by the illumination of a radiation or light.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using an ion implantation technique.

[0002]

2. Description of the Related Art With the rapid development of information communication networks, semiconductor devices used for constructing information communication networks have recently been required to have characteristics such as ultra-high speed operability, low power consumption, and high efficiency. As such a semiconductor device, a Schottky barrier FET is typically used.
(MESFET) and high electron mobility transistor (HEM
T), which are produced by forming an electrically active region on a compound semiconductor substrate such as GaAs or InP.

As a technique for forming an electrically active region on a substrate such as GaAs or InP, a method of selectively implanting impurity ions such as Si into a semi-insulating semiconductor substrate is generally used. Is. To form a channel layer of a transistor, a low resistance layer for reducing source resistance, and a resistance layer of a resistor on a substrate, impurity ions in the substrate are implanted after implanting impurity ions using an ion implantation technique. A method of processing the substrate by an annealing technique that thermally activates ions is used.

The annealing technique is roughly classified into two modes from a method of applying heat to a target substrate. That is, there are an annealing method utilizing heat transfer due to conduction and convection, and an annealing method utilizing heating by radiation or light irradiation. A typical example of the former is a furnace in which a substrate is annealed by inserting it in a high temperature furnace. An annealing method can be cited, and a typical example of the latter method is a lamp annealing method in which infrared rays are applied to the substrate to anneal. Among them, the annealing method utilizing heating by radiation or light irradiation, which can efficiently raise the temperature of the semiconductor substrate in a short time and has a high activation rate of implanted ions, is useful for manufacturing the above semiconductor device. At this time, the resistance values of the channel layer of the transistor, the low resistance layer for reducing the source resistance, and the resistance layer of the resistor are determined by the amount of impurity ions selectively implanted.

In the case of the annealing method, there is a tendency that the substrate is likely to be warped or strained due to thermal history, and the resistance value of the formed semiconductor device is likely to be varied. In this regard, various techniques have been disclosed, for example, a method of making the temperature of the substrate uniform by adjusting the heating rate and the cooling rate during annealing (Japanese Patent Laid-Open No. 62-11421).
8 [Reference 1] and JP-A-2-181916 [Reference 2]), a method of performing a two-step heat treatment of a low temperature long time and a high temperature short time (JP-A 61-63024 [Reference 3]) and a quartz glass plate as a substrate. A method of uniformizing the temperature of the substrate by setting the substrate at a low temperature and performing annealing for a short time (Japanese Patent Laid-Open No. 64-7616 [Reference 4]). Further, a method of increasing the activation rate of ions by adjusting the heating rate (Japanese Patent Laid-Open No. 62-7).
1221 [Reference 5]) is also disclosed.

[0006]

However, none of the methods of the above documents is suitable for controlling the resistance value of the semiconductor device to a desired value in a wide range from a high resistance value to a low resistance value. There wasn't.

Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device that realizes a desired resistance value.

Another object of the present invention is to provide a method of manufacturing a semiconductor device with reduced warpage and distortion.

[0009]

As a result of earnest research in view of the above situation, the present inventor has paid attention to the process of activation of ions implanted in a substrate while the substrate is being heated by radiation or light irradiation. did. As a result of repeated experiments and trials based on this idea, the desired effect can be obtained by providing a step of holding the substrate at a temperature at which ions are not substantially activated during the temperature rise of the substrate. It was

Therefore, in the method for manufacturing a semiconductor substrate according to the present invention, the semiconductor substrate in which the impurity ions are implanted is formed at a temperature at which the ions implanted in the semiconductor substrate are not substantially activated and the width is within 100 ° C. A first step of heating by radiation or light irradiation to a temperature included in the first temperature zone, and a second step of maintaining the semiconductor substrate at a temperature within the first temperature zone for a predetermined time by radiation or light irradiation. And a third step of heating the semiconductor substrate to a second temperature by radiation or light irradiation to activate ions to form a semiconductor device on the semiconductor substrate.

In the method for manufacturing a semiconductor substrate according to the present invention, the first temperature zone is included between a temperature 50 ° C. lower than the second temperature and a temperature 700 ° C. lower than the second temperature. May be a feature.

According to the knowledge obtained by the present inventor, in the process of heating the substrate by annealing using radiation or light irradiation, the substrate is kept for a certain period of time at a temperature at which the ions implanted in the semiconductor substrate are not substantially activated. By maintaining it, it is possible to obtain a substrate in which a large number of impurity ions with increased activity are stably present at the site that gives n-type upon activation of the impurity ions. The present inventor speculates as to this phenomenon as follows: ions are randomly present with respect to their position in the substrate immediately after implantation, but are kept at a temperature at which the ions are not activated when the substrate is heated. By performing the temperature increase including the step of, the ions selectively enter the site giving the n-type.

Furthermore, by maintaining the temperature of the substrate in the first temperature zone for a certain period of time during the heating of the substrate, the unevenness of the substrate temperature that occurs during the temperature raising process is alleviated.

Here, the "temperature zone" is a set of all temperatures from a certain lower limit temperature to a certain upper limit temperature,
The "width of the temperature zone" is the lower limit temperature subtracted from the upper limit temperature. From the viewpoint of the stability of the annealing operation, it is preferable that both the lower limit temperature and the lower limit temperature of the temperature zone are substantially constant, and therefore the width of the first temperature zone is also substantially constant.

The first temperature zone having a certain width may be formed at a temperature lower than the second temperature for activating ions, and preferably 50 ° C. higher than the second temperature. It may be included in the low temperature to 700 ° C. lower temperature, and more preferably in the temperature group that is 200 ° C. lower to 600 ° C. lower than the second temperature. Particularly preferably, the first temperature zone may be included in a temperature group that is 400 ° C. lower to 500 ° C. lower than the second temperature. The width of the first temperature zone is
The temperature range is preferably about 100 ° C., more preferably the first temperature zone may have a width of about 50 ° C., and particularly preferably,
It may have a width of about 30 ° C.

The method for manufacturing a semiconductor substrate according to the present invention may be characterized in that the temperature in the first temperature zone is further included in a temperature lower than the growth temperature of the semiconductor layer of the semiconductor substrate.

In the process of heating the substrate, the substrate is held for a certain period of time in a first temperature range consisting of a temperature lower than the activation temperature of the ions implanted in the substrate and lower than the growth temperature of the semiconductor layer. Thereby, particularly when a semiconductor substrate having a semiconductor layer having a crystallized control is used, the activity of impurity ions at a site in the semiconductor that imparts n-type is stably enhanced while maintaining the crystal structure of the controlled semiconductor layer and the like. be able to.

Further, the method of manufacturing a semiconductor substrate according to the present invention may be characterized in that the radiation or light irradiation is irradiation of infrared rays.

In the so-called lamp annealing method using infrared rays, while high ion activation can be obtained in a short time, the temperature of the substrate rises rapidly, but the present invention includes a step of maintaining the temperature of the substrate when raising the temperature. According to the method of 1, the nonuniformity of the temperature of the substrate is alleviated even when the temperature rises rapidly.

The semiconductor substrate manufacturing method according to the present invention may be characterized in that the semiconductor substrate is a semiconductor substrate selected from the group consisting of a GaAs substrate and an InP substrate.

In the method of manufacturing a semiconductor substrate according to the present invention, the semiconductor substrate is a semi-insulating GaAs substrate, the impurity ions are Si ions, and the first temperature zone is 30.
It may be characterized by being included between 0 ° C and 550 ° C.

The semiconductor substrate manufacturing method according to the present invention may be characterized in that the predetermined time in the second step is within 60 seconds.

In the method of manufacturing a semiconductor substrate according to the present invention, the second temperature is included between 800 ° C. and 900 ° C., and the time from the start of the first step to the end of the third step is 10 times. It may be characterized by being within minutes.

For manufacturing a semiconductor device such as MESFET or HEMT, a GaAs substrate or an InP substrate is preferably used, and a semi-insulating GaAs substrate may be preferably used. In that case, Si may be preferably implanted into the substrate as impurity ions.

When Si ions are implanted into a semi-insulating GaAs substrate and activated by using infrared rays, a temperature having a fixed upper and lower limit temperature in the range of 300 ° C. to 550 ° C. when the substrate is heated. Ga in GaAs is provided by providing a step for holding the substrate within 60 seconds in the band.
It is considered that Si, which exists randomly regardless of the sites or As sites, selectively enters the As sites that give the n-type and is activated. When lamp annealing using infrared rays is used to manufacture a semiconductor device such as MESFET or HEMT using the above-mentioned materials, it is necessary to keep the temperature of the substrate high because the characteristics of the manufactured semiconductor device are not deteriorated. The total time required for the annealing including may be 10 minutes or less.

When performing the annealing according to the present invention after implanting Si ions into the GaAs substrate, it is more preferable to set the first temperature zone to 350 to 550 ° C., and particularly preferable. It may be 450 to 500 ° C. At this time, the time for holding the substrate at the temperature within the first temperature zone may be preferably 60 seconds or less, more preferably 40 seconds or less, and particularly preferably 20 seconds or less. You may hold | maintain in the temperature zone of. At this time, the time from the start of the first step to the end of the third step may be preferably within 5 minutes, more preferably within 3 minutes, and particularly preferably within 1 minute.

The semiconductor substrate manufacturing method according to the present invention may be characterized in that the sheet resistance of the semiconductor device is 400 ohms or more.

Further, the method for manufacturing a semiconductor substrate according to the present invention may be characterized in that the semiconductor device is selected from one or more of a group consisting of a field effect transistor, a high electron mobility transistor and a resistor. .

[0029]

Embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the same elements in the drawings will be denoted by the same reference numerals and redundant description will be omitted.

FIG. 1 shows an infrared lamp annealing furnace used for the lamp annealing treatment in this embodiment.
1A is a top view of the lamp annealing furnace 10, and FIG. 1B is a side view thereof. The lamp annealing furnace 10 used in this embodiment is a commercially available general lamp annealing apparatus.

As shown in FIGS. 1 (a) and 1 (b),
The lamp annealing furnace 10 includes a furnace body portion 12 that accommodates and heats a wafer. The furnace body 12 is a lamp holding ring 1
4 has a lamp 16 (indicated by a dotted line) supported therein. An actual device is equipped with 48 1.6 kW rod-shaped halogen lamps 16, but for ease of illustration, 11 lamp holding rings 14 are provided at the top and bottom, and 16 lamps 16 are provided.
Only the book is shown in FIGS. 1 (a) and 1 (b). An IR sensor mount 18 for mounting an IR sensor for detecting and controlling the temperature in the lamp house is provided in the furnace body 12. The heating temperature range of the lamp annealing furnace 10 is 40
The temperature is 0 ° C to 1200 ° C (600 to 1200 ° C when closed loop control is performed by an IR sensor). In addition, the rating of the lamp annealing furnace 10 is as follows.

Wafer size: Maximum 6 inches (about 152.4 m
m) High temperature use time: 1100 ° C. for 600 seconds Wafer surface temperature distribution: maximum +/− 5.0 ° C. (within 10 mm from wafer edge) Temperature reproducibility: maximum +/− 5.0 ° C. Temperature rising rate: Up to 200 ° C / sec. Cooling rate: Maximum natural cooling rate Cooling of furnace body: Cooling by water cooling jacket Structure of furnace body: Reflector structure FIG. 2 is a top view of the susceptor 22 in which the wafer 20 is arranged inside the furnace body portion 12, It shows how wafers are housed inside. As shown in FIG. 1 (b),
A susceptor 22 made of Si (shown by a dotted line in FIG. 1B) on which a wafer 20 (shown by a dotted line in FIG. 1B) is arranged, and a guide rail 24 (shown by a dotted line in FIG. 1B) are shown. ) It is inserted into the furnace body 12 while being attached to the tip (not shown) of the loader arm fixed to the upper slide bearing (not shown). Susceptor 2 at this time
A view from above of 2 is shown in FIG.

Regarding the method for measuring the temperature of the wafer,
As shown in FIG. 2, a thermocouple 26 was embedded in the susceptor 22, and the temperature detected by the thermocouple 26 was used as the wafer temperature.

(Example: Fabrication of Resistor on Semi-insulating GaAs Substrate) FIGS. 3A to 3F are sectional views of the GaAs substrate, and a method of fabricating the resistor in this example. Represents the flow of. In this embodiment, Si ions are implanted by an ion implantation method on a semi-insulating GaAs (hereinafter referred to as SI GaAs) substrate on which a resist layer is formed, and the lamp annealing furnace 10 shown in FIG. 1 is used. A resistor was produced by activating Si ions.

3 inches (about 76.2 mm) of semi-insulating G
After the photoresist layer 32 is formed on the aAs substrate 30 (see FIG. 3A), the acceleration energy is 120 (keV) and the dose is 4 × 10 ¹² (cm 2) by the ion implantation method.
^-2 ) Si ion with a mass number of 29 (hereinafter referred to as Si ⁺ )
To form a first ion-implanted layer 34 (see FIG. 3).
(B)).

After forming the first ion-implanted layer 34, the resist layer 32 is removed with acetone, and S. I. GaAs substrate 3
A SiN passivation layer 36 was formed on the surface of No. 0 by plasma CVD (see FIG. 3C). This Si
The N passivation layer 36 is for preventing the desorption of As from the substrate in the later annealing.

Next, after forming a new photoresist layer 38 on the SiN passivation layer 36, the acceleration energy is 90 (keV) and the dose amount is 6 × 10 ¹³ (cm ^-2 ).
Then, Si ⁺ was injected to form an n ⁺ layer 40 (that is, a low resistance layer) (see FIG. 3D).

After forming the n ⁺ layer 40, the substrate 30 is formed as shown in FIG.
2 is placed on the Si susceptor 22 in a state as shown in FIG. 2 (the SI GaAs substrate 30 of this embodiment corresponds to the substrate 20 in FIG. 2) in the lamp annealing furnace 10 shown in FIG. It was delivered.

FIG. 4 is a chart of the temperature detected by the thermocouple 26 shown in FIG. 2, and shows the temperature rise profile of the substrate 30 during the annealing of this embodiment. The substrate 30 after the photoresist 38 has been removed with acetone is
It was put in the lamp annealing furnace 10 shown in FIG. 1 and heated by the lamp 16 (see FIG. 3E). At this time, as shown in FIG.
After raising the temperature to 0 ° C. in about 20 seconds, about 470 ° C. to about 50
Hold at 0 ° C (first temperature zone, width is about 30 ° C) for about 20 seconds, then raise the temperature again to about 870 ° C (second temperature).
Up to about 10 seconds. After reaching about 870 ° C., the lamp 16 was switched off and the substrate 30 was left as it was. In this way, Si ⁺ of the first ion implantation layer 34 and the n ⁺ layer 40 was activated.

Then, the substrate 30 is patterned again with a photoresist (not shown) to form an ohmic metal (Au).
Ge / Ni) is deposited and lifted off, then 450 ° C. 1
The alloy was heated and alloyed under the condition of a minute, the ohmic electrode 42 was formed, and the resistor was completed. The sheet resistance of this resistor was 600 ohms.

3 with a resistor made as described above
Inch (about 76.2 mm) S.M. I. When the warpage of the GaAs substrate was measured, a maximum warpage of 2 μm was recognized in the diameter direction. The value of this warp is a value that is allowed without any problem with respect to the pattern alignment accuracy in the semiconductor manufacturing process after the annealing step.

Further, in this embodiment, in order to confirm the variation of the sheet resistance with respect to the Si ⁺ dose amount, 10 types of dose amounts are set, and a large number of resistors are produced for each dose amount by the above method, Their sheet resistance was measured. FIG. 5 is a graph showing the relationship between the Si ⁺ dose amount and the sheet resistance. In FIG. 5, the sheet resistance with respect to the dose amount of the resistor manufactured in this example is plotted in a triangle, and the variation of the sheet resistance with respect to each dose amount is also shown with the width of the mark [I]. As shown in FIG. 5, the resistor manufactured in this example has a resistance of about 320 (ohm) to about 72 (ohm).
It was confirmed to give a stable sheet resistance for a relatively high sheet resistance of 0 (ohm).

Comparative Example: Fabrication of Resistor on Semi-Insulating GaAs Substrate by Raising Temperature without Step of Holding Substrate in Constant Temperature Zone For the purpose of confirming the effect of the present invention,
S. I. After implanting Si ⁺ on the GaAs substrate, lamp annealing was performed according to a method conventionally used to manufacture a resistor.

As shown in FIG. 4, the method of manufacturing the resistor does not include a step of holding the substrate in a constant temperature zone at the time of annealing, and the temperature is raised from 200 ° C. to 870 ° C. in about 20 seconds. The procedure was the same as that of the example according to the present invention except that the temperature rising profile was used, that is, the steps shown in FIG. Then, similar to the example according to the present invention, five kinds of dose amounts were set, a large number of resistors were produced for each dose amount by the same method, and their sheet resistances were measured.

A 3 inch S.T. with a resistor made in the comparative example. I. When the warpage of the GaAs substrate was measured, a maximum warpage of 10 μm was confirmed in the diameter direction. This is a value that has a considerable influence on the pattern alignment accuracy in the semiconductor manufacturing process after the annealing step, and further causes a reduction in product yield.

Similarly to the embodiment, the sheet resistance with respect to the dose amount is plotted in a circle in FIG. 5, and the variation of the sheet resistance at each dose amount is shown by the width of the mark [I]. As shown in FIG. 5, the range of variation in sheet resistance at each dose amount is very large. Comparing this with the width of the variation in the example, the difference is very remarkable.

As described above, the features of the present invention have been described with the preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made. For example, when raising the temperature for activation of Si ⁺ , the temperature band for holding does not need to be limited to about 470 ° C. to about 500 ° C. as described above, but may be any temperature between 300 ° C. and 550 ° C. You may perform in a temperature zone. Further, the substrate is made of InP, ZnSe, In
A substrate such as Sb may be used. The impurity ions include tin ions, selenium ions, p
Beryllium ions or magnesium ions may be used as the type ions. In that case, the temperature range of holding does not depend on the temperature range of the above range, but depends on the activation temperature of such ions.

Further, for example, the holding temperature of about 470 ° C. to about 500 ° C. at the time of temperature rise in the above embodiment is not only lower than the activation temperature of Si ⁺ , but also the growth temperature of GaAs (about 550 ° C. It is also lower than about 700 ° C).
Therefore, as a modification of this embodiment, the S. I. The resistor may be formed by the above method using a substrate in which crystal-controlled GaAs is formed on the GaAs substrate by the MOCVD method or the like.

For example, in lamp annealing using infrared rays, the activation temperature of Si ⁺ in the GaAs substrate is set to about 600 ° C. to 650 ° C., and the time required for the entire temperature rise is set to about 30 minutes. Hold temperature band at 3
The resistor may be formed on the GaAs substrate by providing a step of holding for about 5 to 6 minutes as an arbitrary temperature zone within 50 ° C to 500 ° C.

[0050]

As described above in detail, according to the method of the present invention, in the process of raising the temperature of the semiconductor substrate in which the impurity ions are implanted by using annealing by radiation or light irradiation, the ions are substantially removed. By performing a temperature raising step including an operation of maintaining the temperature of the substrate at a temperature included in the first temperature zone having a constant width and having a constant width, the site of n-type is given, It is possible to obtain a substrate in which a large number of impurity ions with increased activity are stably present.

Further, according to the method of the present invention, by performing the temperature raising process including the operation of maintaining the temperature of the substrate at the temperature included in the first temperature zone, the temperature of the substrate generated during the temperature raising process is not affected. Uniformity is relaxed.

Therefore, it becomes possible to manufacture a semiconductor device including a resistor with stable sheet resistance and less warpage or distortion.

[Brief description of drawings]

1 is a lamp annealing furnace used in Examples,
(A) is a top view and (b) is a side view.

FIG. 2 is a top view of a susceptor.

FIG. 3 is a cross-sectional view of a GaAs substrate in an example and a comparative example, showing steps of the example and the comparative example in the order of (a) to (f).

FIG. 4 is a graph showing a substrate temperature profile in annealing, where is a substrate temperature profile of the example,
Represents the substrate temperature profile of the comparative example.

FIG. 5 is a graph showing the relationship between Si ⁺ dose and sheet resistance.

[Explanation of symbols]

10 ... Lamp annealing furnace, 12 ... Furnace body part, 14 ... Lamp holding ring, 16 ... Lamp, 18 ... IR sensor mount, 20 ... Wafer, 22 ... Susceptor, 24 ... Guide rail, 26 ... Thermocouple, 30 ... Half Insulating GaAs substrate, 32
... Photoresist, 34 ... First ion-implanted layer, 36 ...
SiN passivation layer, 38 ... Photoresist, 4
0 ... N ⁺ layer, 42 ... Ohmic electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/778

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device using annealing by radiation or light irradiation, wherein the semiconductor substrate in which impurity ions are implanted is not substantially activated by the ions implanted in the semiconductor substrate. It consists of temperatures and the width between the upper limit temperature and the lower limit temperature is 1
A first step of heating the semiconductor substrate by radiation or light irradiation to a temperature included in the first temperature zone that is within 00 ° C., and within the first temperature zone for a predetermined time by the radiation or light irradiation. And a second step of maintaining the temperature of the semiconductor substrate by the radiation or light irradiation to heat the semiconductor substrate to a second temperature higher than the upper limit temperature of the first temperature zone to activate the ions, And a third step of forming a semiconductor device on a semiconductor substrate. 2. The first temperature zone is included between a temperature 50 ° C. lower than the second temperature and a temperature 700 ° C. lower than the second temperature. A method of manufacturing a semiconductor device according to item 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the first temperature zone is further included in a temperature lower than a growth temperature of a semiconductor layer of the semiconductor substrate. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the radiation or light irradiation is infrared irradiation. 5. The semiconductor substrate is a GaAs substrate and In.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a semiconductor substrate selected from the group consisting of a P substrate. 6. The semiconductor substrate is a semi-insulating GaAs substrate, the impurity ions are Si ions, and the first temperature zone is included between 300 ° C. and 550 ° C. The method for manufacturing a semiconductor device according to claim 4. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the predetermined time in the second step is within 60 seconds. 8. The second temperature is included between 800 ° C. and 900 ° C., and the time from the start of the first step to the end of the third step is within 10 minutes. The method for manufacturing a semiconductor device according to claim 7. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the sheet resistance of the semiconductor device is 400 ohms or more. 10. The semiconductor device formed on the semiconductor substrate is selected from the group consisting of a field effect transistor, a high electron mobility transistor, and a resistor. 10. The method for manufacturing a semiconductor device according to any one of 1 to 9.