JPH04271642A - Line simulator - Google Patents

Abstract

PURPOSE:To realize the line simulator setting optionally an error of a data used for a test and grasping quantitatively an error correction capability or the like at a receiver side. CONSTITUTION:The simulator is provided with a line simulator circuit 2 comprising a noise generator 4 inputting noise to a data such as a moving picture, a still picture and a sound or the like compressed by a compressor 1 at a sender side and a storage device 5 with the data written once therein and reading the data with a delay, and an expander 3 is used to expand the data for the reception at the receiver side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulator device for testing error correction ability, etc. in a communication line system.

0002

[Prior Art] Conventionally, when testing the line of equipment such as satellite communication, especially when testing equipment that performs digital communication, digital data is converted from the transmitting side to an RF signal and transmitted. A data error is generated by intentionally degrading the C/N, and the receiving side receives this signal and performs error correction. The line is tested by checking its error correction ability and operation. .

0003

[Problem to be solved by the invention] With such conventional line testing methods, it is difficult to freely set the data errors that occur on the transmitting side, so it is difficult to quantitatively understand the error correction ability etc. on the receiving side. There is a problem in that it is difficult to perform tests that accurately recognize the line status. SUMMARY OF THE INVENTION An object of the present invention is to provide a line simulator device that makes it possible to quantitatively understand the error correction ability and the like on the receiving side.

0004

[Means for Solving the Problems] The line simulator device of the present invention includes a noise generator that inputs noise into data such as moving images, still images, and audio compressed on the transmitting side, and a noise generator that inputs noise into data such as compressed moving images, still images, and audio. It is equipped with a line simulator circuit consisting of a memory device that reads out the data with a delay. This is because in digital communications over satellite lines or wired lines, line errors occur as a code error of 0 or 1 in the digital data, so it is possible to replace the line with a digital circuit as an equivalent circuit. Due to the fact that For example, the noise generator includes a random pulse generator and a data modification circuit that inputs the generated random pulses into data, and the memory includes a memory and a write address generator that writes data to the memory. and a read address generator for reading data from the memory.

[0005]

According to the present invention, any data error can be generated by controlling the noise generator, and any data delay can be generated by controlling the storage element.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, an input S1 of still images, moving images, audio, etc. is converted into digital compressed data S2 through a compression device 1, and is input to a line simulator circuit 2. Noise and delay are applied to the data S3 in the line simulator circuit 2, and the data S3 is input to the expansion device 3, where the data is expanded and restored to the original data S4. The line simulator circuit 2 includes a noise generator 4 that generates data errors by adding noise to digital data, and a memory 5 that generates line delays by delaying data transmission timing.

FIG. 2 is a block diagram showing a specific example of the line simulator circuit 2. As shown in FIG. The noise generator 4 includes a random pulse generator 11, a data modification circuit 12 that adds the random pulse to input data, and a serial/parallel shift register 13. Further, the storage device 5 includes a memory 14, a write address generator 15, a read address generator 16, and a parallel/serial shift register 17.

According to such a line simulator device, serial data S2 sent from the compression device 1 is input to the data changing circuit 12. Data change circuit 12
Then, at the same time, a random pulse generated by the random pulse generator 11 is inputted, data is changed in the data S2 during the pulse generation period, and a data error is generated. At this time, the data error rate can be grasped from the data of the random pulse generator 11. Data S21 containing errors
is passed through the serial/parallel shift register 13 to become parallel data S22, and then stored in the memory 14 using the write address A1 from the write address generator 15. The stored data is read from the memory 14 by the read address A2 from the read address generator 16, but at this time, a delay amount is set based on the time difference between the read address A2 and the write address A1, and the data S23 is read out with a delay. . This delayed data S23 passes through the parallel/serial shift register 17 to become serial data S3, and is further expanded by the expansion device 3 to become receiving side data S4.

Therefore, in this line simulator device, by controlling the data change circuit 12, it is possible to manage random pulses, ie, noise, input into data. Further, by controlling the write address generator 15 and the read address generator 16, the amount of delay can be arbitrarily set. This makes it possible to generate arbitrary data errors, and to quantitatively test the error correction ability and the like on the receiving side using data including this data error.

0010

[Effects of the Invention] As explained above, in the present invention, a line simulator circuit is configured by a noise generator that inputs noise into data, and a memory element that once writes data and then reads it out with a delay. Therefore, data errors can be set arbitrarily by controlling the noise generator and memory element, and by conducting tests using these data errors, it is possible to quantitatively test error correction ability, etc. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a line simulator device of the present invention.

FIG. 2 is a block diagram showing the internal configuration of a line simulator circuit.

[Explanation of symbols]

1 Compression device 2 Line simulator circuit 3 Stretching device 4 Noise generator 5. Memory device 11 Random pulse generator 12 Data change circuit 14 Memory 15 Write address generator 16 Read address generator

Claims (2)

[Claims] Claim 1. A communication line system in which data such as moving images, still images, audio, etc. is compressed on the transmitting side and transmitted through a satellite line or wired line, and the received data is expanded and received on the receiving side. The circuit is equipped with a line simulator circuit consisting of a noise generator that inputs noise into the data, and a memory device that once writes the data and then reads it out with a delay. A line simulator device characterized in that it is configured to be set to an equivalent line. 2. The noise generator includes a random pulse generator and a data modification circuit that inputs the generated random pulses into data, and the storage device includes a memory and a write address generator for writing data into the memory. 2. The line simulator device according to claim 1, further comprising a read address generator for reading data from the memory.