JPH0426788B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit memory, and particularly to a semiconductor integrated circuit memory that achieves a large capacity without increasing the planar area.
The present invention relates to a large-scale semiconductor memory suitable for large-scale expansion. [Prior art] As a type of semiconductor integrated circuit memory, MOS dynamic memory was developed in the early 1970s as 1Kb dynamic random access memory (dRAM).
Since its release, it has quadrupled in size in three years. However, 16-pin DIP (dual-in-package) has been mainly used as the package for storing memory chips, and the size of the cavity for storing chips is also limited. Even with age, it has only increased by 1.4 times at most. Therefore, the memory cell area for 1 bit, which is 1 storage capacity, has decreased significantly as the scale has increased.
As the scale has increased four times, it has also become smaller by about 1/3. The capacitance C of the capacitor is C=εA/t (where ε: dielectric constant of the insulating film, A: capacitor area, t:
Therefore, if the area A becomes 1/3, C will also become 1/3 as long as ε and t are the same.
As a storage capacity, the signal amount S is proportional to the electrification amount Q, and since this Q is the product of C and voltage V, as A becomes smaller, Q also becomes smaller in proportion, and the signal S becomes smaller accordingly. becomes smaller. If the noise is N, the S/N ratio decreases as S decreases, which poses a major problem in rotational operation.
Therefore, the decrease in A is usually compensated for by the decrease in t, and as the scale increases to 4Kb, 16Kb, and 64Kb, the typical SiO ₂ film thickness is 100nm,
It has become thinner to 75nm and 50nm. Furthermore, it has recently been confirmed that α particles emitted from heavy metals (U, Th, etc.) contained in packages etc. generate a charge of about 200 fC in the Si substrate, which becomes noise, and it has been confirmed that the amount of signal is Q is almost
It has become difficult to keep the temperature below 200fC. Therefore, attempts have been made to further accelerate the thinning of the insulating film, and this time dielectric breakdown of the insulating film has become a problem. The dielectric strength electric field of SiO ₂ is maximum
10 ⁷ V/cm, therefore, 10 nm of SiO ₂ is almost permanently destroyed or degraded by applying 10 V. Furthermore, in consideration of long-term reliability, it is important to use a voltage as low as possible from the maximum breakdown voltage. Japanese Unexamined Patent Publication No. 51-130178 discloses a structure in which the capacitor area A is maintained or increased without reducing the insulating film thickness even when the memory cell is miniaturized. The gist of this technology is to increase the electrode area without increasing the planar area by using the sidewalls of the grooves dug into the Si substrate as the electrode surfaces of the capacitor. Thereby, a desired capacitance can be obtained without making the insulating film thinner and increasing the breakdown of the insulating film. Figure 1 shows the configuration of a one-transistor type dynamic memory cell using insulated gate field effect transistors (hereinafter referred to as MOS transistors).
It consists of a MOS transistor 2, the drain of which is connected to a bit line 3, and the gate connected to a word line 4. The operation is performed by reading out the signal charge stored in the capacitor 1 by the switch transistor 2. To construct an actual N-bit memory, there are two methods for constructing a memory array, which are broadly classified as follows. FIG. 2 shows a so-called "open bit line" configuration in which bit lines 31 and 32 are arranged on both sides of a sense amplifier 5 that takes out signals differentially. In this case, only one bit line 31 electrically crosses one word line 41, and the difference between the signals on the bit lines 31 and 32 is detected by the sense up 5. FIG. 3 shows the other "folded bit line" configuration, in which two bit lines 31 and 32 connected to the sense amplifier 5 are arranged in parallel, and one word line 41 is arranged in parallel. It intersects the bit lines 31 and 32 of the book. Although the embodiments of the present invention to be described later mainly show cases of folded bit line configurations, they are also applicable to open bit line configurations. As shown in FIGS. 2 and 3, if the value of the parasitic capacitance 6 of the bit line 32 is C _D and the value of the capacitor 12 of the memory cell is C _S , then one of the main performance indicators of this memory array is becomes C _S /C _D. The S/N ratio of this memory array has a one-to-one correspondence with C _S /C _D. Increasing the capacitor value of the memory cell and simultaneously reducing the parasitic capacitance C _D of the bit line will also improve the S/N ratio. This will improve the results. FIG. 4 shows an example of a plane of a memory cell of the folded bit line type. A part of the active region 7 surrounded by a thick field oxide film, usually 100 nm or more, is covered with a plate 8 to form a capacitor. The part that forms the switch transistor
The plate is selectively removed from the contact hole 9 (region 80) for connecting the drain heavy line electrode on the Si substrate, and the word lines 41, 4
2 is deposited to form a switch transistor 2. To aid understanding, FIG. 5 shows a cross-sectional view of the portion indicated by AA in FIG. 4. For convenience of explanation, an example using an n-channel type transistor will be shown below. To make a p-channel type, generally the conductivity types of the Si substrate and the diffusion layer can be reversed from those for an n-channel. Usually on a p-type Si substrate 10 of about 10 Ω cm.
A field SiO ₂ film 11 with a thickness of about 100 to 1000 nm is
The so-called using _Si3N4 as _an oxidation-resistant mask
Deposit selectively using LOCOS method, etc. After this 10~
A gate oxide film 12 with a thickness of 100 nm is deposited on the Si substrate 10 by thermal oxidation or the like. After this, Rin
Plate 8 represented by polycrystalline Si doped with As
is selectively deposited, and this polycrystalline Si plate 8 is oxidized to form a first interlayer oxide film 13. After that, the word line 4 made of polycrystalline Si, Mo silicide, or refractory metal (Mo or W) is deposited, and ions of phosphorus, As, etc. are implanted, and the plate 8 and the word line 4 are not deposited. An n ⁺ diffusion layer 15 is formed in the active region and becomes the source and drain of the switch MOS transistor 2. After this, PSG 14 containing phosphorus is deposited to a thickness of 500 to 1000 nm by the so-called CVD method, and contact holes 9 are formed where the bit line 3, represented by the Al electrode, is connected to the diffusion layer 15. 3 is selectively applied. In this memory cell, the region 16 of the capacitor 1, which serves as the storage capacity, is the shaded area in FIG. Unless the capacitor capacity is
C _S becomes small, which causes a big problem in memory operation. Therefore, one method of increasing the capacitance is to form a capacitor by providing a groove in the substrate. [Problems to be Solved by the Invention] However, the method of forming a capacitor by providing a groove in a substrate has a major problem with regard to memory cells. One of them is leakage current between memory cells. In conventional planar memory cells, leakage current between memory cells occurs under the element isolation insulating film near the substrate surface. Therefore, since the impurity concentration on the substrate surface is usually high due to ion implantation using a channel stopper or the like, leakage is less likely to occur. Furthermore, the area near the surface of the substrate was also affected by the potential of the wiring on the substrate, and leakage was also less likely to occur due to this. However, in the method of constructing a capacitor by providing a groove in a substrate, since a deeply dug groove is used as a capacitor, it has been found that leakage current is generated inside the substrate rather than on the surface of the substrate. This is more likely than traditional board surface leakage, e.g.
It has been found that leakage current becomes a problem in trench type memory cells even though the memory cell spacing does not cause problems in planar type memory cells. An object of the present invention is to provide a large-scale semiconductor memory in which leakage current between capacitances of trench-type capacitive memory cells is less likely to occur. [Means for Solving the Problems] In order to achieve the above object, the present invention provides at least means for preventing depletion layer extension, that is, means for reducing leakage current, between adjacent trench memory cells. . [Function] The leakage current between the trench capacitances is related to the extension of the depletion layer, and by preventing this extension, the leakage current can be reduced. In addition, the influence of electrons or holes is also related to the elongation of the depletion layer, and by preventing this elongation,
The influence of alpha rays etc. can be reduced. [Example] The present invention will be described below with reference to the drawings. 6 to 20 show trench type memory cells more suitable for applying the present invention. First, the manufacturing method will be explained. As shown in Figure 6, a p-type 10Ωcm Si substrate 1
500-1000nm by the LOCOS method described above.
A thick field SiO ₂ film 11 is selectively formed.
The same process can be achieved by forming this field SiO ₂ film and then removing unnecessary portions by photo-etching or the like. In the description of the invention, LOCOS
The law shall be used. After this, as shown in FIG. 8, parallel plate plasma etching is performed using F or Cl gases such as CF ₄ , SF ₆ , CCl ₄ as the main components, or a gas containing H in these. An etched groove 17 is formed in a predetermined portion of the Si substrate 10. This plasma etching mask is made with the structure shown in Figure 6 in advance, since if the mask is made of ordinary photoresist, the photoresist itself may be etched and disappear.
Films of SiO ₂ , Si ₃ N ₄ , and CVDSiO 2 are deposited on the Si substrate 10 in the order of SiO 2 , Si 3 N 4 , and CVDSiO ₂ . First, the top layer of CVDSiO ₂ is etched into a photoresist mask, and then the lower layer is etched into a photoresist mask.
Si ₃ N ₄ and SiO ₂ may be etched, and the Si substrate 10 may be etched using these as a mask. this
The Si ₃ N ₄ film prevents the field SiO ₂ film 11 from being etched when the CVDSiO ₂ serving as a mask is finally removed. Therefore, other membranes may be used as long as they meet this purpose. At least, these three-layer films of CVDSiO ₂ /Si ₃ N ₄ /SiO ₂ are mask materials and will be removed eventually and will not remain on the Si substrate. Therefore, the mask material is not limited as long as it meets this purpose. Alternatively, if a fine beam can already be formed, the desired etching groove 17 can be obtained without a mask material. In principle, there is almost no limit to the depth of the etching groove 17, but if the width of the groove is W _M , then the depth D _M
is realistically about 0.5W _M to 5W _M. After this, a capacitor insulating film is formed. In principle, this insulating film can be made of any material as long as it has a high electrical breakdown voltage and is stable, but the materials traditionally used are thermally oxidized SiO ₂ and thermal nitrogen.
Examples include Si ₃ N ₄ , CVDSi ₃ N ₄ , Ta ₂ O ₅ by CVD or reactive sputtering, Nb ₂ O ₅ , GrO _{2 ,} etc. These films can be made into a single layer or multilayer to form a capacitor insulating film. In this example, a case will be explained in which a stacked film of SiO ₂ and Si ₃ N ₄ is used. Grooves formed in the Si substrate 10 by dry etching (plasma etching, sputter etching, etc.) cause more or less electrical crystal damage and contamination to the Si substrate 10, unlike in the case of solution etching. Therefore, after dry etching, 10
Solution etching may be performed to a depth of about 500 nm to the extent that the damage and contamination described above do not effectively pose a problem. As a solution, NH ₄ OH + H ₂ O ₂ system or HF +
Aqueous solutions based on HNO ₃ are well suited for this purpose. As shown in Figure 9, Si
After removing the surface of the substrate 10 and its grooves 17, a capacitor SiO ₂ film 18 with a thickness of 5-20 nm is deposited.
Formed by thermal oxidation at 900-1200℃ in an oxidizing atmosphere. Thereafter, a capacitor Si ₃ N ₄ film 19 is deposited to a thickness of 5 to 20 nm by CVD at 650 to 850°C. Since these film thicknesses are set in consideration of the desired capacitance per unit area and withstand voltage, they may deviate from the above-mentioned film thickness ranges. This CVDSi ₃ N ₄ 19 generally has an internal stress of 1×10 ¹⁰ dyn/cm ² and is strong, so if it is directly deposited on the Si substrate 10, defects will occur and the characteristics will be impaired. Therefore, in general
SiO ₂ is placed under Si ₃ N ₄ . This is not the case when directly nitriding the Si substrate 10 to form a Si ₃ N ₄ film, and a dense film with high electrical breakdown voltage can be obtained, but in order to obtain a film thicker than 10 nm,
Requires reaction time of over 1 hour. Furthermore, since the rate of increase in film thickness decreases rapidly when the thickness exceeds 10 nm, it is not appropriate to obtain a thick film. Also these
The surface of the Si ₃ N ₄ film 19 can be oxidized by 2 to 5 nm to improve the breakdown voltage. Thereafter, as shown in FIG. 10, a plate 8 made of polycrystalline Si is deposited on the entire surface. Polycrystalline Si deposited by the CVD method often goes around the inside of the groove 17 and is deposited, so the polycrystalline Si on the side wall of the groove 17
The film thickness is almost the same as that of the upper surface. Then this polycrystal
Thermal diffusion of phosphorus is performed on Si using POCl ₃ gas, etc. Since the width of the etched groove 17 is W _M , if the thickness of the polycrystalline Si 8 is T _S1 , if W _M > 2T _S1 , a groove (groove width 2T _S2 ) as shown in Fig. 10 remains. do.
Since this groove adversely affects the insulating film deposited on its upper surface and the processing and deposition condition of the word line 4, it is better to fill it. In this application example, as shown in Fig. 10, the same polycrystalline Si is deposited on the entire surface with a thickness of T _S2 ,
After that, when the entire surface is removed by the thickness of T _S2 by plasma etching using well-known CF ₄ or SF ₆ gas, polycrystalline Si 82 remains just buried in the groove, as shown in Figure 10, and the top surface is It becomes flat.
If the trench is filled with only one deposition of polycrystalline Si 8, there is no need for a second deposition, but since the plate 8 is also used as a wiring part, an appropriate thickness is required.
It is about 100 to 500 nm. If this does not fill the area, use the double deposition method of polycrystalline Si as explained above. If a second polycrystalline Si layer is directly deposited on top of the polycrystalline Si layer 8 and the entire surface is etched, the end point of the etching becomes unclear because the boundary between the two layers is fused. Therefore, the surface of the first layer of polycrystalline Si8 is
30 nm thermal oxidation is performed and _two SiO layers are sandwiched between the two. In this way, the SiO ₂ film on the first layer of polycrystalline Si8 is exposed while the second layer of polycrystalline Si is etched over the entire surface, and plasma etching of polycrystalline Si is generally
Since the etching speed of polycrystalline Si is more than 10 times higher than that of SiO ₂ , even if some overetching is performed, the polycrystalline Si 8 in the first layer is protected by SiO ₂ and will not be etched. Thereafter, a plate 8 is formed by a photoetching method, and as shown in FIG. 11, this is oxidized to obtain a first interlayer oxide film 13 having a thickness of 100 to 400 nm.
At this time, the Si ₃ N ₄ film 19 is hardly oxidized. Thereafter, using the first interlayer oxide film 13 as a mask, the Si ₃ N ₄ film 19 and the SiO ₂ film 18 are removed by etching.
A gate oxide film 12 with a thickness of 10 to 50 nm is obtained by oxidation in dry oxygen at 1150° C. and 1 to 5% HCl. After that, as shown in Fig. 12, a single layer of polycrystalline Si, silicide (Mo ₂ Si, Ta ₂ O ₅ ), etc. or a layered film of these, or a layer of W or
A gate (word line 4) made of refractory metal such as Mo is selectively deposited. Then, as shown in Figure 13, A _S and phosphorus were added to the
When ion implantation is accelerated to ~120 KeV, n ⁺
A source/drain layer 15 is formed. Further, a second interlayer insulating film 14 typified by a CVDSiO ₂ film containing 4 to 10 mol % of phosphorus is deposited to a thickness of 300 to 1000 nm, and densified by heat treatment at 900 to 1000°C. Thereafter, electrode connection holes 9 are formed that reach the n ⁺ layer 15 of the substrate, the gate 4, and the plate 8, and electrodes 30, typically made of Al, are selectively deposited (only the bit line 3 is shown in the figure). With this, the etched groove 17
A one-transistor type dynamic memory cell can be constructed in which the sidewall of the capacitor is a part of the capacitor. FIG. 14 shows a plan view of this memory cell. If the bottom surface of the etched groove 17 is the same as the top surface, the capacitor area seen from the top surface will not change, so if the peripheral length of the etched groove 17 is L _M and the depth is D _M , then the etched groove is added. As a result, the area increases by L _M ×D _M. The planar area of capacitor region 16 is
If a groove 17 of 3 μm is formed, the plane area is
9μm ² , and the side wall of the etched groove is 1×4×2=
It becomes ^8μm2 . That is, by adding an etched groove 17 of 1 μm and 2 μm deep, the capacitor area is approximately doubled from 9 μm ² to 17 μm ² (=9+8). This approximately doubles the S/N ratio of the signal input to the sense amplifier 5, which has an extremely significant effect in terms of stable operation of the memory. In the explanation of FIG. 14, the grooves 17 are square, but FIGS. 15 and 16 show another application example of the present invention in which a plurality of grooves 17 are provided. FIG. 15 shows a case in which the edge of the groove 17 is located at a constant distance ΔL from the edge of the capacitor region 16, and is composed of one groove 17. If the area of the capacitor is L×L, the peripheral length L _M of the etched groove 17 is 4(L−2ΔL). FIG. 16 shows another application example of the present invention,
Four square grooves were formed as shown. If the distance between the etched grooves 17 is S _M , the peripheral length of the four etched grooves is 8 (L-2ΔL-S _M ). In order to intuitively understand these magnitude relationships, L=
If 5μmΔL=S _M =1μm, the peripheral length A ₁ of the groove in the case of one groove in Fig. 15 is A ₁ = 12 μm, and the peripheral length A ₄ in the case of four grooves in Fig. 16 is A ₄ = 16 μm. . Therefore, multiple grooves are generally more advantageous than one groove, and they reduce the minimum size that can be processed using lithography.
If L _nio , the width of the etched groove L _M and the interval S _M
Most advantageously, L _M =S _M =L _nio . L _M and
If one of S _M is larger than the other, then
The smaller of either can be set as L _nio . FIG. 17 shows another example of application of the present invention. The key point of this application example is that a depression is introduced in the case shown in FIG. 15, with L _M constant, and the area increases by the amount of the side wall that goes inside. FIG. 18 shows another example of application of the present invention. This application example is a case where there is a planar capacitor part 162 surrounded by a groove 17 with a width L _M , and with this, the side wall of the columnar part formed therein is newly added to the capacitor part 162 in the case shown in FIG. The area can be increased. The common feature of the application examples shown in FIGS. 17 and 18 is that the bending angle of the inner wall along the inner wall of the etched groove 17 is 180 degrees.
This means that there is a portion (the portion indicated by θ _L in FIGS. 17 and 18) that exceeds the limit. The edges of these patterns processed by lithography are rarely formed with absolute straight lines;
Generally, it has a curvature of radius r, but even in this case it can be defined by having an angle exceeding 180 degrees. In other words, it can be defined by the presence of a convex portion on the inner wall of the groove 17. FIG. 19 shows another example of application of the present invention, in which there are a plurality of columnar parts 163 and 164,
This also allows a large capacitor area to be obtained with the same area. The application example of the present invention has been described above using one unit of memory cell, but in actual memory, a plurality of these cells form an array, and as mentioned above, interference between mutual cells becomes a problem. . This explanatory diagram is shown in FIGS. 20 to 22. Second
As shown in FIG. 0, four grooves 171 to 174 are arranged alternately. In this case, mutual interference can be roughly divided into between grooves (AA cross section) and between grooves and diffusion layer (BB cross section).
There is a cross section). FIG. 21 is a diagram illustrating the interference between grooves 171 and 172. Grooves 171 and 172 face each other with field oxide film 11 in between, and depletion layers 201 and 202 surround each other. It is formed. According to the depletion layer approximation method, which is simplified as long as it does not impair the essence of physics, the gate insulating film 12 and Si
If there is no carrier 21 at the interface of the substrate 10,
The thickness of the depletion layer is

It is given by [Formula]. Here, ε _S , φ _F , q, and Na are respectively Si substrate 1
Dielectric constant of 0, Fermi level and elementary charge amount (=
1.6×10 ^-19 C), and the impurity concentration of the Si substrate. Since the gate insulating film 12 is usually sufficiently thinner than the thickness of the depletion layer, V _C can be regarded as the applied voltage V _a , so the depletion layer grows to the 1/2 power of the applied voltage. Also, the thickness of the depletion layer when there is enough carrier at the interface to reach an equilibrium state.

[Formula] becomes. As shown in FIG. 21, when depletion layers extend from both sides, the exchange of current (carrier movement) between them increases exponentially. For example, from the specifications of a normal memory cell, N _A =1×10 ¹⁵ /cm ³
If V _C = 5V, Xd _nax 2.5μm, Xd _nio = 0.8μ
m. Therefore, if the shortest distance between the grooves 171 and 172 is S _nio , S _nio approaches the sum of Xd _nax and Xd _nio , that is, 3.3 μm (=2.5 + 0.8),
As it becomes smaller, the carrier stored in one groove wall will flow to the other groove, and the stored information will be lost. When the carrier moves to the side where there is no carrier, the depletion layer shrinks by that amount, and on the side where the carrier is lost, the depletion layer grows, so that antagonism is maintained. Note that at this time, the depletion layer extends more inside the semiconductor substrate than near the surface of the semiconductor substrate. This is because, in general, a high concentration channel stopper of the same conductivity type as the substrate 10 is formed directly below the field oxide film 11. This means that the leakage current between the memory cell capacitances flows not near the surface of the semiconductor substrate, but inside the semiconductor substrate at a portion where the depletion layers of adjacent groove capacitors overlap each other. This causes a problem in that memory information interference occurs between adjacent memory cell capacitors. Since the information in dynamic RAM is volatile,
Normally, it is rewritten every 20ms (also called refresh), so it is only necessary to maintain a sufficient reproducible signal amount during this time.As explained above, the judgment criterion is simply whether or not the depletion layer contacts. I can't. However, setting S _nio > Xd _nax + Xd _nio is an effective means for retaining information. When there is no carrier in the two adjacent grooves 171 and 172, both have the maximum depletion layer width.
Xd _nax , but even if they come into contact, the information will not be destroyed because there is no carrier. Further, as shown in FIG. 22, not only interference between grooves but also interference between the grooves 173 and the diffusion layer 151 is assumed. This case is also basically the same as the groove-to-groove interference. Since it is necessary to increase the integration density of memory cells, especially when shortening the distance between grooves, as can be inferred from the equation for Xd _nax mentioned above, the substrate concentration
Just increase N _A. The simplest method is to increase the concentration of the entire Si substrate 10, but in this case, it will affect peripheral circuits other than memory cells, so as shown in FIG. Before forming the groove, a means for preventing depletion layer extension, that is, a well 22 having the same conductivity type as the substrate may be formed in the groove portion. A p-type impurity such as B may be added to a density of 1×10 ¹² to 1×10 ¹⁴ cm ⁻² by ion implantation, and then diffused to a predetermined depth by heat treatment at 1000 to 12000° C. Although FIG. 23 shows a case in which one well 22 is formed for one trench, the same effect can be expected even if one well is formed in the entire memory array including a plurality of memory cells. In this case, the concentration of the switch transistor 2 will also be high, so if you want to avoid this as well, as shown in FIG. 24, the groove 17 shown in FIG.
After forming the Si substrate, a depletion layer extension prevention means, that is, a high concentration layer 23 having the same conductivity type as the substrate, may be formed only on the surface layer by a thermal diffusion method or the like from the Si surface. Since ion implantation is linear, in order to add impurities to the side walls of the groove 17, ions must be implanted from an oblique direction, or at an accelerating voltage of 10 KeV or less.
It is also possible to actively deposit impurities on the side walls by actively utilizing sputtering using implanted ions. All of the embodiments of the present invention described above are
The inversion layer of the MOS capacitor is the capacitor 1 of the memory cell.
It was used as Further, another embodiment of the present invention using a capacitor between the n ⁺ layer and the plate 8 is formed by selectively forming the same diffusion layer 15 in the capacitor region 16 by photoetching or the like after forming the 25th layer.
n ⁺ conductivity type region, i.e. capacitor electrode layer 2
form 4. Directional ion implantation can be used to add impurities to the trench sidewalls using A _S
or P diagonally, or 10KeV
Next, the acceleration energy is lowered, and A _S and P are added to the sidewalls by actively using ion sputtering. Or commonly used
It is also possible to diffuse AS and _P using a thermal diffusion method using POCl ₃ or selectively depositing CVD glass containing _AS and P. Further, although the field portion of the present invention is formed of the oxide film 11, the present invention may also use an isolation groove 25 dug into the substrate as shown in FIG. 26 as an isolation portion between memory cells. can. It uses the well-known CF ₄ and SF ₆ on the Si substrate.
Dry etching with gas as the main component, 1~
A trench with a depth of 5 μm is dug and filled with a film 26 of SiO ₂ film or polycrystalline Si to provide isolation. When the filling film 26 is made of conductive material such as polycrystalline Si with impurities added, an isolation insulating film 27 typified by SiO ₂ or Si ₃ N ₄ is coated in advance as shown in FIG. After this, the filling film 26 may be embedded. Polycrystalline Si deposited using the CVD method wraps around even narrow grooves well, and even a groove with a width of 1 μm and a depth of 5 μm can be filled with 0.5 μm thick CVD polycrystalline Si. FIG. 28 shows another embodiment of the invention. This is an example in which, in place of the field oxide film 11 of the example shown in FIG. 21, which has already been explained, the isolation by the groove shown in FIG. 27 is also provided as a depletion layer extension prevention means. At the time of forming the isolation shown in FIG. 6, the isolation groove 25 is formed in the Si substrate 10, and the isolation insulating film 27, which is an overlapping film with SiO ₂ or Si ₃ N ₄ , is formed to a thickness of 10 to 200 nm.
It is deposited thickly and filled with a filling film 26 of polycrystalline Si.
Either during or after the deposition of the film 26, phosphorus and A _S
is added to obtain conductivity. Even if this filling film 26 is kept at the ground potential or at the same potential as the power supply voltage V _CC , if a region with a high impurity concentration of the same conductivity type as the substrate is formed sufficiently below the trench 25, this trench can be formed. Depletion layers 20-1 and 20-2 extending from both sides can be separated. In addition, the grooves 171 and 172
It is possible to shorten the distance between the two, contributing to higher memory density. Although FIG. 28 shows an example using an inversion layer, it is clear that the capacitor electrode shown in FIG. 25 can be formed in exactly the same manner. The embodiments of the present invention have been described using an example of an n-channel type, but to make a p-channel type, all conductivity types may be reversed. Further, in the description of the embodiments of the present invention, a folded bit line configuration is used, but it is clear that the present invention can be similarly applied to an open bit line configuration. Furthermore, in the embodiment of the present invention, SiO ₂ and Si ₃ N ₄ are used in the capacitor insulating film.
An insulating film having a one-layer to three-layer structure can also be used by using one or both of the above. Although the present invention has been illustrated by detailed examples above,
If a groove-type capacitor is used, for example, a groove 17 of 2 μm square and 4 μm deep is formed in a 3 μm square capacitor region 16.
, the capacitor area is 9μm ² without this groove, but with the groove it is 41μm ²
(=3×3+2×4×4), which is an improvement of more than 5 times. According to the present invention, such trench type capacitor memory cells can be arranged even closer together.

[Brief explanation of drawings]

FIGS. 1, 2, 3, 4, and 5 are diagrams explaining conventional memory cells, and FIGS.
14 to 20 are plan views showing examples of application of the semiconductor memory to the present invention, and FIGS.
FIG. 2 is a cross-sectional view showing the mutual relationship between memory cells of a semiconductor memory according to an example of application to the present invention, and FIGS. 23 to 28 are cross-sectional views showing embodiments of the semiconductor memory according to the present invention. 1... Capacitor, 2... MOS transistor for switch, 3... Bit line, 4, 41-44...
...word line (a part of which becomes the gate electrode), 5
...Sense amplifier, 6...Parasitic capacitance, 7, 71~7
3... Active region (area surrounded by field oxide film), 8... Plate, 9... Contact hole (contact hole for bit line), 10... Si substrate, 11
...Field oxide film, 12...Gate oxide film,
13...First interlayer oxide film, 14...Second interlayer oxide film, 15,151,152...Diffusion layer, 16...
Capacitor region, 17,171-174...groove,
18... Capacitor SiO ₂ film, 19... Capacitor Si ₃ N ₄ film, 20,201-204... Depletion layer,
21...Carrier, 22...Well, 23...High concentration layer, 24...Capacitor electrode layer, 25...Isolation groove, 26...Isolation filling film, 27...Isolation insulating film.

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit lines provided to intersect with the word lines, and a plurality of memory cells provided at desired intersections of the word lines and the bit lines; In a large-scale semiconductor memory having a circuit for amplifying information read out to the bit line, each of the memory cells has a capacity for storing information and a switch transistor for controlling reading and writing of information to the capacity. The capacitor includes a groove provided in a first region of the main surface of the semiconductor substrate, a capacitive insulating film provided on the semiconductor surface of the groove, and an electrode provided on the capacitive insulating film. and the depth of the groove is 0.5W _M or more, where the width of the groove is W _M , and the first electrode of the switch transistor is electrically connected to the word line, and the first electrode of the switch transistor is electrically connected to the word line. a second electrode is electrically connected to the bit line; a third electrode of the switch transistor is electrically connected to the semiconductor surface of the groove; A large-scale semiconductor memory, further comprising means for reducing leakage current between the capacitances of the two memory cells within the semiconductor substrate. 2. The means for reducing the leakage current is an impurity region formed outside the capacitor insulating film,
2. The large-scale semiconductor memory according to claim 1, wherein the impurity region has the same conductivity type as the first region and has a higher impurity concentration than the first region. 3. The large-scale semiconductor memory according to claim 1 or 2, wherein the bit line is provided on the word line with an insulating film interposed therebetween. 4. Claims 1 to 4, characterized in that the first electrode is made of polycrystalline Si and silicide, and the capacitive insulating film is made of a three-layer film of SiO ₂ , Si ₃ N ₄ , and SiO ₂ The large-scale semiconductor memory described in item 3. 5 The SiO ₂ film on the upper layer of the capacitive insulating film is the Si ₃ N ₄
5. The large-scale semiconductor memory according to claim 4, wherein the large-scale semiconductor memory is provided by oxidizing the semiconductor memory. 6 A plurality of word lines, a plurality of bit lines provided to intersect with the word lines, a plurality of memory cells provided at desired intersections of the word lines and the bit lines, and a plurality of memory cells provided for reading to the bit lines. In a large-scale semiconductor memory having a circuit for amplifying stored information, the memory cell has a capacitor for storing information and a switch transistor for controlling reading and writing of information to the capacitor, and the capacitor is a semiconductor memory cell. a groove provided in a first region of the main surface of the base, a capacitive insulating film provided on the semiconductor surface of the groove, and an electrode provided on the capacitive insulating film; The width is 0.5 W _M or more, where W _M is the width of the groove, the electrode contains at least polycrystalline Si, the first electrode of the switch transistor is electrically connected to the word line, and the switch transistor is electrically connected to the word line. A second electrode of the transistor is electrically connected to the bit line, a third electrode of the switch transistor is electrically connected to the semiconductor surface of the groove, and the first electrode is made of polycrystalline Si, silicide. , consisting of a single layer or a layered film selected from refractory metals, and between two adjacent memory cells of the plurality of memory cells, the groove is formed with the capacitance of the two memory cells. A large-scale semiconductor memory characterized by having deep grooves. 7. The large-scale semiconductor memory according to claim 6, wherein the capacitance groove of the semiconductor is filled with polycrystalline Si. 8. The large-scale semiconductor memory according to claim 6 or 7, wherein the bit line is provided on the word line with an insulating film interposed therebetween. 9. Claims 6 to 9, characterized in that the first electrode is made of polycrystalline Si and silicide, and the capacitive insulating film is made of a three-layer film of SiO ₂ , Si ₃ N ₄ , and SiO ₂ The large-scale semiconductor memory according to item 8. 10 The SiO ₂ film above the capacitive insulating film is as described above.
The large-scale semiconductor memory according to claim 9, characterized in that it is provided by oxidizing a Si ₃ N ₄ film. 11. The large-scale semiconductor memory according to claim 7, wherein the polycrystalline Si has conductivity and is maintained at a constant potential.