JPS62120072A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To process against a leakage current at low temperature by using a dielectric film having specific dielectric constant larger than a silicon nitride as the insulating film of a capacitor, and operating it in the state cooled colder than an ambient temperature in DRAM using a charge storage capacitor as a memory cell to increase a storage capacitance. CONSTITUTION:Capacitor electrodes 20 are contacted at the center with a diffused region 14b, risen at one side on a gate electrode 16a, at the other side on a word line 16b, and a dielectric film 22 and capacitor electrodes 24 are formed in the same shape as the electrodes 20 (stacked capacitor type). Since Ta2O5 capacitor is formed in the step after forming an MOS transistor, it is less exposed within high temperature atmosphere. Since Ta2O5 film varies in its crystal structure in atmosphere of 600 deg.C or higher, it can prevent a leakage current from abruptly increasing. PMOS is used for a transfer transistor of the memory cell to prevent a hot electron effect from occurring at low temperature. The memory cell employs a CMOS structure in n-well to prevent minority carrier from implanting to the capacitor due to alpha-ray emission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device using a charge storage capacitor as a memory cell.

[Conventional technology]

Dynamic random access memory (DRAM)
The memory cell is of the so-called one-transistor, one-capacitor type, and stores data 1.0 depending on the presence or absence of charge stored in the capacitor, and connects and disconnects the capacitor with the bit line by means of the transistor, which is turned on and off based on the word line potential.

DRAMs are also becoming increasingly highly integrated and have large capacities, and high integration is achieved by making memory cells smaller, which also leads to smaller storage capacitors. In order for the sense amplifier to amplify the output voltage of the memory cell without malfunction, the capacitance of this storage capacitor needs to be within about 15:1 from the ratio of the bit line parasitic capacitance to the storage capacitor capacitance. Approximately 30 fF or more was required regardless of the voltage. In addition, regarding soft errors caused by alpha ray irradiation, in order to not be affected greatly by this, the number of bits per bit is small (2000
A charge of fC or more is required, and when the power supply voltage is 5V, a capacitance of at least 40 fF or more is required.

Even if the cell structure is improved to make it more resistant to α-ray irradiation (
For example, form a cell in a well of 0MO3) 20
If a capacitance of fF or more is not secured, the sense amplifier is likely to malfunction. For this reason, as capacitors have become smaller, their dielectric films have become thinner, thereby achieving desired capacitance. For example, in a 64K DRAM, SiO2 is used and the thickness is 40K.
IM
Now, the number has decreased to about 100 people. When the degree of integration is further improved to 16M or 64M, the memory cell area becomes extremely small, making it impossible to secure the above capacity. The reason for this is that the thickness of the insulating film cannot be made so thin as to cause a sudden increase in leakage current due to tunnel current. There is a way to increase the electrode area by making the capacitor structure of a memory cell into a groove structure like a trench capacitor, but when comparing the opening of the trench with the depth of the groove, the latter is extremely large, so deep grooves cannot be practically used. . This is because capacitors using deep, full surfaces cannot increase the degree of integration due to punch-through between capacitors, the electric field tends to concentrate and the dielectric strength is low, the process of forming the grooves is difficult, and the shape tends to vary. This is due to poor process stability.

[Problem that the invention seeks to solve]

On the other hand, there is also an idea of using a high dielectric constant film as a method other than this. Ta 205 has a dielectric constant about 6 times that of commonly used SiO2, and T i O2 has a dielectric constant of more than 25 times, which is effective in increasing the capacitance and preventing the film thickness from decreasing if the capacitance is kept constant. However, materials with high dielectric constants have a relationship with high leakage current, and if the thickness of the insulating film is increased in order to suppress the leakage current to a practically usable level, the amount of accumulated charge will eventually decrease and the high dielectric constant film will no longer have any meaning. Put it away.

FIG. 2 shows the relationship between the dielectric constant and the voltage when the leakage current is 10 A/cd. Leak current 10=A
A value of /- is the limit that can be used as a dielectric film of a storage capacitor in a DRAM, and if there is a larger leakage than this, it becomes unusable.

As you can see from this graph, the voltage x dielectric constant is almost constant, and in reality the performance of all materials is not much different, so SiO2゜S i Na is easy to adapt to the silicon process.
The conclusion is that it is easy to use.

However, as mentioned above, 16M and 64M are required to be thin, which is practically impossible.

However, the relationship shown in Figure 2 is at room temperature and will change if the temperature is changed. The present invention focuses on this point,
The dielectric film of the storage capacitor is made of a material with a high dielectric constant, and leakage current is counteracted by using the capacitor at low temperatures.

[Means for solving problems]

The present invention provides a dynamic semiconductor memory device in which a charge storage capacitor is used as a memory cell, in which a dielectric film having a relative dielectric constant higher than that of silicon nitride is used as an insulating film of the capacitor, and the device is operated in a state cooled from room temperature. This is a characteristic feature.

[Effect]

In the present invention, silicon oxide (SiO2) or nitride (S
A film with a high dielectric constant that has a higher leakage current than i3Nm), specifically aluminum oxide A1 whose dielectric constant is more than twice as large.
20z or tantalum oxide Ta205, etc., and is used in a state where leakage current is small by cooling it. These dielectric constants are 12 for Al2O3 and Ta2O! 1, which is considerably larger than about 4 for SiO2.

FIG. 3 shows the leakage current of a Ta205 film with a thickness of 300 at room temperature (300K) and liquid nitrogen temperature (77K).

At room temperature, there is a leakage current of about 10-5 A/cd when the applied voltage is 2.5 cm, which hinders its practical use. However, 7
7 is 1O-9A/cIl! This decreases to below and falls within the practical range as a DRAM capacitor.

Therefore, if Ta205 is used for the dielectric film of the storage capacitor and the DRAM is cooled with liquid nitrogen, it will be sufficiently practical.

Assuming that the miniaturization of memory cells requires 50 people to thicken the SiO2 dielectric film of the storage capacitor, this is quite thin (
, it falls into the range where it is not easy to manufacture. On the other hand, T
If A205 is used, the film thickness only needs to be 300 because the dielectric constant is about 6 times that of SiO2, and it is easy to manufacture. Furthermore, if a dielectric film of 100 people is made of Ta2O5, the equivalent 5tO2 film would be 16 to 17 people, and in this case, a tunnel current flows and it becomes a resistor rather than an insulator. Therefore, it is extremely effective to use a material with a high relative permittivity by cooling it to suppress leakage current.

The only thing that can be reduced by cooling is the leakage current (
hopping current), not tunneling current. Therefore, even when a material with a high dielectric constant is cooled and used, it cannot be made thin enough to allow tunneling current to flow.

It is known that junction leakage is drastically reduced when the temperature is lowered than at room temperature, and therefore cooling tends to be preferable for DRAMs.

On the other hand, it is generally known that the hot electron effect becomes noticeable at low temperatures.

The hot electron effect is when electrons accelerated in a high electric field enter the gate oxide film of a MOS transistor with high energy and remain trapped, which changes the threshold voltage of the MOS FET. .

This hot electron effect is more pronounced in 9MO3 than nMO5.
It is known that this phenomenon is less likely to occur in FETs. This is 9
This is because the junction shape of the source and drain of the MO3FET is relatively smooth, making it difficult for local electric fields to occur. In nMOS FBTs, the shapes of the source and drain junctions are devised to prevent the generation of high electric fields (so-called L
D D (Lightly Doped Drain
) structure is known.

〔Example〕

Figure 1 shows a DRAM dedicated to operation in the liquid nitrogen temperature range using a T a 205 film as a capacitor as an embodiment of the present invention.
Indicates a cell. The cell structure is a so-called stacked capacitor type, in which capacitors are partially stacked on top of the memory cell transistor to increase the capacitor area as much as possible. In this figure, 10 is a p-type silicon substrate, and 12 is a p-type silicon substrate on the substrate. The formed n-type wells, 14a and 14b, are p diffusion layers formed in the n-wells, and 15a and 16b are word lines formed on the substrate with an insulating film interposed therebetween, and also serve as gate electrodes of the transfer gate transistor.14a.

14b and 16a are the source, drain, and gate of the transistor. 16b is a portion between the gates in this cross-sectional view, and becomes the gate of a transistor of another memory cell at a position slightly shifted in the vertical direction of the paper of this figure. The capacitor consists of a tantalum electrode 20 in ohmic contact with the diffusion region (source) 14b, a dielectric film 22 formed by oxidizing the surface of the tantalum electrode 20, and a molybdenum electrode (cell plate) 24 deposited on the surface. 30 is an insulating film between the eyebrows, and 18 is a bit line made of aluminum. A tantalum electrode 26 made at the same time as the capacitor is interposed at the contact portion between the bit line 18 and the diffusion region (drain) 14a. The capacitor electrode 20 is in ohmic contact with the diffusion region 14b at the center as shown, and - for example, with the gate electrode 16a.
The other side rides on the word line 16b, and the dielectric film 22 and the capacitor electrode 24 are connected to the capacitor electrode 2.
0 (stacked capacitor type), but this structure is convenient for 'l'a205 capacitors. This is because this capacitor is manufactured in a process after forming the MOS transistor, so it is rarely exposed to a high-temperature atmosphere. To form a MOS transistor, the gate oxide film fabrication process requires at least 10
00°C is required, and annealing after implanting high-concentration impurity ions into the mace and drain also requires temperatures of 900°C or higher. Therefore, if a transistor is made after forming a capacitor, the capacitor will naturally be exposed to the above-mentioned high temperature. Become.

The crystal structure of Ta20sB'A changes in an atmosphere of 600° C. or higher, and as a result, leakage current increases rapidly, so it is not preferable to expose it to high temperatures.

The transfer transistor of the memory cell has PM as shown in the figure.
O5 is used. This is to prevent hot electron effects at low temperatures. Also, the memory cell is CMOS
The structure is placed in an n-well. This is to prevent minority carriers generated by α-ray irradiation from being injected into the capacitor portion.

A method for manufacturing this memory cell will be described below. p by a known method
An n-type well 12 is formed in a type wafer 10, and p-channel type MO3) transistors 14a and 14b are formed.

16a etc. are formed. Next, an insulating film is formed around the gate electrode, and capacitor electrodes 20 are formed on the source and drain electrodes 14b of the MO5I transistor. The electrode material is tantalum (T a ). This may be deposited by sputtering, but CVD is preferred because it provides good coverage of the stepped portion (so-called MOCVD is used). Next, the tantalum film is applied to the capacitor part 20 and the bit line contact part 26.
The tantalum film is patterned in the shape of , and the tantalum film other than those in the memory cell portions is removed. Next, the surface of the tantalum film is oxidized to a thickness of 300 mm by anodic oxidation in oxygen gas plasma to form a film 22. Since tantalum is removed from the peripheral circuit portion during anodization of the tantalum film, the surfaces of the n+ or p+ source and drain regions of the MOS transistor are also slightly anodized. However - the 5i thus formed in the role
Since Oz has a lower conductivity than Ta205, the tantalum film portion is selectively oxidized, and the oxide film on the source and drain is a few tens to hundreds of oxides that can be easily removed in a later process.
Only people grow. During this anodic oxidation, the wafer is placed on the lower electrode of a pair of parallel electrodes in the chamber, and current is applied to the tantalum film through the substrate 10, the n-well 12, and the diffusion region 14b.
This will be done using the following route.

Tantalum can be oxidized by thermal oxidation, but when anodic oxidation is used, the film thickness is uniquely determined by the formation voltage, so the uniformity and reproducibility of the film thickness is good, and there is no breakdown voltage deterioration due to pinholes etc. Few. This is because if there is a pinhole, the conductivity is high, so more current flows and anodic oxidation progresses.
This results in a uniform insulating film thickness over the entire surface.

Next, the counter electrode plate 24 of the capacitor is formed.

This was a molybdenum film formed by MOCVD.

A SiO2 film is deposited on the transistor and capacitor parts formed in this manner (the plasma CVD method can deposit an insulating film at low temperatures), a contact hole for a bit line is made in this, and an aluminum layer is deposited using a known method. The bit lines 18 are wired according to the method. Aluminum wiring layer 1
Although the upper part of 8 is not shown, it is 5iz according to the plasma CVD method.
Cover with N4 film to protect the chip. In addition, although the power supply voltage is 5■, 2.5V is supplied to the cell plate so that the absolute value of the voltage applied to the capacitor film is 2.5V to further suppress leakage current and reduce the probability of dielectric breakdown occurring. lower.

〔Effect of the invention〕

As explained above, in the present invention, a dielectric film with a high dielectric constant is used for the capacitor of a DRAM memory cell, and although this has a leakage current at room temperature, this can be effectively reduced by cooling it to around the temperature of liquid nitrogen. Lower it to a value that causes no problems. This will result in 100 to 300 people
203. Ta20s.

A high dielectric constant film such as TiOz can be used, and a capacitor that is extremely small, has sufficient capacitance, and has a film thickness that is practical can be realized. Taking 'l'a20a as an example, the dielectric constant is approximately 2
5, and 200 people's Ta20a corresponds to 30 people's 5i02. An insulating film with a thickness of 30 mm cannot be manufactured reliably, and tunnel current flows significantly, so that it does not function as a memory capacitor. However, if the thickness is 200 mm, a 20 a film can be manufactured.

In the memory cell of this embodiment, the capacitor area is about 50% of the cell area, so in a 16M DRAM with an area of 3.5 μm 2 per bit, a storage capacity of 20 fF can be obtained by using 200 Ta2C)+ films. Although this value cannot be said to be sufficient as a storage capacity according to current understanding, it is necessary to perform ECC (Error Checking and
By installing a correcting circuit, the soft error rate can be made sufficiently low. On the other hand, if we use a 5to2 film made of about 70 people without using such a high dielectric constant film, we can only obtain a storage capacity of 7.4 fF, and the cell signal sense will be lost before the soft error rate can be reduced to 1141i)i. This will make it difficult to achieve 16M.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing an embodiment of the present invention, Figure 2 is a characteristic diagram showing the relationship between dielectric constant and leakage current, and Figure 3 is a graph showing the relationship between applied voltage and leakage current with temperature as a parameter. FIG. In the drawing, 20.22.24 are memory cell capacitors, 1
4a, 14b, and 16a are transistors for the same transfer gate.

Claims (1)

[Claims] In a dynamic semiconductor memory device in which a charge storage capacitor is used as a memory cell, a dielectric film having a dielectric constant higher than that of silicon nitride is used as an insulating film of the capacitor, and the device is operated in a state cooled from room temperature. A dynamic semiconductor memory device characterized by: