JPH04265085A - Closed caption broadcast receiver - Google Patents

Abstract

PURPOSE:To reduce the number of pins and that of elements for IC by using a taking-in completion signal, which is used at the time of taking caption data into a shift register, as a field discriminating pulse. CONSTITUTION:The output signal of a VCO 118 has the phase locked to that of a horizontal synchronizing signal, and a signal of 2fH is applied to a counter 120 from a frequency divider 119, and a pulse of the timing of caption data extraction is applied to an AND gate 121. The counter 120 is reset in accordance with a vertical synchronizing signal and starts counting. A pulse is generated which is in the high level during the 21st horizontal synchronizing signal period when caption data exists. A latch circuit 111 applies a read clock to a 16-bit shift register 110 by the discrimination output from an O/E discriminating circuit 124 and reads out and latches data. When the output of a delay circuit 127 is applied to a using circuit 112, the circuit 112 directly takes in the Q output of an FF 125 and obtains field discrimination information at its timing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a receiving apparatus for closed caption broadcasting for the deaf that is used in the United States, and particularly to a closed caption broadcast receiving apparatus suitable for use in an IC.

0002

[Prior Art] Closed Caption Broadcasting (CLOSED CA), which displays conversations, announcements, etc. during TV broadcast programs as subtitles on the TV screen for the benefit of deaf people.
PTION) is being conducted in the United States. This is similar to teletext broadcasting in Japan, and data is transmitted superimposed on the vertical retrace period of the video signal. The data is transmitted by a code method, and when characters are to be displayed, a character generator is provided inside the receiver to prepare the characters. This allows the broadcast station to instantly display the information by simply sending a code. There are roughly two types of display modes: text mode (TEXT MODE) and caption mode (CAPTION MODE). In text mode, up to 15 lines x 32 characters can be displayed in the center of the TV screen, and in caption mode, characters can be displayed in the upper and lower parts of the display range, that is, between columns 1 and 4 and between columns 12 and 15. It is possible to display only the interval. Closed caption broadcast data is available at the 21st H of the vertical blanking period (
H is superimposed on the horizontal scanning period), and when that part is enlarged, it becomes as shown in FIG. The 21st composite signal shown in FIG. 2(A) is composed of a 3.58 MHz color burst signal, a 503 KHz run-in clock, and caption data, and the caption data is as shown in FIG. 2(B). It includes a 3-bit start bit, 7-bit data, a parity bit for the data, 7-bit data, and a parity bit for the data. Figure 2 (
8-bit data (1 byte) including the parity bit (b) is used as one unit to transmit the above-mentioned character code as well as commands that determine the position (row and column), color, etc. of the character.

[0003] As a receiver for this closed caption broadcasting, a receiver as shown in FIG. 3 can be considered. A television broadcast signal on which closed caption broadcast data is superimposed is received by the antenna (101) in FIG. 3, tuned by a tuner (102), and then amplified and amplified by an IF (intermediate frequency) amplifier circuit (103). Detected. The detected video signal is processed by a Y/C (luminance/chroma) processing circuit (104), and then R. G. The B primary color signal is the R. G. It is applied to the B switching circuit (105).

[0004] Also, from the video signal from the IF amplifier circuit (103), only caption data is extracted by a sampling circuit (106) and applied to a decoder (107). The decoder (107) performs parity check, display determination, decoding, etc. of caption data. The decoded caption data is applied to a character generator (108) and processed so that a desired character can be displayed at a desired position. Then, according to the process, the R. G. A primary color signal of B is generated, and the output control circuit (10
9) via R. G. The voltage is applied to the B switching circuit (105), and caption characters are displayed on the original television screen.

[0005]

Now, FIG. 4 shows in detail the relationship between the extraction circuit (106) and the decoder (107) of FIG. 3 when they are integrated into an IC. The data shown in FIG. 5(b) is applied from the extraction circuit (106) in FIG. The voltage is applied as shown in . The data taken into the 16-bit shift register (110) is read out and transferred to the latch circuit (111) in response to the arrival of a clock signal from the latch circuit (111). The clock signal is transmitted from the extraction circuit (106) to the latch circuit (111).
This occurs in response to the fall of the transfer end signal in FIG. 5(d) applied to the transfer end signal. The signal shown in FIG. 5(d) is also used for extracting the data shown in FIG. 5(b), and indicates that the data transfer has definitely been completed. Therefore, data can be stably latched into the latch circuit (111). A signal for determining whether the currently received television signal is an even field or an odd field is also applied from the extraction circuit (106) to the decoder (107). In closed caption broadcasting, programs (characters) with different contents are transmitted in even and odd fields, allowing the viewer to select. The decoder (107) is applied with a signal according to the wishes of the viewer, and must always be able to determine which field the sent character data belongs to. The utilized circuit (112) shows such a part.

As described above, it is necessary to transmit a plurality of signals from the extraction circuit (106) to the decoder (107), and the I
When converting to C, problems arise such as an increase in the number of pins and an increase in wiring. Therefore, it has been desired to reduce the number of signal paths for transmission.

[0007]

[Means for Solving the Problems] The present invention has been made in view of the above points, and provides a closed screen that decodes caption data multiplexed on a television signal and displays text information on a television screen. A caption broadcast receiving device comprising: a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal in a television signal; a PLL circuit that locks to the horizontal synchronization signal from the synchronization separation circuit; a counter that is reset in response to a vertical synchronization signal, counts the output signal of the PLL circuit, and generates a caption data transfer completion signal; and a television signal that arrives in response to the vertical synchronization signal from the synchronization separation circuit. a first integrated circuit comprising: a discrimination circuit that discriminates whether the field is an even field or an odd field; and an output circuit that outputs a discrimination output signal of the discrimination circuit in accordance with an output signal of the counter; and a second integrated circuit including a shift register that takes in caption data in response to a clock signal from the PLL circuit.

[0008]

According to the present invention, the caption data transfer completion signal and the field discrimination signal are converted into one signal and applied to the decoder, and the original signal information can be reproduced within the decoder.

[0009]

[Embodiment] Figure 1 is a circuit diagram showing an embodiment of the present invention.
113) is a synchronization separation circuit that separates the horizontal synchronization signal (H) and vertical synchronization signal (V) from the video signal of the IF amplifier circuit (103), and (114) is a synchronization separation circuit that separates the caption data from the video signal of the IF amplifier circuit (103). The comparator (115) for extraction is a phase comparator (116), a low-pass filter (117), a VCO (118) and a frequency divider (11).
9), the PLL circuit (120) is the frequency divider (1
The signal of 2fH (fH is the horizontal synchronization signal frequency) from the synchronization separation circuit (19) is counted as a clock signal, and
A counter (121) is reset according to the vertical synchronization signal from the frequency divider (119) and a gate pulse corresponding to the caption data period according to the divided output of the frequency divider (119) and the output signal of the counter (120). and gate to create, (122) is 32fH from VCO (118)
The first clock signal is applied to the decoder (107).
The switch (123) is a second switch (123) that applies the output signal of the comparator (114) to the decoder (107).
124) is an O/E (odd
/even) discrimination circuit, (125) is a counter (120
) D-FF (D-type flip-flop circuit) that converts the output signal of ) and the O/E discrimination output into one signal, (126)
(127) is a polarity matching circuit that generates pulses of the same polarity in response to the arrival of rising and falling pulses, and (127) is a delay circuit.

In FIG. 1, circuit elements that are the same as those in FIGS. 3 and 4 are designated by the same reference numerals, and explanations thereof will be omitted.

VCO (118) of PLL circuit (115)
The center frequency is set to 32fH. 32f
H is a value for reading caption data, which is finally divided to a frequency fH by a frequency divider (119) and applied to a phase comparator (116). On the other hand, since a horizontal synchronizing signal is applied to the phase comparator (116) from the synchronizing separation circuit (113), the PLL circuit (115) locks to the horizontal synchronizing signal. Therefore, VCO (118
) is locked to the phase of the horizontal synchronization signal shown in FIG. 6(A). The frequency divider (119) outputs 2f to the counter (120) as the first frequency divided output signal φ1.
An H signal is applied, and a pulse at the timing for extracting caption data as shown in FIG. 6(b) is applied as a second frequency-divided output signal φ2 to the AND gate (121). The counter (120) is reset in response to the vertical synchronization signal from the synchronization separation circuit (113) and starts counting. Then, a pulse as shown in FIG. 6(C) that goes to "H" level is generated during the 21H horizontal synchronizing signal period in which caption data exists. In addition, the counter (120) is O/E
The count value is changed by 0.5H in accordance with the output of the discrimination circuit (124). Therefore, a pulse as shown in FIG. 6(d) is generated from the AND gate (121), and only during the "H" level period, the first and second switches (122)
23) Close. Then, from the VCO (118) to the 16-bit shift register (110) in the decoder (107)
The 32fH clock signal is transmitted only during the period when caption data exists, as shown in Figure 6 (
f).

On the other hand, the output data of the comparator (114) is, for example, as shown in FIG.
23) to a 16-bit shift register (110). The output data in FIG. 6(E) is shown in FIG.
(to) is taken into a 16-bit shift register (110) in response to a clock signal. In this way, since the clock signal is applied to the 16-bit shift register (110) only when data exists, data can be stably fetched without being affected by noise or the like.

On the other hand, the O/E discrimination circuit (124) generates the discrimination output shown in FIG. 7(c). Figure 7 (a) shows the timing of the television signal, and Figure 7 (b) shows the timing of the television signal in Figure 6 (
c) shows the pulse. In response to the fall of the signal in FIG. 7(b), the signal in FIG. 7(c) is
This occurs in the output, as shown in FIG. 7(d). And Figure 7 (
d) signal is sent to the polarity matching circuit (1) in the decoder (107).
A pulse applied to the latch circuit (111) and a delay circuit (127) indicating the same state change is applied to the latch circuit (111) and the delay circuit (127). Then, the latch circuit (111) can apply a read clock signal to the 16-bit shift register (110), read the data, and cause the latch circuit (111) to latch the data. When the signal delayed by the delay circuit (127) is applied to the usage circuit (112), the usage circuit (
112) directly takes in the signal shown in FIG. 7(d), and field discrimination information can be obtained at that timing. In this way, the signal in FIG. 7(d) indicates the completion of data transfer, field determination, and determination timing of the field determination.

Therefore, according to the circuit shown in FIG. 1, signal paths can be shared, and it is possible to reduce the number of pins when integrated into an IC and to reduce the number of signal paths between ICs.

[0015]

As described above, according to the present invention, the capture completion signal when capturing caption data into a shift register can also be used as a pulse for field discrimination. It is possible to reduce the amount of

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a closed caption broadcast receiving apparatus according to the present invention.

FIG. 2 is a waveform diagram for explaining closed caption broadcasting.

FIG. 3 is a block diagram of a conventional closed caption broadcast receiving device.

4 is a circuit diagram showing one embodiment of the decoder (107) of the device of FIG. 3; FIG.

FIG. 5 is a waveform diagram for explaining FIG. 4;

FIG. 6 is a waveform diagram for explaining FIG. 1;

FIG. 7 is a waveform diagram for explaining FIG. 1;

[Explanation of symbols]

(110) 16-bit shift register (111)
Latch circuit (113) Synchronous separation circuit (114) Comparator (115) PLL circuit (120) Counter (121) AND gate (122) First switch (123) Second switch

Claims (3)

[Claims] 1. A closed caption broadcast receiving device that decodes caption data multiplexed on a television signal and displays character information on a television screen, the device comprising: A synchronous separation circuit that separates synchronous signals, a PLL circuit that locks to the horizontal synchronous signal from the synchronous separation circuit, and a PLL circuit that is reset in response to the vertical synchronous signal from the synchronous separation circuit and counts the output signal of the PLL circuit. , a counter that generates a caption data transfer completion signal, and a determination circuit that determines whether the incoming television signal is an even field or an odd field in accordance with the vertical synchronization signal from the synchronization separation circuit; a first integrated circuit comprising an output circuit that outputs a discrimination output signal of the discrimination circuit in response to an output signal of the counter; and a shift register that captures caption data in response to a clock signal from the PLL circuit. a second integrated circuit comprising: an output signal of the output circuit of the first integrated circuit;
A closed caption broadcast receiving device characterized in that the closed caption broadcast receiving device is used as a capture completion signal for the shift register of the second integrated circuit. 2. Closed caption broadcasting according to claim 1, wherein the output circuit is a D-type flip-flop in which the output of the discrimination circuit is applied to a data terminal and the output of the counter is applied to a clock terminal. Receiving device. 3. The closed caption broadcast receiving apparatus according to claim 1, wherein the second integrated circuit includes a utilization circuit that utilizes a determination as to whether the field is an even field or an odd field.