JP2540328Y2 - Closed caption broadcast receiver - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a closed caption broadcast receiving apparatus for the deaf in the United States, and in particular, a general-purpose 8-bit microcomputer can be used as decoding means. The present invention relates to a closed caption broadcast receiving device.

[0002]

2. Description of the Related Art Closed caption broadcasting (CLOSED CAP) for displaying conversations, announcements, and the like in a television broadcast program as captions for a deaf person on a television screen.
TION) is taking place in the United States. This is similar to teletext broadcasting in Japan, in which data is transmitted by being superimposed on a vertical retrace period of a video signal. The transmission of the data is a code system, and when displaying characters, a character generator (character generator) is prepared inside the receiver to prepare characters. As a result, it is possible to instantaneously display the code only by sending a code (code) from the broadcast station. The display mode is roughly classified into two types, a text mode (TEXT MODE) and a caption mode (CAPTION MODE). In the text mode, a maximum of 15 lines × 32 characters can be displayed at the center of the television screen, and in the caption mode, the upper and lower sides of the display range, that is, between 1 to 4 columns and 12 to 1 column.
Display is possible only for five columns. The data of the closed caption broadcast is superimposed on the 21st H (H is the horizontal scanning period) of the vertical blanking period, and the enlarged portion is as shown in FIG. The 21H composite signal shown in FIG. 2A is a 3.58 MHz color burst signal and a 5
2 and a run-in clock of 03 KHz and caption data.
As shown in (b), a 3-bit start bit, 7-bit data, a parity bit of the data, a 7-bit data,
And a parity bit of the data. Fig. 2 (b)
8-bit data including 1 parity bit (1 byte)
Is transmitted as a unit, and in addition to the above-described character code, a command (command) for determining the position (row and column) and color of the character is transmitted.

[0003] As a receiver of this closed caption broadcast, one as shown in FIG. 3 is conceivable. The television broadcast signal on which the data of the closed caption broadcast is superimposed is received by the antenna (101) of FIG. 3, is tuned by the tuner (102), and is then amplified by the IF (intermediate frequency) amplifier circuit (103). It is detected. The detected video signal is processed by a Y / C (luminance / chroma) processing circuit (104). G. FIG. B primary color signal is R.B. G. FIG. Applied to the B switching circuit (105).

[0004] Also, from the video signal from the IF amplifier circuit (103), only the caption data is extracted by the extraction circuit (106), and the data and clock are converted to a decoder (10).
7) is applied. The decoder (107) performs parity check, display determination, decoding, and the like of caption data. The decoded caption data is applied to a character generator (108) and processed so that a desired character can be displayed at a desired position. And according to the process,
From the character generator (108) G. FIG. A primary color signal of R.B is generated, and R.B. G. FIG. The signal is applied to the B switching circuit (105), and the caption characters are displayed on the original television screen.

When the decoder (107) performs a process such as decoding, it is necessary to read out caption data at a speed suitable for the process. Therefore, means for temporarily storing caption data is required, and a 16-bit shift register (1) is provided in the decoder (107).
10) is built in.

[0006]

The decoder (107) shown in FIG. 3 is preferably constituted by a microcomputer because of the complexity of processing. Therefore, a microcomputer (microcomputer) having a 16-bit shift register is required as the decoder (107).
Such a microcomputer is not common, and a dedicated microcomputer must be developed, which is expensive. Therefore, it has been demanded that a general-purpose microcomputer having a common 8-bit shift register can be used for the decoder.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the feature of the present invention is to decode caption data multiplexed on a television signal, and to perform character decoding. A closed caption broadcast receiving apparatus for displaying information on a television screen, comprising: a sampling signal generating circuit for generating a sampling signal for extracting caption data from a television signal; and a second signal generating a clock signal for caption data. A first clock signal source, a slice circuit for extracting caption data according to the sampling signal, and a signal from the first clock signal source only during a period in which caption data is extracted from the slice circuit at least according to the sampling signal. An integrated circuit having a clock output circuit for outputting a clock signal; An 8-bit first shift register that captures caption data from a clock circuit according to a clock signal from the clock output circuit, and to which caption data from the first shift register and a clock signal from the clock output circuit are applied. An 8-bit second shift register, a second clock signal source for generating a clock signal for caption data, and at least the contents of the first shift register after the clock output circuit stops outputting in response to the sampling signal And a clock control means for applying a clock signal from the second clock signal source to the first and second shift registers only during a period necessary to transfer the clock signal to the second shift register. It is a point.

[0008]

According to the present invention, since an 8-bit shift register for temporarily storing 16-bit caption data is arranged at the subsequent stage of the integrated circuit for extracting data, an 8-bit shift register is provided as decoding means. A general-purpose microcomputer can be used.

[0009]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(1) a separation circuit (2) for separating the horizontal and vertical synchronization signals from the television signal from the IF amplification circuit (103)
A PLL circuit (3) for locking to the horizontal synchronization signal from the separation circuit (2), and counting the output of the PLL circuit (3) as a clock, resetting the signal in accordance with the vertical synchronization signal, and extracting the caption data. , A slicing circuit (5) for slicing and extracting caption data in accordance with the output signal of the counter (4), and a slicing circuit in accordance with the output signal of the counter (4).
A first signal for applying a clock signal for caption data from the LL circuit (3) to the gate of the first transistor (6)
An integrated circuit comprising a switch (7), and (8) an 8-bit first shift register for receiving caption data from a pin (9) of the integrated circuit (1) in response to a clock signal from a pin (10). , (11) are a falling edge detection circuit (12), a delay circuit (13), and a waveform shaping circuit (14)
And a clock control means ( 16 ) comprising a second switch (15), a clock signal source (17), an 8-bit second shift register (18), and a decoding circuit (19).
And a microcomputer formed as a general-purpose IC having a second transistor (20).

The video signal from the IF amplification circuit (103) is applied to a separation circuit (2), where a horizontal synchronization signal H and a vertical synchronization signal V are separated and applied to a PLL circuit (3) and a counter (4). At the same time, the video signal is applied to the slice circuit (5). The PLL circuit (3) locks on the horizontal synchronizing signal, and a signal of a frequency f _H (horizontal synchronizing signal frequency) is applied to the counter (4) as a clock signal. Further, the counter (4) is reset by the vertical synchronizing signal, generates a gate pulse as shown in FIG. 4B for extracting the caption data of the 21H, and applies it to the slice circuit (5). The slicing circuit (5) slices and extracts the caption data of the 21H in the video signal based on a 503 KHz run-in clock.

On the other hand, the gate pulse shown in FIG.
The signal is applied to the switch (7), and is switched to the "H" level period a side. Therefore, from the PLL circuit (3) to FIG.
Is generated and applied to the gate of the first transistor (6). At this time, the microcomputer (1
Since the second switch (15) in 1) is on the b side, the second transistor (20) is off. Therefore, the clock signal from the source of the first transistor (6), that is, the pin (10) is applied to the first and second shift registers (8) and (18). In the period A of FIG. 4D, the data shown in FIG. 4A is applied to the first shift register (8). At this time, the clock shown in FIG. 4D is applied to the second shift register (18) in the microcomputer (11), but the data has not yet arrived and the operation is not performed. Then, in the period B of FIG. 4 (d), the data shown in FIG. 4 (a) starts to be applied to the first shift register (8),
The data stored until then is applied to the second shift register (18). As a result, the data
Data is stored in the shift register (18) in the first shift register (8). Then, the microcomputer (11) reads out the data in the second shift register (18) at its own optimum speed and performs processing such as decoding.

When the processing based on the data is completed, it is necessary to perform the processing based on the data next. In this case, the clock signal is generated from the source of the second transistor (20) in the microcomputer (11). . The generation of the clock signal is determined according to the fall of the signal in FIG. The signal shown in FIG.
The falling edge is detected by a falling edge detection circuit (12), and the detection output is delayed by a delay circuit (13). This delay time is determined according to the above-described processing time of the data, and is set to, for example, about 1H as shown in FIG. The delayed signal is subjected to waveform shaping by a waveform shaping circuit (14) composed of, for example, a monomultivibrator, and the pulse width of the signal passes through eight clocks.
(C) Only during the “H” level period of the signal in FIG. 4C, the second switch (15) is switched to the “a” side, and the clock signal from the clock signal source (17) in the period C in FIG. 20) and applied to the first and second shift registers (8) and (18). At this time, the first switch (7) is switched to the b side, and the first transistor (6) is off. As a result, the data of the first shift register (8) is transferred to the second shift register (18), and is processed in the same manner as the data.

Therefore, according to the circuit of FIG. 1, a general-purpose microcomputer having an 8-bit shift register can perform processing such as decoding of caption data. Although the embodiment of FIG. 1 has been described for an integrated circuit having an open-drain type output circuit, a case of having a C-MOS type output circuit will be described with reference to FIG.

In FIG. 5, the data of FIG.
When applied to the shift register (8), the first and second
Switches (7) and (15) are switched as shown. Therefore, the output of the second output circuit (21) becomes "H" level, and the AND gate (22) opens. Further, the tri-state gate (23) according to the "H" level
Is in an output enabled state. The third switch (24) is open as shown. Therefore, the PLL
The clock signal from the circuit (3) is supplied to the first output circuit (25)
Via the first and second shift registers (8) and (1).
8). Next, FIG.
The signal of (c) is the second and third switches (15) and (2)
4), and the second switch (15) is connected to the contact a side,
It is assumed that the third switch (24) is closed, contrary to the illustration. Then, the output of the second output circuit (21) becomes "L" level, the AND gate (26) opens, and the tri-state gate (23) enters a floating state. Therefore, the clock from the clock signal source (17) is applied to the first and second shift registers (8) and (18), and the data is applied to the second shift register (18).

[0015]

As described above, according to the present invention, it is possible to decode caption data by using a general-purpose microcomputer having an 8-bit shift register. For that reason,
The receiving device can be easily configured without requiring a dedicated decoding microcomputer.

[Brief description of the drawings]

FIG. 1 is a block diagram of a closed caption broadcast receiving apparatus according to the present invention.

FIG. 2 is a waveform chart for explaining closed caption broadcasting.

FIG. 3 is a block diagram of a conventional closed caption broadcast receiving device.

FIG. 4 is a waveform chart for explaining FIG. 1;

FIG. 5 is a block diagram showing another embodiment of the closed caption broadcast receiving apparatus according to the present invention;

[Explanation of symbols]

(1) Integrated circuit (3) PLL circuit (4) Counter (5) Slice circuit (8) First shift register (11) Microcomputer ( 16 ) Clock control means (17) Clock signal source (18) Second shift register

Claims (2)

(57) [Scope of request for utility model registration] 1. A closed caption broadcast receiving apparatus for decoding caption data multiplexed on a television signal and displaying character information on a television screen, wherein the caption data is extracted from the television signal. A sampling signal generating circuit for generating a signal; a first clock signal source for generating a clock signal for caption data; a slice circuit for extracting caption data in response to the sampling signal;
And the caption data is extracted from the slice circuit.
Clock from the first clock signal source only during the
Wherein the integrated circuit and a clock output circuit for outputting a signal, the caption data from the slice circuit Black
An 8-bit first shift register to be fetched in response to a clock signal from a clock output circuit, and to which caption data from the first shift register and a clock signal from the clock output circuit are applied.
A second shift register for bits, a second clock signal source for generating a clock signal for caption data, and the clock output circuit stopping output in response to the sampling signal
After that, at least the contents of the first shift register
Microcomputer and a clock control means for a clock signal Ru is applied to the first and second shift register from only <br/> the second clock signal source for periods of time necessary to transfer to the second shift register A closed caption broadcast receiving device, comprising: 2. The clock control means includes: an edge detection circuit for detecting an edge of the sampling signal; a delay circuit for delaying a detection output of the edge detection circuit; and a waveform for shaping a waveform of an output signal of the delay circuit. 2. The closed caption broadcast receiving device according to claim 1, further comprising a shaping circuit.