JPH0888840A - Teletext system discrimination device - Google Patents

Abstract

PURPOSE: To discriminate the teletext system of Japan and the closed caption system of USA and to perform a data processing suitable for the respective systems in a common decoder. CONSTITUTION: Since the transmission rate and pattern of character information superimposed on the 21st H of a vertical blanking period are different between the teletext system of Japan and the closed caption system, when the character information is superimposed on the 21st H, a clock frequency is discriminated by a band-pass filter 71 and a level comparison circuit 72 or a clock cycle is discriminated by a timer and an edge pulse detection circuit or an edge pulse counting circuit. By them, based on the transmission rate, which one of the systems is a multiplex system is discriminated. Or by discriminating bit synchronization data by a pattern coincidence detection circuit and discriminating the result of error correction further, which one of the systems is the multiplex system is discriminated based on the pattern of the character information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for discriminating a character multiplex system in television broadcasting or the like.

[0002]

2. Description of the Related Art Conventionally, image information composed of characters and graphics is multiplexed in a digital signal with a television signal and transmitted, and the signal is decoded on the receiving side and displayed on a television receiver. Multiplex broadcasting is known.

In the character multiplex broadcasting in Japan, a hybrid transmission system is adopted in which character information is transmitted by a code transmission system and fine graphic information is transmitted by a pattern transmission system.

On the sending side, a teletext screen is produced by combining an additional sound as needed with a screen made up of characters and graphics. Each teletext screen is encoded, and data designating a program number, page number, display mode, etc. is added. Further, a sync code, an error correction code, etc. are added to form a character signal, which is transmitted by being superimposed on a predetermined horizontal scanning period (H) in the vertical blanking period of the television signal.

In the character multiplex broadcasting system of Japan (hereinafter, abbreviated as Japanese system), the character signals are 14H to 16H and 21H in the odd field and 277H to 279H and 284H in the even field. It is possible to superimpose on and respectively.

In the character-based multiplex broadcasting of the Japanese system, the character signal is a binary signal of "1" or "0", and NRZ (Non Ret
urn to Zero) signal format and its transmission speed is 5.72
7272 Mb / s, and the color subcarrier frequency fsc (=
It corresponds to 8/5 times (3.579545 MHz).

"1" of the character signal in the transmission line of layer 1
The levels of “0” and “0” are 70 IRE (70% white) and 0 IRE (pedestal level), respectively, as shown in FIG. 9A. In addition, as shown in FIG. 9B, the data line of hierarchy 2 which is superimposed in one horizontal scanning period is 1
The data is divided into a sync part including a 6-bit bit sync code and an 8-bit byte sync code, and a data packet including a 190-bit information bit and a 82-bit check code.

As shown in FIG. 9C, the bit synchronization code (Clock Run-in) for clock recovery is configured such that eight "1" s and "0s" are alternately arranged to establish byte synchronization. The byte synchronization code (Framing Code) for extracting the data packet part is "1110010".
1 ”array.

The check code for correcting an error in packet units has a code structure called a shortened difference set cyclic code which can correct all errors of 8 bits or less occurring in one packet (272, 190). ing.

Although illustration is omitted, the program data of the layer 5 is composed of program management data and each page data, and the program data header has a number for identifying the program and a group of programs. There is a number.

As shown in FIG. 10, in the television receiver compatible with the character multiplex broadcasting, the broadcast radio wave received by the antenna 1 is supplied to the tuner 11 to select the broadcast signal of a desired channel. The tuner 11 includes a video and audio demodulator (not shown), and the video signal and audio signal from the tuner 11 and the video signal and audio signal from the external VTR 2 are sent to the selector 12. The video signal Sv and the audio signal Sa supplied and selected by the selector 12 are supplied to the video signal processing circuit 13v and the audio signal processing circuit 13a, respectively,
Predetermined signal processing is performed.

The output of the audio signal processing circuit 13a is supplied to the speaker 16 via the adding circuit 14a and the amplifier 15a, and the output of the video signal processing circuit 13v is supplied to the picture tube 17 via the adding circuit 14v and the video output circuit 15v.
Is supplied to.

The video signal Sv from the selector 12 is supplied to the sync separation circuit 18, and the horizontal sync signal Hsy and the vertical sync signal Vsy obtained by the sync separation circuit 18 are supplied to the horizontal / vertical deflection circuit 19. The output of the deflection circuit 19 is supplied to the deflection coil 17y.

Reference numeral 20 denotes a system control circuit (microcomputer, CPU), which supplies predetermined control signals from the control circuit 21 to the tuner 11 or the video output circuit 15v, as indicated by the broken line in FIG.

Reference numerals 30, 40 and 50 respectively denote a data extraction system, a decoding / display system and a control system of the character multiplex decoder, which are the data extraction system 30 and the decoding / display system 4.
0 is configured as shown in FIG.

The video signal Sv from the selector 12 is supplied to the data sampling system 30, and the sync separation circuit 18 is shared by the data sampling system 30 and the decoding / display system 40.
The horizontal synchronizing signal Hsy and the vertical synchronizing signal Vsy are supplied. Then, from the decoding / display system 40, a video signal corresponding to a character or a figure is supplied to the adding circuit 14v, and an audio signal corresponding to an additional sound is supplied to the adding circuit 14a.

The control system 50 is a microcomputer (CP
U) 51, a program RAM 52, a display VRAM 53, a work RAM 54 and a character ROM 55, which are connected through a system bus 56. The data extraction system 30 and the decoding / display system 40 are connected to the bus 56 via interfaces not shown. The system control circuit 20 is also connected to the bus 56.

Then, for example, an infrared transmission type remote control receiver 57 is connected to the bus 56 via an interface (not shown), and a corresponding remote control transmitter 58 is provided.
Allows remote control of the television receiver and character multiplex decoder.

A data sampling system 3 as shown in FIG.
At 0, the video signal is commonly supplied to the waveform equalization circuit 31 and the sync separation circuit 32. The waveform equalization circuit 31 shapes the waveform of the character signal in order to reduce ghosts that occur during transmission and errors caused by the influence of the television receiver.

The output of the sync separation circuit 32 is supplied, and the timing signal generation circuit 33 forms a gate pulse for extracting a character signal and a clock pulse used as a reference pulse for code identification and decoding processing of the character signal. Is played. Further, the timing signal generation circuit 33
In, a clock signal for display is also formed.

In the character signal separation circuit 34, the gate pulse from the timing signal generation circuit 33 is superimposed on the vertical blanking periods 14H to 21H and 277H to 284H during the output of the waveform equalization circuit 31, as described above. The character signal is separated, the code identification of "0" and "1" is performed at the timing of the reproduction clock, and the data packet is extracted.

The data extracted by the character signal separation circuit 34 is written in the buffer RAM 35, and the error correction circuit 3
By 6, the error caused by noise or waveform distortion that occurs during transmission or in the receiver is corrected. To correct this error,
As described above, the 82-bit check code [(272, 190) shortened difference set cyclic code] at the end of the data packet is used. The character data whose error has been corrected by the correction circuit 36 is transferred to the decoding / display system 40 via the bus 56.

In the decoding / display system 40 as shown in FIG. 11, the character data from the data extracting system 30 is fetched into the buffer RAM 41, and the program ROM 42 is loaded.
It is decrypted by the CPU 51 according to the procedure written in. The dot pattern data corresponding to the information of the decoded character or figure is read from the character ROM 55,
It is transferred to the display VRAM 53.

The character ROM 55 stores dot pattern data of mosaic figures in addition to alphanumeric characters, kana and kanji, and therefore the character ROM 55 is also called a character generator.

The dot pattern data transferred to the display VRAM 53 is read at the scanning cycle of the video signal by the address data from the display control circuit 43 and supplied to the adding circuit 14v. On the other hand, an audio signal is extracted from the additional sound generation circuit (so-called sound source) 44 corresponding to the additional sound data in the program data and supplied to the adding circuit 14s.

[0026]

By the way, in the United States, closed captions (CloS) are provided for the hearing impaired, in which characters are displayed on the screen at the same time as the television image.
sed Caption) broadcasting is being carried out.

In this closed caption broadcast,
During the vertical blanking period of the television signal, the character information based on the American standard code for information exchange is superimposed on the 21st H of the odd field, and the information for field discrimination is superimposed on the 284H of the even field.

In closed captioning, the coded composite video signal is composed of a clock run-in-burst having a 7-cycle sinusoidal waveform and a binary NRZ character signal as shown in FIG. 12A. The levels of "1" and "0" of the signal are 50 IRE, respectively.
(50% white) and 0IRE (pedestal level). The clock frequency is 32 times the horizontal scanning frequency fH (= 503.4965 kHz), and the cycle of the clock run-in burst is made equal to the clock cycle.

The data structure of the character signal is, as shown in FIG. 12B, a 1-bit start bit S and 16-bit data. This data consists of a 7-bit code 1 (B1) and a 2-bit code (B2), and a 1-bit error detection code C added after each code.

Further, with the widespread use of programs with closed captions, the number of video software programs using tapes or disks as package media with closed caption English subtitles is increasing. Recently, in Japan, programs with closed captions in the United States have started to be broadcast via communication satellites (CS), and video software with closed captions has also been imported.

In Japan, these broadcasts and video software are used not only for hearing impaired persons but also for language learning, etc., so that an external closed caption decoder can be easily obtained. Became.

However, as described above, the closed caption system and the Japanese system have the common point that the character information is superimposed on the 21th H of the vertical blanking period of the television signal, but the clock frequency (data transmission Since standards such as rate) and data structure are different,
In order to view the character information of both methods, it is necessary to prepare a dedicated decoder for each, and there is a problem that the economic burden on the viewer increases.

Further, since most of the hardware for extracting and displaying character information can be shared between the closed caption system and the Japanese system, when a dedicated decoder is prepared for each system as described above, Redundant use of major hardware puts viewers in vain.

When a decoder common to the closed caption system and the Japanese system is embodied in order to solve the above-mentioned problem, the reception or reception is performed in order to perform data processing suitable for each system. It becomes necessary to determine the multiplexing method of the reproduced character information.

In view of the above point, an object of the present invention is to provide a character multiplex system discriminating apparatus capable of discriminating a plurality of character multiplex systems.

[0036]

In order to solve the above-mentioned problems, the character multiplex type discriminating apparatus according to the first aspect of the present invention makes the vertical blanking of the television video signal correspond to the reference numerals of the embodiments described later. A plurality of character multiplex type discriminating apparatus which superimposes character information in a predetermined data format and transmits at a predetermined transmission rate in a predetermined horizontal scanning period of a period, and superimposes in a predetermined horizontal scanning period. It is characterized in that it comprises extraction means 63 for extracting the extracted character information, and transmission rate determination means 71, 72; 75, 76; 75, 77 for determining the transmission rate of the character information obtained by this extraction means. Is.

In the character multiplex type discrimination device according to the second aspect of the present invention, when the reference symbols of the embodiments described later are made to correspond,
A plurality of character multiplex type discriminating apparatus adapted to superimpose character information in a predetermined data format and transmit at a predetermined transmission rate and pattern in a predetermined horizontal scanning period of a vertical blanking period of a television video signal. In addition, it is provided with an extracting unit 63 for extracting the character information superimposed in a predetermined horizontal scanning period, and pattern determining units 78, 79; 36 for determining the pattern of the character information obtained by the extracting unit. It is what

[0038]

According to the first aspect of the present invention, the multiplexing method of the character information is determined based on the transmission rate of the character information extracted in a predetermined horizontal scanning period, and the data processing adapted to the multiplexing method is performed. It becomes possible to

Further, according to the second invention having the above-mentioned structure, the multiplexing method of the character information is determined based on the pattern of the character information extracted in a predetermined horizontal scanning period, and the multiplexing method is selected. It becomes possible to carry out an adapted data processing.

[0040]

【Example】

[First Embodiment] An embodiment of a character multiplex system discriminating apparatus according to the present invention will be described below with reference to FIGS.

FIG. 2 shows the connection relationship between the character multiplex system discrimination circuit of this embodiment and peripheral circuits, and FIG. 3 shows the configuration of this embodiment. In FIG. 2, parts corresponding to those in FIG. 11 are designated by the same reference numerals, and redundant description will be omitted.

In FIG. 2, 30L is a character data extracting system, and a line memory 37 is provided in front of the waveform equalizing circuit 31. This line memory 37 has AD
Through the converter 38, the video signal Sv is supplied in common with the sync separation circuit 32, the gate signal for capturing character data is supplied from the timing signal generation circuit 33, and the output of the line memory 37 is the waveform equalization circuit. 31 is supplied.

A character multiplex system discriminating circuit 60 is connected to the line memory 37 of the character data extracting system 30L. The remaining structure of the character data extracting system 30L is similar to that of the character data extracting system 30 shown in FIG.

In the television receiver equipped with the character multiplex system discriminating circuit of this embodiment,
The dot pattern data corresponding to the character information of the caption system is added to the character ROM 55 shown in FIG. 10 and the program ROM 42 shown in FIG.
Is added with a closed caption decoding procedure.

Referring to FIG. 3, the character multiplex system discriminating circuit 60 is shown.
A includes a data extracting circuit 61 and a sync separation / horizontal counter circuit 62. The video data Dv is commonly supplied to both of them, and the horizontal sync signal Hsy and the vertical sync signal Vsy from the circuit 62 are 21H gate circuits. Is supplied to. Further, the slice voltage Es set to a predetermined level is supplied to the data sampling circuit 61.

In this embodiment, the sampling clock generating circuit 64e causes the frequency to be 4 · fnCK (fnCK =
From the output signal of the crystal oscillation circuit 64x (5.73 MHz), an 8-phase sampling clock with a frequency of fnCK is generated. Frequency 4 · fnCK is the color subcarrier frequency f
It is 32/5 times sc, and although not shown, it is 1/1 for phase synchronization with the color burst signal by the PLL.
Zero-down circuit and 1/6 for generating 8-phase clock
A 4 down converter is provided in the clock generation circuit 64e.

The 8-phase sampling clocks from the clock generation circuit 64e are supplied to the data sampling circuit 61, and the output of the data sampling circuit 61 outputs the selector 65s.
And the clock phase calculation circuit 65c are commonly supplied.
In the phase calculation circuit 65c, based on the bit synchronization code,
The optimum clock phase is calculated.

Based on this calculated phase and the control data Dcp from the CPU 51 (see FIG. 10), the phase determination circuit 65
At d, the optimum clock phase is determined, the selector 65s is controlled by the output of the phase determination circuit 65d,
Of the output data of the data sampling circuit 61, the data corresponding to the optimum clock phase is derived from the selector 65s and supplied to the decoder 66.

The decoder 66 is constructed by using, for example, an RS flip-flop circuit, and "0" is a reset signal and "1" is a set signal. As a result, when multiple data of the closed caption method with a clock frequency of 503 kHz arrives, a large number of consecutive "1" and "0" generated by the Japanese method sampling with a clock frequency of slightly more than 11 times 5.73 MHz. Are respectively converted into "1" and "0" to reproduce the original closed caption clock frequency component.

The center frequency of the output of the decoder 66 is fn.
The 21H gate signal from the gate circuit 63 is supplied to the filter 71 while being supplied to the bandpass filter 71 of CK (= 5.73 MHz), and the filter 71 corresponds to the 21th H of the output data of the decoder 66. Only the clock frequency component having the frequency fnCK is extracted and supplied to the level comparison circuit 72. Then, in the level comparison circuit 72, it is compared with an appropriate set level, and the output of the comparison circuit 72 is supplied to the CPU 51.

Next, the system discriminating operation of the embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 100 is a character multiplex system determination routine. First, in step 101, it is determined whether or not there is multiplex data in the 21st H of the vertical blanking period, and if there is no data, the arrival of data is awaited.

When the character multiplexed data arrives, the process proceeds to the next step 102, and it is judged whether the multiplexed data is of the closed caption system or not. In the embodiment of FIG. 3, it is determined whether the incoming data is of the Japanese type or of the closed caption type depending on the presence or absence of the output of the bandpass filter 71 having the center frequency of 5.73 MHz.

When the Japanese method multiplexed data, for example, the above-mentioned bit synchronization code "10101010" arrives, the incoming data is read by the Japanese method sampling clock frequency (5.73 MHz) as in the conventional case, and is directly decoded. After passing through 66 and the bandpass filter 71, it is supplied to the comparison circuit 72 at a predetermined level.

In addition, when the closed caption system multiplexed data, for example, the above-mentioned clock run-in burst of 503 kHz arrives, the positive and negative half cycles of the data are generated by the Japanese system 5.73 MHz clock. It is sampled and read as 5 to 6 consecutive "1" s and "0" s, eg "111111" and "000000".

In this embodiment, the decoder 66 converts 5 to 6 consecutive "1" s and "0s" into one "1" and "0", respectively, as described above, Since the frequency component of the original clock run-in-burst of 503 kHz is reproduced, the output of the decoder 66 is blocked by the bandpass filter 71.

If it is determined in step 102 that the incoming multiplex data is of the closed caption type, the process proceeds to step 103, data processing of the closed caption type is performed, and the incoming multiplex data is also applied. Is not of the closed caption system, that is, if it is judged to be of the Japanese system, the process proceeds to step 104, and the data processing of the Japanese system is performed.

As described above, in this embodiment, the bandpass filter 71 having the center frequency of 5.73 MHz and the comparison circuit 72 for detecting the output level thereof are provided, and the clock frequency component is discriminated. It is possible to determine which multiplexing method is used based on the transmission rate of, and it is possible to perform data processing adapted to that multiplexing method.

Further, in this embodiment, by providing the decoder 66, it is possible to cope with the closed caption type multiplexed data without switching the frequency (5.73 MHz) of the Japanese type sampling clock.

[Second Embodiment] Next, another embodiment of the character multiplex system discrimination device according to the present invention will be described with reference to FIGS.

The configuration of another embodiment of the present invention is shown in FIG. In FIG. 4, parts corresponding to those in FIG. 3 above are denoted by the same reference numerals, and redundant description will be omitted. In FIG. 4, illustration of a portion relating to clock phase selection as shown in FIG. 3 is also omitted.

In FIG. 4, a character multiplex system discrimination circuit 60 is provided.
The frequency of fnCK (= 5.73 MH) from the sampling clock generation circuit 64 is input to the B data sampling circuit 61.
The sampling clock of z) is supplied, and the output of the data extracting circuit 61 is supplied to the decoder 66.

The output of the decoder 66 is the buffer RAM 7
2H, the 21H gate signal from the gate circuit 63 is also supplied to the buffer RAM 72, and from the buffer RAM 72, among the output data of the decoder 66,
Only the data corresponding to the 21st H is extracted and supplied to the edge pulse extraction circuit 74.

The extraction circuit 74 extracts the edge pulse of the clock and supplies it to the timer 75 and the edge pulse detection circuit 76 in common, and the edge pulse detection circuit 76 outputs the control signal of the timer 75 to the edge pulse detection circuit 76. Output is supplied.

In the embodiment of FIG. 4, the clock frequency of the Japanese system is fnCK (= 5.73 MHz), and the closed
Set the caption clock frequency to fcCK (= 503
kHz), the time period Tt of the timer 75 is set within the range of 2 / fcCK>Tt> 2 / fnCK. The other structure is the same as that shown in FIG.

In the embodiment of FIG. 4, the extraction circuit 74
For example, the down edge of the clock as shown in FIG. 5A is extracted, the timer 75 is activated by this down edge, and the “H” output of the timer 75 as shown in FIG. 76 is activated.

Then, within the time period Tt of the timer 75,
When the detection circuit 76 detects the arrival of the next clock down edge, the CPU determines that the clock is of the Japanese system. Also, the timer 75
If the arrival of the down edge of the next clock is not detected within the time period Tt of, the closed caption system is determined.

As described above, in this embodiment, the timer 75 set within the range of twice the clock period of each of the Japanese system and the closed caption system, and the edge pulse detection circuit 76 are provided, and the clock period is set. It is possible to determine which multiplexing method is used based on the transmission rate of the character information by determining the length of, and it is possible to perform data processing adapted to that multiplexing method.

[Third Embodiment] Next, still another embodiment of the character multiplex type discrimination apparatus according to the present invention will be described with reference to FIGS. 6 and 7. The structure of still another embodiment of the present invention is shown in FIG. In FIG. 6, parts corresponding to those in FIGS. 3 and 4 described above are denoted by the same reference numerals, and redundant description will be omitted.

The character multiplex system discrimination circuit 60 of the embodiment shown in FIG.
In C, an edge pulse counting circuit (counter) is used instead of the edge pulse detecting circuit 76 of the embodiment shown in FIG.
77 is provided, and the counter 77 is activated by the output of the timer 75. The other structure is the same as that shown in FIG.

In the embodiment shown in FIG. 6, the clock frequency of the Japanese system is fnCK (= 5.7) as in the embodiment shown in FIG.
3 MHz) and the clock frequency of the closed caption system is fcCK (= 503 kHz), the time period Tt of the timer 75 is set within the range of 2 / fcCK>Tt> 2 / fnCK.

Also in the embodiment shown in FIG. 6, the extraction circuit 74 extracts, for example, a down edge of the clock as shown in FIG. 7A, and the down edge extracts the timer 7 from the down edge.
5, the edge pulse counting circuit 77 is activated by the output of "H" from the timer 75 as shown in FIG. 7B, and the down edge of the clock is counted.

Then, within the set period Tt of the timer 75,
When the counting circuit 77 counts one or two down edges, the CPU determines that the clock is of the closed caption type. Further, when 14 to 20 down edges are counted within the set period Tt of the timer 75, it is determined that the clock is of the Japanese system.

As described above, in this embodiment, the timer 75 set within the range of twice each clock cycle of the Japanese system and the closed caption system, and the edge pulse counting circuit 77 are provided, and the clock cycle is set. It is possible to determine which multiplexing method is used based on the transmission rate of the character information by determining the length of, and it is possible to perform data processing adapted to that multiplexing method.

[Fourth Embodiment] Next, still another embodiment of the character multiplex type discrimination device according to the present invention will be described with reference to FIG.

FIG. 8 shows the configuration of still another embodiment of the present invention.
Shown in In FIG. 8, portions corresponding to those in FIGS. 4 and 6 described above are denoted by the same reference numerals, and redundant description will be omitted.

The character multiplex system discrimination circuit 60 of the embodiment shown in FIG.
In D, 78 is a pattern matching detection circuit and 79 is a code pattern generation circuit, which is a pattern matching detection circuit 78.
Is supplied with the output of the buffer RAM 73,
The output of the code pattern generation circuit 79 is supplied. The rest of the configuration is the same as in FIGS. 4 and 6 above.

In the embodiment shown in FIG. 8, the Japanese system bit sync code as shown in FIG. 9C and the closed caption system clock run-in burst and start as shown in FIG. Based on a bit and
It is determined which method is used.

A code, for example, as shown in FIG. 9C,
When a code having the same pattern as the Japanese system bit synchronization code, in which eight "1" s and "0s" alternately appear, and the Japanese system bit synchronization code arrives at the pattern matching detection circuit 78, The detection circuit 78 determines that the two match.

On the other hand, when the multiplexed data of the closed caption system arrives at the data extracting circuit 61 of the discriminating circuit 60D, a clock run-in-burst of 7-cycle sinusoidal waveform as shown in FIG. 12A. Will be sliced so that each of the seven "1" s and "0" s will appear alternately from the decoder 66. Further, the subsequent start bit S is “0” in binary NRZ, and is “0” at the same rate as the clock run-in burst.
It becomes "0".

Therefore, the detection circuit 78 includes 16-bit "101010101010100" corresponding to the clock run-in burst and the start bit.
The data pattern of "0" is supplied and compared with the 16-bit pattern "1010101101101010" from the pattern generating circuit 79, which is the same as the Japanese bit synchronization code.

As is clear from the above, the last 3 bits of the pattern corresponding to the clock run-in burst and the start bit are "000", and the last 3 bits of the pattern from the code pattern generating circuit 79 are "010". "
Therefore, the detection circuit 78 determines that the two do not match.

As described above, in this embodiment, the pattern coincidence detection circuit 78 and the code pattern generation circuit 79 for generating the code having the same pattern as the Japanese system bit synchronization code are provided to determine the bit synchronization data. As a result, it is possible to determine which multiplexing method is used based on the pattern of the character information, and it is possible to perform data processing adapted to that multiplexing method.

[Fifth Embodiment] Next, still another embodiment of the character multiplex type discrimination device according to the present invention will be described.

As described above, in the character-based multiplex broadcasting of the Japanese system, the (272,190) shortened difference set cyclic code is used so that all the errors of 8 bits or less occurring in one packet can be corrected. There is. The generator polynomial G (x) of the (272,190) shortened difference set cyclic code is expressed by the following equation (1).
The remainder obtained by dividing the information data by the generator polynomial G (x) is added as a check code.

G (x) = x ⁸² + x ⁷⁷ + x ⁷⁶ + x ⁷¹ + x ⁶⁷ + x ⁶⁶ + x ⁵⁶ + x ⁵² + x ⁴⁸ + x ⁴⁰ + x ³⁶ + x ³⁴ + x ²⁴ + x ²² + x ¹⁸ + x ¹⁰ + x ⁴ +1 (1).

Then, on the receiving side, the error is corrected by the majority decision based on the check matrix generated by the generator polynomial. Whether or not this error correction is correctly performed is determined by ER (bit 4 of the 0th byte). ) Is "0" or "1".

In this embodiment, as described above (272,
190) If the error correction is correctly performed based on the result of the error correction processing by the shortened difference set cyclic code,
The incoming multiplex data is determined to be of the Japanese system, and if the error correction is not performed correctly, the incoming multiplex data is determined to be of the closed caption system.

As described above, in this embodiment, it is possible to determine which multiplexing method is used based on the processing result in the error correction circuit 36, in other words, based on the pattern of character information. , It becomes possible to perform data processing adapted to the multiplexing method.

[0089]

As described above, according to the present invention, when the character information is superimposed on the 21th H of the vertical blanking period of the video signal with the transmission rate and the pattern which are different depending on the multiplexing system, the band filter and the level are used. The comparison circuit determines the clock frequency of the character information, or the timer and the edge pulse detection circuit or the edge pulse counting circuit determine the clock cycle of the character information to determine the multiplexing method based on the transmission rate. be able to. Alternatively, it is possible to determine the multiplexing method based on the pattern of the character information by determining the bit synchronization data of the character information by the pattern matching circuit or by determining the success or failure of the error correction.

Therefore, in the decoder that is common to the Japanese character multiplex system and the US closed caption system, data processing suitable for each system can be performed according to the above system determination result. .

[Brief description of drawings]

FIG. 1 is a flow chart for explaining the operation of an embodiment of a character multiplex system discrimination device according to the present invention.

FIG. 2 is a block diagram for explaining an embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

5 is a waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing a configuration of still another embodiment of the present invention.

FIG. 7 is a waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 8 is a block diagram showing the configuration of still another embodiment of the present invention.

FIG. 9 is a conceptual diagram for explaining the present invention.

FIG. 10 is a block diagram showing an example of the overall configuration of a conventional television receiver compatible with character multiplex broadcasting.

11 is a block diagram showing a configuration of a main part of the television receiver of FIG.

FIG. 12 is a conceptual diagram for explaining the present invention.

[Explanation of symbols]

 20 System Control Circuit (CPU) 30, 30L Character Data Extraction System 36 Error Correction Circuit 37 Line Memory 40 Character Data Decoding Display System 42 Program ROM 50 Control System 51 CPU 55 Character ROM 60 Character Multiplex System Discrimination Circuit 61 Character Data Extraction Circuit 63 21H Gate circuit 64 Sampling clock generation circuit 66 Decoder 71 Band filter 72 Level comparison circuit 73 Buffer 74 Edge pulse extraction circuit 75 Timer 76 Edge pulse extraction circuit 77 Edge pulse counting circuit (counter) 78 Pattern match detection circuit 79 Code pattern generation circuit 100 Character multiplex method determination routine

Claims (7)

[Claims] 1. A plurality of character multiplex systems in which character information is superimposed in a predetermined data format and transmitted at a predetermined transmission rate during a predetermined horizontal scanning period of a vertical blanking period of a television video signal. And a transmission rate determining means for determining a transmission rate of the character information obtained by the extracting means, the extracting means extracting the character information superimposed in the predetermined horizontal scanning period. Character multiplex system identification device. 2. The character multiplex system discriminating apparatus according to claim 1, wherein the transmission rate discriminating unit is a unit for extracting a frequency component corresponding to the transmission rate of a specific character multiplex system. 3. The character multiplex system discriminating apparatus according to claim 1, wherein the transmission rate discriminating unit is a period measuring unit which responds to a signal component corresponding to the transmission rate of the specific character multiplex system. 4. The character multiplex type discriminating apparatus according to claim 1, wherein the transmission rate discriminating unit is a unit for counting signal components corresponding to the transmission rate of the specific character multiplex system. 5. A plurality of characters which are superimposed at a predetermined data format in a predetermined horizontal scanning period of a vertical blanking period of a television video signal and are transmitted at a predetermined transmission rate and pattern. A multiplex type discriminating apparatus comprising: a sampling unit for sampling character information superimposed in the predetermined horizontal scanning period, and a pattern discriminating unit for judging a pattern of the character information obtained by the sampling unit. Character multiplex system identification device. 6. The character multiplex system discrimination device according to claim 5, wherein the pattern discrimination means is a data pattern comparison means of the specific character multiplex system. 7. The character multiplex system discriminating apparatus according to claim 5, wherein the pattern discriminating unit is an error correcting unit of the specific character multiplex system.