JPH02312368A - Television receiver - Google Patents

Abstract

PURPOSE:To display a character on the screen of a display means at the same display state in spite of the kind of the signal system of a received video signal by discriminating the signal system of the received video signal, and varying the oscillation frequency of an oscillation circuit based on discriminated output. CONSTITUTION:The character on the screen of the display means is displayed by a character signal generating means 72 which discriminates the signal system of the received video signal and generates a character signal setting a synchronizing signal as reference. Respective display position of the character is controlled with a reference signal, and the oscillation frequency of the oscillation circuit 68 which generates the reference signal is varied with the discriminated output of the signal system of the received video signal. Thereby, it is possible to display the character at the same state on the screen of the display means in spite of the kind of the signal system of the received video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television receiver that displays characters on the screen of a display means.

[Summary of the invention]

The present invention provides a television receiver that receives video signals of a plurality of signal systems with different frequencies of synchronization signals.
Character signal generation means that determines the signal format of the received video signal and generates a character signal based on the synchronization signal displays a character on the screen of the display means, and controls each display position of the character using the reference signal. , the oscillation frequency of the oscillation circuit that generates the reference signal is
By making it variable depending on the output for determining the signal format of the received video signal, it is possible to display the character in the same display state on the screen of the display means, regardless of the signal format of the received video signal. It has been made possible.

[Conventional technology]

A television receiver has been proposed in which characters such as letters and symbols are displayed on the screen of a CRT tube, superimposed on images of received video signals.

Such a television receiver is provided with a character signal generation circuit including a character ROM, etc., and controls the generation timing of the character signal based on the horizontal synchronization signal and vertical synchronization signal separated from the received video signal.
Characters are displayed at predetermined positions on the screen of the T screen.

[Problem to be solved by the invention]

By the way, such a television receiver is, for example, N
If it is possible to receive video signals of multiple signal systems with different frequencies of synchronization signals such as horizontal synchronization signals, such as video signals of TSC system and MIISE system,
The following problems arise.

When receiving an NTSC video signal, for example, write 10 numbers horizontally on the screen as shown in Figure 8A.
Suppose that it is displayed in a row.

Next, when receiving a video signal of the Musti method,
Similarly, if you try to display 10 numbers in one horizontal line on the screen, as shown in Figure 8B, the first five numbers are twice as wide as in Figure 8A compared to Figure 8A. will be displayed at twice the interval, and the last five numbers will not be displayed.

This is the NTSC system and? In both IUSE and NTSC systems, the frequency of the vertical synchronization signal of the video signal is the same as 60Hz, but the frequency of the horizontal synchronization signal is 15°7 in the case of the NTSC system.
In the case of 5 kHz SMUSE method, it is 31.5'H
z and the frequency of the horizontal synchronizing signal of the video signal of the MIJSE system is twice that of the NTSC system, and
The oscillation frequency of the oscillation circuit that generates the oscillation signal to regulate the horizontal display position of the character displayed on the RT screen (higher frequency than the frequency of the horizontal synchronization signal) is This is because they are the same.

In view of this, the present invention provides a television receiver that receives video signals of a plurality of signal systems with different synchronization signal frequencies, regardless of the signal system of the received video signal. There are some attempts to propose methods that can display characters in the same display state.

[Means to solve the problem]

The present invention provides a television receiver that receives video signals of a plurality of signal systems with different frequencies of synchronization signals.
Discrimination means (17) for discriminating the signal format of the received video signal
), a character signal generating means (72) that generates a signal of the character to be displayed on the screen of the display means (35) based on a synchronization signal, and each display of the character to be displayed on the screen of the display means (35). It has an oscillation circuit (68) that generates a reference frequency signal that is a reference for controlling the position, and the oscillation circuit (68) generates a reference frequency signal that is a reference for controlling the position.
68) in which the oscillation frequency is made variable.

[Effect]

According to the present invention, the signal system of the received video signal is determined based on the determination output of the determination means (17), and the oscillation frequency of the oscillation circuit (68) is varied accordingly. (35) Display the characters in the same display state on the screen.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a television receiver device according to an embodiment as a whole, and this will be explained below.

(1) shows the receiver as a whole, and (2) shows this receiver!
Figure 2 shows a remote controller that remotely controls fi(1).

The remote controller (2) includes a remote control signal generation circuit (5), a keyboard (6), a modulation circuit (7), a transmitter (infrared light emitting diode) (8), and the like. Remote controller (2)
The infrared remote control signal from the transmitter (8) of the receiver (
1) is received by the receiver (infrared photodiode) (3), further subjected to tMm by the demodulation circuit (4), and then supplied to the microcomputer (9). still,
(10) is a clock signal generation circuit, and the clock signal from this circuit is supplied to the microcomputer (9).

Next, Uke@! The configuration of machine (1) will be explained. (11) is a UHF/VHF antenna, and a high frequency reception signal from this antenna is supplied to and received by a UHF/VHF tuner (13). (12) is an SHF antenna, and a high frequency reception signal from this antenna is supplied to and received by an SHF tuner (14). Also, these tuners (13), (1
The channel selection in 4) is performed under the control of the microcomputer (9). The received signals from the tuners (13) and (14) are respectively supplied to video detection circuits (15) and (16) and detected, and then switched to a switching circuit (18) controlled by a microcomputer (9). supplied to In addition, the video detection circuit (16) on the SHF tuner (14) side
) is the output of ? ItlSE (Multiple Sub-Nyquist Sampling Encoding)/NTSC
It is supplied to a discrimination circuit (17), and its discrimination output is supplied to a microcomputer (9). This discrimination circuit (17
), a discrimination signal is output depending on whether the frame pulse of the MIISE signal or the horizontal and vertical synchronization signals of the NTSC signal are detected.

When a high frequency MUSE signal is received by the SHF tuner (14), this tuner (14) FM demodulates the high frequency MUSE signal and
The MUSE signal obtained by Mffi tuning has a cutoff frequency of 8
．． After being low-pass filtered with 15 MHz, it simply passes through the video detection circuit (16) and is supplied to the MUSE decoder (20) through the switching circuit (18).

this? 1l ISE decoder (20) (7) configuration is published in the magazine rNHK Technology Research, Vol. 39, No. 2, 1988, "Hi-Vision Technology", 1st edition published on November 25, 1988 (published by Japan Broadcasting Publishing Association), etc. Since it is the same as that disclosed, a description of its configuration will be omitted, but the configuration of its input side will be briefly explained. That is, the input MUSE signal is supplied to an A/D conversion circuit to convert it into a digital MUSE signal, and the digital MUSIli signal is supplied to a separation circuit to separate a synchronization signal and a control signal. .A PLL circuit for reproducing a 2 MHz sampling clock signal is provided to obtain a 16.2 MHz sampling clock signal whose frequency is synchronized with the frame pulse of the MUSE signal and whose phase is synchronized with the horizontal synchronization signal (HD) of the MUSE signal. , is supplied to the above-mentioned A/D conversion circuit.

The red, blue, and green signals R, G, .

Further, the digital synchronization signal obtained from the MUSE decoder (20) is supplied to the synchronization detection circuit (3rd), and the horizontal synchronization signal (31.5kHz) HD and vertical synchronization signal (60Hz) VD obtained from this are supplied. is a microcomputer (
9) and is also supplied to the deflection circuit (36) through the switching circuit (41).

When an NTSC signal is received by the tuner (13) or (14), the NTSC signal from the switching circuit (18) is
The C composite color video signal Cv is supplied to a circuit (25) that sets the signal level of a part of the character display part of the screen to 0, and is also supplied to a synchronization detection circuit (39) to detect horizontal synchronization signals (15, 75kHz) HD and vertical sync signal (60Hz
) VD is obtained and supplied to the microcomputer (9) and also to the deflection circuit (36) through the switching circuit (41).

When an NTSC signal is received by the tuner (13) or (14) and the NTSC composite color video signal C from the switching circuit (18) is converted to an IDTV (In-Blue Definition TV) signal, the NTSC signal is received by the tuner (13) or (14).
The C composite color video signal CV is converted into an IDTV conversion circuit (19
) is supplied to the luminance/chromaticity separation circuit (21) to separate the luminance signal and chromaticity signal, and the obtained luminance signal and chromaticity signal are supplied to the compression circuit (22) for time compression in the horizontal direction. .

Then, the compressed luminance signal and chromaticity signal from the compression circuit (22) are supplied to a double speed conversion circuit (23) for double speed conversion, and then supplied to a decoder (24) for red, blue, and green colors. Obtain signals R, G, and B. The red, blue, and green signals R and GSB are then supplied to a circuit (25) that sets the signal level of a part of the character display section of the screen to O. Also, at this time, the horizontal synchronization signal HD from the synchronization detection circuit (39)
and the vertical synchronization signal VO are supplied to the double-speed synchronization circuit (40), where only the frequency of the horizontal synchronization signal HD is doubled, and the horizontal synchronization signal (31.5kHz) and vertical synchronization signal (60Hz) obtained therefrom are ) is a microcomputer (
9) and is also supplied to the deflection circuit (36) through the switching circuit (41).

Moreover, the switching circuit (41) has a built-in horizontal synchronization signal generation circuit, and the pseudo horizontal synchronization signal (31) generated from this
, 5kHz) and the pseudo vertical synchronization signal (6(LHz)) are
It is supplied to a deflection circuit (36).

The switching of this switching circuit (41) and the generation of the pseudo synchronization signal are performed by the microcomputer (9).
be controlled.

In addition, the red, blue, and green signals R, G, B or composite color video signal C from the circuit (25) that sets the signal level of the character display part of a part of the screen to 0 are used to control the character display part of a part of the screen. A blanking circuit (27) that reduces the signal level of the entire screen to 0 through a circuit (213) that reduces the signal level of the entire screen to 1/2.
supplied to In addition, each of the above circuits (25), (26),
The operation or non-operation of (27) is a microcomputer (9)
controlled by

(42) is a character signal generation circuit, which is supplied with a read control signal and an address signal (character selection signal) from the microcomputer (9), as well as horizontal and vertical synchronization signals corresponding to the received signal. and red, green and blue character signals Rc, GcsB having predetermined timing with respect to the vertical synchronization signal.
Generate C.

The specific configuration of this character signal generating circuit (42) will be described later with reference to FIG.

The red, green, and blue character signals Rc, Gc, and Bc from the character signal generation circuit (42) are sent to the contrast variable circuit (43) and the clamp and brightness variable circuit (4).
4), the signal is supplied to a circuit (45) that turns the signal level on and off at a predetermined frequency. These circuits (43),
(44) is controlled by an adjustment signal based on manual adjustment from input terminals (47) and (4B), and the clamp and brightness variable circuit (44) is controlled by a microcomputer (
It is also controlled by a signal related to the horizontal synchronization signal from 9).

In addition, the circuit (45) for turning on and off the signal level connects the collector-emitter of an NPN transistor between each transmission path of the red, green, and blue character signals Rc, Gc, and Bc and the ground, for example. Can be configured. These transistors are then connected to a microcomputer (
The on/off control is performed at a predetermined frequency (period) by the control signal from 9).

Red, blue and edge color signals qR from blanking circuit (27)
, G, B, and red, green, and blue character signals Rc and GCsBc from the circuit (45) for turning on and off signal levels are supplied to adders (29), (30), and (31), respectively, and added. After that, the signal is supplied to a switching circuit (33) containing an amplifier (34).

Further, the composite color video signal CV from the blanking circuit (27) and the green character signal Gc from the circuit (45) for turning on and off the signal level are supplied to the adder (28) and added, and then the NTSC decoder (32) and are converted into red, blue and green signals R1G and B, respectively, and then supplied to a switching circuit (33) containing an amplifier (34). This switching circuit (33) is switched and controlled by a microcomputer (9).

The red, blue, and green signals R, G, and B from the switching circuit (33) and amplified by the amplifier (34) are then amplified by the amplifier (34) and then connected to a color cathode ray tube as a display means. (35) is supplied to each cathode or grid.

The deflection signal from the deflection circuit (36) is supplied to horizontal and vertical deflection means (not shown) of the color cathode ray tube (35).

(49) is an audio ROM, to which the read control signal and address signal A from the microcomputer (17) are sent.
By supplying D, various synthesized audio signals are generated, and the signals are supplied to the adder (51) and added to the TV audio signal from the input terminal (50), and the added output is a low frequency signal. Through the amplifier (52), the speaker (53)
).

Next, referring to FIG. 2, the specific configuration of the character signal ordering circuit (42) in FIG. 1 will be described. This character signal generation circuit (42) is entirely composed of an IC.

(61) is an interface circuit that receives data signals, clock signals, etc. from the microcomputer (9) in FIG. 1, and outputs write signals, data signals, and address signals.

(72) is a character ROM with 12 dots horizontally and 16 dots vertically.
Character signals of 96 types of dot characters (letters, numbers, alphabets, etc.) are stored, and according to the address signal from the address multiplexer (71),
The character signals of the corresponding addresses are read out line by line and sent to the output circuit (63) through the shift register (74).
).

(70) is the data RAM, and the CRT (35) in Figure 1
8 rows and 16 columns of character codes (1
7 bits per character). The character code signal read from this data RAM (70) is then used as an address signal.
Through the address multiplexer (71) mentioned above, it is supplied to the character RAM (72) and also to an 8x7-bit row display control register (RAM) (74) that stores row display control data for eight rows. Ru. Also, this line display control register (73)
The row display data read from is supplied to the output circuit (6).

Further, (62) is a 6×8-bit screen display control register that stores screen display control data, and receives the write signal, data signal, and address signal from the interface circuit (61), and outputs the screen display control signal. It is supplied to the output circuit (63).

Next, writing and reading of character data to and from the data RAM (70) will be explained.

The data RAM (70) is an interface circuit (
When a write signal is supplied from the microcomputer (61) and the write state is entered, the microcomputer (61) shown in FIG.
9), the character data signal supplied through the interface circuit (61) is written to the predetermined address.

When reading this data RAM (70), the character data stored in the data RAM (70) is read out by the horizontal and vertical address signals from the address multiplexer (68), and the character data is used as an address signal. Address multiplexer (
71) to the character RAM (72), and a character signal corresponding to the character code is read out.

Next, the horizontal and vertical address signals supplied to this data RAM (70) will be explained. The horizontal address signal is generated from the horizontal position counter (64) and the vertical address signal is generated from the vertical position counter (65). The vertical address signal generated from the vertical position counter (65) is also supplied to the character ROM (71) through the address multiplexer (71).

(66) is a vertical synchronous circuit, (67) is a horizontal synchronous circuit,
The vertical synchronization signal and horizontal synchronization signal (external vertical synchronization signal and external horizontal synchronization signal) separated from the television signal currently being received are supplied to synchronize with the external vertical synchronization signal and external horizontal synchronization signal, respectively. generates a vertical synchronization signal and a horizontal synchronization signal (internal vertical synchronization signal and internal horizontal synchronization signal).

Then, the vertical synchronization signal from the vertical synchronization circuit (66) is
A vertical position counter (65) is supplied. In addition, the horizontal synchronization signal from the horizontal synchronization circuit (67) is sent to the horizontal position counter (64), the vertical position counter (65), and the vertical synchronization circuit (
66) and an oscillation circuit (68).

Further, an oscillation signal from the oscillation circuit (68) is supplied to the interface circuit (61), horizontal position counter (64), vertical synchronization circuit (66), and horizontal synchronization circuit (67).

Therefore, the horizontal position counter (64)
8) and counts the oscillation signals from the horizontal synchronization circuit (
It is reset by the horizontal synchronization signal from 67). Similarly, the vertical position counter (65)
7), and is reset by the vertical synchronization signal from the vertical synchronization circuit (66).

Now, in the case of an NTSC television signal (video signal), the horizontal synchronization signal frequency is 15.75kHz and the vertical synchronization signal frequency is 60H2, whereas MUS
In the case of E format television signals (video signals), the frequency of the horizontal synchronizing signal is 31.5kHz, the frequency ratio of the horizontal synchronizing signals of both types is 1:2, and the frequency of the vertical synchronizing signal is It's the same.

Therefore, if characters in 8 rows and 16 columns are displayed on the screen of the CRT (35) when an NTSC television signal is received, the oscillation frequency of the oscillation circuit (68) at this time is Since it is 5MHz, MUS
When receiving E format television signals, if the oscillation frequency of the oscillation circuit (68) is set to lOMHz, in this case as well, the CRT (35) On the screen, 8 lines 1
Six columns of characters can be displayed with the same size and spacing.

Note that even when receiving an NTSC television signal, the oscillation circuit (68) is controlled by a control signal from the microcomputer (9) even when the television signal is converted to an IDTV signal and received. Then, the oscillation frequency is switched to lOMHz.

Next, two specific examples of the oscillation circuit (68) in FIG. 2 are shown in FIGS. 3 and 4.

In the oscillation circuit shown in FIG. 3, a coil L is connected between the input and output terminals of the inverter INV, and the input and output terminals are grounded through capacitors CH and C2, respectively.
The input terminal of is grounded through the capacitor C3 and the collector-emitter of the NPN transistor Q, and the oscillation frequency control signal (DC current) from the microcomputer (9), that is, from the input terminal T1, is connected to the transistor through the resistor R. This is an LC oscillation circuit constructed by connecting power source B to the collector of transistor Q through resistor R2. Here, input terminal T
, by changing the level of the frequency control signal supplied to two types, turning on the collector-emitter of transistor Q,
By turning it off, the frequency of the oscillation signal output from the output terminal T2 is changed into two types: 5 MHz and 10 MHz.

The oscillation circuit shown in FIG. 4 connects a coil L between the input and output terminals of an inverter INV, and connects the input and output terminals to ground through a series circuit of a capacitor C4 and a variable capacitance diode vC1, as well as a capacitor C2. ), that is, the digital frequency control signal from the input terminal TI' is supplied to the D/A conversion circuit DE, which converts it into an analog frequency control signal, and the analog frequency control signal (DC signal) from the input terminal T. This is an LC oscillation circuit in which the voltage is applied to the variable capacitance diode VC through the resistor R3. Here, the level of the digital frequency control signal supplied to the input terminals T, / is changed into two types, and thereby the capacitance of the variable capacitance diode vC1 is changed into two types, and the oscillation frequency is set to 5MHz and lO
MHz and 2 types.

Next, in the character signal generation circuit shown in FIG.
After delaying each by a predetermined amount, the vertical synchronization circuit (6
6) and the horizontal synchronization circuit (67), and each delay amount is set to an arbitrary desired value (in the case of a vertical synchronization signal, the delay The amount of delay is in the range of O to 1 vertical period period, and in the case of a horizontal synchronization signal, the delay amount is in the range of 0 to 1 horizontal period period), as shown in FIG. 35) The horizontal and vertical display start positions of the characters displayed in the display area on the screen can be arbitrarily varied.

Next, referring to FIG. 5, variable delay circuit DL.

A specific example will be explained. It goes without saying that the variable delay circuit shown in FIG. 5 can also be applied to the variable delay circuit DL2.

This variable delay circuit is composed of two stages of cascade-connected monostable multivibrators MHI and MM2.

The monostable multi-bibreak MM at the front stage is a time constant circuit consisting of a resistor R4 connected between power supply element B and the main body, and a series circuit of capacitor C5 and variable capacitance diode VC2 connected between power supply element B and the main body. In addition to providing
From the microcomputer (9), that is, input terminal T6
The digital delay amount control signal from the D/A converter circuit DA
2 and is converted into an analog delay amount control signal, and the analog delay amount control signal from terminal T7 is connected to resistor R
5, the time width of the output pulse of the monostable multivibrator MM depends on the level of the analog delay amount control signal supplied to the connection point between the capacitor C5 and the variable capacitance diode VC2 of the time constant circuit. (See FIG. 6B) is controlled.

The monostable multi-bibreak MM2 in the latter stage includes a time constant circuit consisting of a resistor R6 connected between the power supply element B and the main body, and a capacitor C6 connected between the power supply element B and the main body, and the time constant is constant. , output pulse time width τ2
(see Figure 6C) is constant.

Then, an external vertical synchronization signal (Fig. 6C
) is supplied to the monostable multi-bi break MM in the preceding stage, and rises at the rising edge of its external vertical synchronization signal, and falls after a predetermined time τ1 has elapsed.
(see Figure B) is output to the terminal T4, which is supplied to the subsequent monostable multivib break signal 2, and from the output terminal T5, it rises at the falling edge of the rectangular wave signal (see Figure 6 B), and the time τ2 [external After the time width of the vertical synchronizing signal (FIG. 6A) is approximately the same as that of the vertical synchronizing signal (FIG. 6A), an externally delayed vertical synchronizing signal (see FIG. 6C) that falls is output.

Thus, by arbitrarily selecting the delay amount of the variable delay circuits DL+ and DL2, the delay amount (phase) of the external vertical synchronization signal and the external horizontal synchronization signal can be changed, as shown in FIG. , the horizontal and vertical display start positions of characters to be displayed on the screen of the CRT (35) can be arbitrarily and easily changed.

〔Effect of the invention〕

According to the present invention described above, in a television receiver that receives video signals of a plurality of signal systems with different frequencies of synchronization signals, regardless of the signal system of the received video signals, the screen of the display means With this, it is possible to display characters in the same display state.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the television receiver according to the present invention, and FIG. 2 is a block diagram showing a specific example of the character signal generation circuit in the television receiver of FIG. 1. 3 and 4 are circuit diagrams showing two specific examples of the oscillation circuit in the character signal generation circuit in FIG. 2, and FIG. 5 is a specific example of the variable delay circuit in the character signal generation circuit in FIG. 2. FIG. 6 is a timing chart for explaining the operation of the variable delay circuit in FIG. 5, FIG. 7 is an explanatory diagram of movement of the character display position, and FIG. It is an explanatory diagram.

(9) is a microcomputer, and (35) is a CRT.

(42) is a character signal generation circuit, (64) is a horizontal position counter, (65) is a vertical position counter, (66) is a vertical synchronization circuit, (67) is a horizontal synchronization circuit, (68) is an oscillation circuit, (70) ) is a data RAM, and (72) is a character ROM.

Claims (1)

[Scope of Claims] A television receiver that receives video signals of a plurality of signal systems having different synchronization signal frequencies, comprising: a determining means for determining the signal system of the received video signal; and a screen of a display means. a character signal generating means for generating a signal of a character to be displayed on the basis of a synchronization signal; and a reference frequency signal generating a reference frequency signal serving as a reference for controlling each display position of the character to be displayed on the screen of the display means. An oscillation circuit, wherein the oscillation frequency of the oscillation circuit is varied according to the discrimination output of the discrimination means.