JPH0425984A - General purpose logical unit - Google Patents

General purpose logical unit

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Publication number
JPH0425984A
JPH0425984A JP13221890A JP13221890A JPH0425984A JP H0425984 A JPH0425984 A JP H0425984A JP 13221890 A JP13221890 A JP 13221890A JP 13221890 A JP13221890 A JP 13221890A JP H0425984 A JPH0425984 A JP H0425984A
Authority
JP
Japan
Prior art keywords
functional element
output
output signal
functional
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13221890A
Other languages
Japanese (ja)
Inventor
Takeo Sato
佐藤 孟生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13221890A priority Critical patent/JPH0425984A/en
Publication of JPH0425984A publication Critical patent/JPH0425984A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To deal with from binary logic to multi-level logic by combining a maximum value selecting functional element, a minimum value selecting functional element, a complementing functional element, a counting functional element, and a comparing functional element. CONSTITUTION:When all the input signals of starting terminal functional elements are 0.0, the output signal 11x, 12x, 13x, 14x, 15x of each starting terminal functional element 11, 12, 13, 14, 15 is 0.0, and similarly, the output signals of the functional elements 16, 17, 18 become 0.0 as well. When the input signal 15a changes from 0.0 to 0.3, the functional element 15 acts as the maximum value selecting functional element, and even if the input signal 15b of the other side is 0.0, the signal 0.3 of a larger side is outputted as the output signal 15x. Similarly, since the input signal 15x of the maximum value selecting functional element 17 changes to 0.3, the output signal 17x changes to 0.3, and further, the output signal 18x too becomes 0.3.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、真・偽の2値論理とともに多値論理をも行
なうことができる汎用論理装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a general-purpose logic device capable of performing multi-value logic as well as binary logic of true and false.

[従来の技術] 近年、機器の高度化にともない、高性能の論理装置の必
要性がますます高まっている。第2図は、このような従
来の論理装置の一例を示すものであり、(1a)、(1
b)、(1c)を入力とする論理積(1)と、(2a)
、(2b)、(2c)および(3a)、(3b)、(3
c)をそれぞれ入力とする論理和(2)および(3)と
が論理積(6)で結合されており、また、(4a)、(
4b)を入力とする論理積(4)と、(5a)、(5b
)を入力とする論理和(5)とが論理和(7)により結
合されている。論理積(6)の出力(6X)と、論理和
(7)の出力(7X)とを入力とする論理和(8)の演
算結果は出力(8x)に出力される。
[Background Art] In recent years, as equipment has become more sophisticated, the need for high-performance logic devices has increased. FIG. 2 shows an example of such a conventional logic device, and shows (1a) and (1
b), logical product (1) with (1c) as input, and (2a)
, (2b), (2c) and (3a), (3b), (3
Logical sums (2) and (3) with c) as inputs are combined by logical product (6), and (4a), (
Logical product (4) with input 4b), (5a), (5b
) is connected by a logical sum (7). The result of the operation of the logical sum (8) using the output (6X) of the logical product (6) and the output (7X) of the logical sum (7) as inputs is outputted to the output (8x).

次に、上記構成の動作について説明する。Next, the operation of the above configuration will be explained.

入力(4a)、(4b)が真の場合、論理積(4)の出
力(4x)が真となり、論理和(7)の入力(4x)が
真となる。従って、論理和(7)の出力(7x)が真と
なるので、論理和(8)の入力(7x)も真となり、論
理和(8)の出力(8X)が真となる。このような演算
経緯を明らかにする操作は、従来、真の値が出されてい
る機能要素(8)、(7)、(4)を示すことにより行
なわれていた。
When inputs (4a) and (4b) are true, the output (4x) of AND (4) is true, and the input (4x) of OR (7) is true. Therefore, since the output (7x) of the logical sum (7) becomes true, the input (7x) of the logical sum (8) also becomes true, and the output (8X) of the logical sum (8) becomes true. Conventionally, operations for clarifying the history of calculations have been carried out by indicating the functional elements (8), (7), and (4) for which the true value has been obtained.

[発明が解決しようとする課題] 従来の汎用論理装置は以上のように構成されているので
、真・偽の2値論理しか扱えず、多値論理ばあつかえな
かった。また、その演算経緯の解釈は、真の出力が得ら
れた機能要素について人為的に機能と対照することによ
り行なう必要があり、操作が複雑で時間がかかるという
問題点があった。
[Problems to be Solved by the Invention] Since the conventional general-purpose logic device is configured as described above, it can only handle binary logic of true and false, and cannot handle multi-valued logic. In addition, the calculation history must be interpreted by artificially comparing the function of the functional element for which the true output has been obtained, which poses the problem of complicated and time-consuming operations.

従って、上記問題点を解消しなければならないという課
題がある。
Therefore, there is a problem that the above problems must be solved.

発明の目的 この発明は上記課題を解決するためになされたもので、
2値論理だけでなく多値論理を扱うことができるととも
に、論理演算の経緯の解釈を効率よく行なうことができ
る汎用論理装置を得ることを目的とする。
Purpose of the invention This invention was made to solve the above problems,
It is an object of the present invention to provide a general-purpose logic device that can handle not only binary logic but also multi-valued logic and can efficiently interpret the history of logical operations.

[課題を角〒決するための手段] この発明にかかる汎用論理装置は、最大値選択機能要素
、最小値選択機能要素、補数機能要素、計数機能要素、
及び比較機能要素のうちの任意の組み合せからなる2値
および多値論理演算機構を備えている。前記各機能要素
の入力および出力にはそれぞれ機能名を対応付け、かつ
、終端機能要素の出力信号と一致する値を出力する前段
の機能要素を終端機能要素側から始端機能要素側に向か
って検索可能に形成し、終端機能要素の出力信号と一致
する値を出力する前記各機能要素の機能名を終端機能要
素側から始端機能要素側に向けて順に出力するものであ
る。
[Means for determining the problem] The general-purpose logic device according to the present invention includes a maximum value selection functional element, a minimum value selection functional element, a complement functional element, a counting functional element,
and a binary and multi-value logic operation mechanism consisting of any combination of comparison functional elements. The input and output of each functional element are associated with a function name, and the preceding functional element that outputs a value that matches the output signal of the terminal functional element is searched from the terminal functional element side to the starting functional element side. The function name of each functional element that outputs a value matching the output signal of the terminal functional element is sequentially output from the terminal functional element side toward the starting functional element side.

[作用] この発明における汎用論理装置は、最小値選択機能要素
、最大値選択機能要素、補数機能要素、計数機能要素、
及び比較機能要素を組合せ、各機能要素の入出力値が0
,0〜1.0を変域とした2値論理から多値論理までを
扱う論理演算をすることができる。
[Operation] The general-purpose logic device according to the present invention includes a minimum value selection functional element, a maximum value selection functional element, a complement functional element, a counting functional element,
and comparison functional elements are combined, and the input/output value of each functional element is 0.
, 0 to 1.0, and can perform logical operations ranging from binary logic to multivalued logic.

また、各機能要素の出力及び始端機能要素の入力信号に
機能名を付与することにより、演算経緯を効率よく解釈
することができる。
Further, by assigning a function name to the output of each functional element and the input signal of the starting functional element, the calculation history can be efficiently interpreted.

[実施例] 以下、この発明の一実施例を図について説明する。第1
図は、この発明による汎用論理装置の論理回路図であり
、(11a)、(1l b)、(11c)を入力とする
最小値選択機能要素(11)と、(12a)、(12b
)、(12C)および(13a)、(13b)、(13
c)をそれぞれ入力とする最大値選択機能要素(12)
および(13)とが最小値選択機能要素(16)で結合
されている。また、(14a)、(1,4b )を入力
とする最小値選択機能要素(14)と、(15a)、(
15b)を入力とする最大値選択機能要素(15)とが
最大値選択機能要素(]7)により結合されている。最
小値選択機能要素(16)の出力(16x)と、最大値
選択機能要素(17)の出力(17x)とを入力とする
最大値選択機能要素(18)の演算結果は出力(18x
)に出力されるように構成されている。上記各機能要素
の人出力値は変域0.0〜1゜Oの間の適当な値をとる
ように構成されている。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a logic circuit diagram of a general-purpose logic device according to the present invention, and includes a minimum value selection functional element (11) whose inputs are (11a), (1l b), and (11c), and (12a) and (12b).
), (12C) and (13a), (13b), (13
Maximum value selection functional element (12) with each input c)
and (13) are coupled by a minimum value selection functional element (16). In addition, a minimum value selection functional element (14) whose inputs are (14a) and (1, 4b), and (15a) and (
15b) is connected to the maximum value selection functional element (15) by the maximum value selection functional element (]7). The calculation result of the maximum value selection function element (18) which inputs the output (16x) of the minimum value selection function element (16) and the output (17x) of the maximum value selection function element (17) is the output (18x).
) is configured to be output. The human output value of each of the above functional elements is configured to take an appropriate value within the range of 0.0 to 1°O.

上記のように各機能要素が組み合わされた状況において
、入力信号が最初に入力される機能要素(11)、(1
2)、(13)、(14)、(15)に対する構成上の
別名を始端機能要素とし、また、最終の出力信号が出力
される最大値選択機能要素(18)に対しては構成上の
別名を終端機能要素と呼ぶことにする。したがって、(
11)は最小値選択機能要素であると同時に、構成上の
別名として始端機能要素と呼ばれる。(11,a)、(
llb)、(1]、c)は最小値選択機能要素(11)
の人力信号、(11x)は同じく出力信号を表わす。そ
のほかの機能要素についても同様である。
In the situation where each functional element is combined as described above, the functional element (11), (1
2), (13), (14), and (15) are the starting end functional element, and the maximum value selection functional element (18) from which the final output signal is output is the structural alias. The other name will be called the terminal functional element. therefore,(
11) is a minimum value selection functional element, and is also called a starting end functional element as another name for its configuration. (11, a), (
llb), (1], c) are minimum value selection functional elements (11)
Similarly, (11x) represents the output signal. The same applies to other functional elements.

(llal)、(11b 1)、(llcl)、(11
1)は、入出力信号に対する機能名であり、各々(11
g)、(’1lb)、(11c)、(11x)の入出力
信号に対応付けられている。以下同様に、(12a)、
(12b)、(13a)、(13b)、  (]、4a
)  、 (14b)、  (15a)、(15b)は
、各々、始端機能要素(12)、(13)、(14)、
(15)に対応する入力信号、(12x)、(13x、
)、(1,4x)、(15x)および(]、 6 x 
)、(]、7x)、(18x)は、各々、機能要素(1
2)、(13)、(14)、(15)、(16)、(1
7)、(18)に対応する出力信号を表わす。また、(
121)、(131)、(141)、(151)、(1
61)、(171)、(181)は各機能構成要素の出
力信号(12x)、(13x)、(14x)、(1,5
x)、(16x)、(17x)、(]、 8 x )に
対応する機能名を表わす。
(llal), (11b 1), (llcl), (11
1) is the function name for the input/output signal, and each (11
g), ('1lb), (11c), and (11x). Similarly, (12a),
(12b), (13a), (13b), (], 4a
), (14b), (15a), and (15b) are the starting end functional elements (12), (13), (14), respectively.
Input signals corresponding to (15), (12x), (13x,
), (1,4x), (15x) and (], 6x
), (], 7x), and (18x) are the functional element (1
2), (13), (14), (15), (16), (1
7) and (18). Also,(
121), (131), (141), (151), (1
61), (171), and (181) are the output signals (12x), (13x), (14x), and (1,5) of each functional component.
x), (16x), (17x), (], 8x).

次に、上記構成の動作について説明する。Next, the operation of the above configuration will be explained.

第1図において、始端機能要素の入力信号(11、a)
、(11b)、(1,1c)、(12a)、(12b)
、(13a)、(13b)、  (1,4a)、(14
,b)、  (15a)、(15b)の値がすべて0.
0の時は、各始端機能要素(11)、(12)、(13
)、(14)、(15)の出力信号(11,x)、(1
2x)、(13x)、(14x)、(15x)は0.0
であり、同様に機能要素(16)、(17)、(18)
の出力信号も0.0となる。
In FIG. 1, the input signal (11, a) of the starting end functional element
, (11b), (1,1c), (12a), (12b)
, (13a), (13b), (1,4a), (14
, b), (15a), and (15b) are all 0.
When it is 0, each start end functional element (11), (12), (13
), (14), (15) output signals (11,x), (1
2x), (13x), (14x), (15x) are 0.0
Similarly, the functional elements (16), (17), (18)
The output signal of is also 0.0.

入力信号(15a)が0.0から0.3に変化した場合
、機能要素(15)は最大値選択機能要素として動作し
、他方の入力信号(15b)が0゜0であっても、出力
信号(15x)には大きい方の信号0.3が出力される
。同様に、最大値選択機能要素(17)の入力信号(1
5x)が0. 3に変化したことにより、出力信号(1
,7x)が0゜3に変化し、さらに出力信号(1,8x
 )も0. 3となる。
When the input signal (15a) changes from 0.0 to 0.3, the functional element (15) operates as a maximum value selection functional element, and even if the other input signal (15b) is 0°0, the output The larger signal 0.3 is output as the signal (15x). Similarly, the input signal (1
5x) is 0. 3, the output signal (1
, 7x) changes to 0°3, and further the output signal (1, 8x
) is also 0. It becomes 3.

そこで、終端機能要素(18)の出力信号(18x)の
値0.3と同一の値が出力されている入出力信号(18
x)、(17x)、(15x)、(15a)に対応する
機能名(181)、(171)(151)、(15al
)を、終端i能要素側から始端機能要素側へ順次出力す
ることにより、上記演算経緯の説明を効率よく行なうこ
とができる。
Therefore, the input/output signal (18
Function names (181), (171) (151), (15al) corresponding to x), (17x), (15x), (15a)
) is sequentially output from the end i-function element side to the start-end function element side, thereby making it possible to efficiently explain the process of the above calculation.

なお、上記実施例では、入出力信号の変域を0゜0〜1
゜0としたが、この変域は負の値であてもよく、任意に
設定することができる。
In the above embodiment, the input/output signal range is 0°0~1.
Although it is set to 0, this range may be a negative value and can be set arbitrarily.

また、使用する機能要素は、最小値選択機能要素と最大
値選択機能要素に限定されることなく、比較機能要素、
補数機能要素、および計数機能要素を含めた2値及び多
値論理演算要素の任意の組合せにより構成することがで
きる。
In addition, the functional elements to be used are not limited to the minimum value selection functional element and the maximum value selection functional element, but also the comparison functional element,
It can be configured by any combination of binary and multi-value logic operation elements including complement function elements and counting function elements.

[発明の効果] 以上のように、この発明の汎用論理装置は、最大値選択
機能要素、最小値選択機能要素、補数機能要素、計数機
能要素及び比較機能要素の任意の組合せを備え、終端機
能要素の出力信号と一致する値を出力する前記各機能要
素の入出力信号に対応付けられた機能名を終端機能要素
側から始端機能要素側に順に出力し、始端機能要素の入
力値から終端機能要素の出力値に至る論理演算の経緯を
説明するようにした構成により、2値論理がら多値論理
までを扱え、かつ、演算経緯の解釈を効率よく行なうこ
とかできる。
[Effects of the Invention] As described above, the general-purpose logic device of the present invention includes any combination of a maximum value selection function element, a minimum value selection function element, a complement function element, a counting function element, and a comparison function element, and has a terminal function. Outputs the function name associated with the input/output signal of each functional element that outputs a value that matches the output signal of the element in order from the end functional element side to the start end functional element side, and outputs the function name corresponding to the input/output signal of each of the above functional elements in order from the end functional element side to the start end functional element side, and outputs the end function from the input value of the start end functional element. With a configuration that explains the history of logical operations leading to the output value of an element, it is possible to handle from binary logic to multivalued logic, and to efficiently interpret the operation history.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明による汎用論理装置の1実施例の論
理回路図、第2図は従来の汎用論理装置の論理回路図で
ある。 図中、(11)、(14)、(]6)は最小値選択機能
要素、(12)、(13)、(15)、(17)、(1
8)は最大値選択機能要素である。 なお、図中同一符号は同一または相当部分を示す。
FIG. 1 is a logic circuit diagram of one embodiment of a general-purpose logic device according to the present invention, and FIG. 2 is a logic circuit diagram of a conventional general-purpose logic device. In the figure, (11), (14), (]6) are minimum value selection functional elements, (12), (13), (15), (17), (1
8) is a maximum value selection functional element. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 最大値選択機能要素、最小値選択機能要素、補数機能要
素、計数機能要素、及び比較機能要素のうちの任意の組
み合せからなる2値および多値論理演算機構を備え、前
記各機能要素の入力および出力にはそれぞれ機能名を対
応付け、かつ、終端機能要素の出力信号と一致する値を
出力する前段の機能要素を終端機能要素側から始端機能
要素側に向かって検索可能に形成し、終端機能要素の出
力信号と一致する値を出力する前記各機能要素の機能名
を終端機能要素側から始端機能要素側に向けて順に出力
することを特徴とする汎用論理装置。
It is equipped with a binary and multi-value logic operation mechanism consisting of any combination of a maximum value selection functional element, a minimum value selection functional element, a complement functional element, a counting functional element, and a comparison functional element; A function name is associated with each output, and the preceding functional element that outputs a value that matches the output signal of the terminal functional element is formed so that it can be searched from the terminal functional element side to the starting functional element side, and the terminal function A general-purpose logic device characterized in that the function name of each of the functional elements that outputs a value that matches the output signal of the element is output in order from the end functional element side to the start end functional element side.
JP13221890A 1990-05-21 1990-05-21 General purpose logical unit Pending JPH0425984A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13221890A JPH0425984A (en) 1990-05-21 1990-05-21 General purpose logical unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13221890A JPH0425984A (en) 1990-05-21 1990-05-21 General purpose logical unit

Publications (1)

Publication Number Publication Date
JPH0425984A true JPH0425984A (en) 1992-01-29

Family

ID=15076151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13221890A Pending JPH0425984A (en) 1990-05-21 1990-05-21 General purpose logical unit

Country Status (1)

Country Link
JP (1) JPH0425984A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6679319B1 (en) * 1998-12-02 2004-01-20 Zexel Valeo Climate Control Corporation Heat exchanger

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6679319B1 (en) * 1998-12-02 2004-01-20 Zexel Valeo Climate Control Corporation Heat exchanger

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