JPH04111019A - Reverse tangent arithmetic circuit - Google Patents

Abstract

PURPOSE:To execute the reverse tangent operation by a practical circuit scale by adding input data to an output of a converting means for outputting a prescribed value to the input data. CONSTITUTION:The circuit is constituted so that a converting means 2 for outputting tan<-1> X-X to input data (X) is provided, and the input data is added to output data of this converting means 2. That is, for instance, in the case an orthogonal coordinate from a reference point is (x, y), the input data (X) of, for instance, 12 bits for showing X = (y/x) is supplied to an input terminal 1. Subsequently, the input data (X) from this input terminal 1 is supplied to a ROM 2 for constituting the converting means, and from this ROM 2, output data (Z) of, for instance, 9 bits is taken out. In such a way, the number of circuits required for the operation is curtailed remarkably, and a reverse tangent operation is executed by a practical circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arctangent calculation circuit used, for example, to generate an arbitrary wipe pattern in a digital image processing device.

[Summary of the invention]

The present invention relates to an arctangent calculation circuit, and includes a conversion means that outputs jan-' This makes it possible to significantly reduce the number of required circuits.

[Conventional technology]

For example, when a so-called wipe process is performed in a digital image processing apparatus, it has been proposed to compress data representing the wipe pattern by representing the wipe pattern in polar coordinates (see Japanese Patent Laid-Open No. 1-280971).

[Problem to be solved by the invention]

However, when using polar coordinates as described above, it is necessary to convert the coordinates given by orthogonal coordinates into distances and angles from the reference point for processing. In this case, distance calculations are relatively easy to perform using square calculations and square root calculations, but angle calculations require arctangent calculations, which cannot be easily realized. That is, when performing an arctangent calculation, for example, if an attempt is made to form this using only logic circuits, an extremely complicated circuit configuration will be required, making it extremely difficult to implement the circuit.

Therefore, conventionally, input data is directly converted into an arctangent value using a memory table (ROM).

However, even when using such a ROM, approximately 20,000 circuits (gates) are required to configure a ROM with, for example, 12 pins for input and 12 bits for output, and it is difficult to incorporate such a large-scale ROM into an IC. It would be extremely difficult to do so, and even if it were possible to do so, there was a risk that the price of the IC would become extremely expensive.

This application was made in view of these points, and is intended to make it possible to realize arctangent calculation with a small number of circuits.

[Means for Solving the Problems] A first means according to the present invention has a conversion means (ROM (2)) that outputs jan-'χ-X for input data (X), and this conversion means This is an arctangent calculation circuit provided with means (addition circuit (4)) for adding the input data to the output data of.

In the second means, the conversion means includes a logic circuit (21) for calculating the upper bits of the output data, and a memory table (ROM (22) for calculating the lower bits of the output data.
) )) The arctangent calculation circuit according to the first means is characterized in that it is comprised of the following.

[Effect]

According to this, jan-' for input data (X)
By providing a conversion means for outputting X −X and adding input data to the output data of this conversion means,
The number of circuits required for calculation is significantly reduced, and arctangent calculation can be performed on a practical circuit scale.

〔Example〕

In Fig. 1, (1) is an input terminal, and for example, when the orthogonal coordinates from the reference point are (x, y), X = (
For example, 12-bit input data (X) representing (y/x) is supplied. Input data (X
) is supplied to the ROM (2) constituting the conversion means, and, for example, 9-bit output data (Z) is taken out from this ROM (2). Three extension bits from the terminal (3) are added to this output data (Z), and the output data (Z) with the extension bits added is supplied to the adder circuit (4). Then, it is added to the input data (X) from the input terminal (1), and output data (Y) of, for example, 12 bits is taken out to the output terminal (5).

In other words, when performing arctangent calculation, the graph of Y=tan to X becomes as shown by the solid line a in FIG. 2. In this figure, the solid line a approximates the Y=X graph already shown as the broken line.

Therefore, from these graphs, the graph of Y = jan-' .

Therefore, in the above circuit, the number of bits of the output data (Z) of ROM (2) can be reduced from the conventional 12 bits to, for example, 9 bits, thereby reducing the number of circuits to approximately 10,000 circuits (gates). I can do it.

As a result, according to the above-mentioned circuit, a conversion means for outputting jan-' ,
The number of circuits required for calculation is significantly reduced, and arctangent calculation can be performed on a practical circuit scale.

Note that in this circuit, the range that can be calculated is 0≦jan-'X<45°, as is clear from the above graph, but the range from 0 to
It is easy to expand to the full 360° range.

Further, FIG. 3 shows an attempt to further reduce the number of circuits (gates) regarding the above-mentioned conversion means (ROM (2)). That is, in this figure, the conversion means (20) is divided into a logic circuit (21) that calculates the upper bits of output data, and a ROM (22) that constitutes a memory table that calculates the lower bits of the output data.

In the above graph, the -dotted chain line C has a gentle slope, and in a curve with such a gentle slope, the upper bits of the output data (Z) do not fluctuate with respect to the input data (X). few.

Therefore, in the case of bits with little variation, it is possible to form a circuit with a smaller number of circuits by calculating the data with a logic circuit rather than storing the data in a ROM.

To explain concrete examples below, Table 1 shows the input data (X), conversion means (ROM
(2)) shows the values of output data (Z) and output data (Y).

In Table 1, the output data (Y) is the sum of the input data (X) and the upper 4 bits of the output data (Z). Therefore, in this Table 1, the output data (Z)
The number of bits required for this is 5 bits, and as mentioned above, it is understood that 3 extension bits of all 0s can be added to the upper 3 bits.

Furthermore, in this Table 1, the 5th bit of the output data (Z) is the above-mentioned X = (0101) and X = (1100
) has a change point, but the interval between them is constant, and the change is gradual with respect to the input data (X).

Therefore, a circuit that can obtain the logic outputs (A+, Az) as shown in Table 2 below is formed, and these logic outputs (A1゜A2
) to the 5th bit data of the output data (Z) (
z4) can be obtained by a simple logic circuit (21).

In other words, in FIG. 4, 4-bit input data (Xo, XI, χ2.X3) supplied to the input terminal (1) is supplied to the output 4-bit ROM (22), and this input Data (X,,X,,X,,X,) is supplied to the logic circuit (21). And this logic circuit (21)
First, the input data (X,,X,) is input to the OR circuit (
31), and this OR output and input data (X)
is supplied to an AND circuit (32), and this AND output and input data (Xi) are supplied to an OR circuit (33) to form a logic output (A1).

Also, the input data (XO, XI) is an OR circuit (34)
This OR output and input data (L, Xi) are supplied to a NAND circuit (35) to form a logic output (A2). And these OR circuits (33
) and the output of the NAND circuit (35) is the AND circuit (36)
5th bit data (Z4) of the output data (Z) is formed.

And 4-bit output data from ROM (22) <
The 1-bit output data (36) from the AND circuit (36) is placed above the
Z4) and 3-bit 0 data (Xs, X-1X7) from the terminal (3) mentioned above are added, and the conversion means (20
) is extracted as the 8-bit data (Z). Furthermore, this output data (Z) is supplied to the adder circuit (4), and the input data (X) from the input terminal (1) is
The added output data (Y) is added to the bit and taken out to the output terminal (5).

Therefore, according to this circuit, the number of output bits of the ROM (22) can be reduced by one bit by simply providing six AND-OR circuits, and the total number of circuits can be significantly reduced.

Further, in Table 1 above, when the fourth and fifth bits of the output data (Z) are obtained by the logic circuit (21), the following procedure is performed. Here, the fifth bit has already been obtained by the circuit described above. On the other hand, the 4th bit data (Z3
) is the logical output (B+, BZ) as shown in Table 3 below.
and 5th bit data (Z4) of output data (Z)
can be obtained from.

Table J- That is, in FIG. 5, 4-bit input data (Xo, Xl+Xi, Xi
) is supplied to the output 3-bit ROM (22), and this input data (XO, X, , XI, Xi) is supplied to the logic circuit (21). And this logic circuit (
21), the input data (XI, X2) is first supplied to the OR circuit (41), and this OR output and the input data (Xi
) is supplied to the OR circuit (42), thereby forming a logic output (B1).

In addition, input data (X o , X + , X z ,
X 3 ) is supplied to the NAND circuit (43), thereby forming a logic output (B2). The outputs of the OR circuit (42) and the NAND circuit (43) are supplied to the AND circuit (44), and the AND output and the 5th bit data (Z4) of the output data (Z) are sent to the inverter (44).
The fourth bit data (Z, ) of the output data (Z) is formed by supplying the signal inverted in step 5) to the AND circuit (46).

Then, the 3-bit output data (
Above the Zo, Z, Zz), an AND circuit (36)
2-bit output data (Zs, Z4) from (46)
and 3-bit 0 data (x
s,xt,.

X? ) is added, and 8-bit data (Z) which is the output of the conversion means (20) is extracted. Furthermore, this output data (Z) is supplied to the adder circuit (4), where the input data (X) from the input terminal (1) is added to the upper 4 bits, and the added output data (Y) is sent to the output terminal ( 5).

Therefore, according to this circuit, the AND-OR circuit is further added to 6
By adding these bits, the number of output bits of the ROM (22) can be further reduced by one bit, and the number of circuits can be significantly reduced.

Further, when three or more bits are formed in the logic circuit (21), the following procedure is performed.

That is, in Table 1 described above, the value of the output data (Z) monotonically increases during a period when the MSB of the input data (X) is 0, and monotonically decreases during a period when the MSB is 1, for example. Therefore, as shown in Figure 6, the logic circuit (21) is divided into a logic circuit (23) that calculates the monotonically increasing part and a logic circuit (24) that calculates the monotonically decreasing part, and the outputs of these are selected. The means (25) selects according to the MSB of input data (X) to obtain output data (Z).

On the other hand, in the above circuit, the circuit that obtains the logic output (A,,B,) changes from O to 1 as the input data (X) increases, and the circuit that obtains the logic output (Az, Bz) changes from input data It changes from 1 to 0 as (X) increases.

Therefore, the former is called an increasing basic circuit, and the latter is called a decreasing basic circuit. In this case, the logic circuit (23) that calculates the monotonically increasing part described above is configured to arbitrarily select the output of the increasing basic circuit. The logic circuit (24) which calculates the monotonically decreasing part is realized by a configuration in which the output of the decreasing basic circuit is arbitrarily selected.

That is, the following Table 4 and FIG. 7 show an example of a logic circuit (23) that calculates a monotonically increasing part when forming a 3-bit output, where the signals (C+, Cz.

C3, Ca, Cs) are each obtained by the above-mentioned incremental basic circuit.

In the figure, the above-mentioned signals (C+, CZ, C3, Ca, Cs) are supplied to the input terminals (51) to (55), respectively, 0 is supplied to the input terminal (50), and 0 is supplied to the input terminal (56). is arbitrarily supplied with a signal. Signals from these input terminals (50) to (56) are applied to switch circuits (60a) to (60d) each consisting of an inverter (61), an AND circuit (62) (63), and an OR circuit (64).
), and the 3-bit output data (Z2.Z3.Z
4) are taken out to output terminals (57) to (59). In addition, in Table 4, the most significant bit (22) of the output data
is the signal (C1) itself, and the second bit (Z,) only needs to select between the signal (C2) and 0 depending on the signal (C1), and by making the same selection for the third bit (Z4), A signal can be obtained, by means of which a logic circuit (23) can be formed which calculates the monotonically increasing part.

Furthermore, the logic circuit (24) for calculating the monotonically decreasing portion is similarly realized by using a switch circuit to arbitrarily select the output of the decreasing basic circuit. Then, signals from these logic circuits (23) (24) can be selected by a selection means (25) according to the MSB of input data (X) to obtain output data (Z).

By the way, when the number of bits of the output data (Z) formed in such a logic circuit (21) is increased, the number of circuits forming this logic circuit (21) increases in a geometric progression.
The number of bits may exceed the number of circuits (gates) of the ROM (22) to be reduced.

Therefore, the output data (
It is necessary to find the optimal value for the number of bits of Z).

In other words, in FIG.
L), in which the signals obtained from each basic circuit are selected by a switch circuit, and these circuits form a logic circuit (23) that calculates a monotonically increasing part and a logic circuit that calculates a monotonically decreasing part. (24), and the signals from these logic circuits (23) and (24) are L.
The output data (Z) is selected according to the MSB of the input data (X) by the selection means (25) consisting of several switch circuits.
) is retrieved.

In this circuit, if the number of basic circuits is all β and the number of switch circuits is all 4, then for example, the circuit required to obtain the most significant bit in the logic circuit (23) that calculates the monotonically increasing part is The number of circuits required to obtain the second bit is β(2°).
22)+4X1, and the number of circuits required to obtain the L-th bit in the same manner is β(2L-')+4 (1+2+...2L-2). Therefore, the sum of these is -2L(β+4)-4L-β-4, and the total of the above circuit is 4L+2x(2L(β+4)-4L-β-4).

On the other hand, the reduced ROM per bit (22)
If the number of times IR (gates) is γ, then the evaluation function J (1
, ) is, for example, J(L)=4 L+2X (2L(β+4)−4L−β
-4) -rL.

For example, if the input of the conversion means (20) is 4 bits and the output is 5 bits, then β=3 and T-36, J (L) = -4OL +14・2L-14, and J'(L )=O, then 40+14 ・2 Lln 2 = 0,', L =
Iogz (40/14 ・In 2) #2.
It becomes 04.

Therefore, in the conversion means (20), the number of bits of the logic circuit (21) is 2 bits, and the number of bits of the ROM (22) is 3 bits.
By using bits, the number of circuits in the conversion means (20) can be minimized.

It is considered that the configuration of the logic circuit (21) described above can be further simplified, and in that case, the optimum value of the number of bits may be 3 to 4.

〔Effect of the invention〕

According to this invention, jan-
By providing a conversion means that outputs 'X
The number of circuits required for calculations has been significantly reduced, making it possible to perform arctangent calculations on a practical circuit scale.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an example of an arctangent calculation circuit according to the present invention,
Fig. 2 is a characteristic diagram for explaining it, Fig. 3 is a block diagram of another example, Fig. 4 is a block diagram of an example of the conversion means, Figs.
7 is a block diagram of another example of the converting means, FIG. 7 is a block diagram of an example of a logic circuit, and FIG. 8 is a block diagram of another example of the logic circuit. (1) is an input terminal, (2) is a ROM, (3) is a terminal, (
4) is an adder circuit, (5) is an output terminal, (20) is a conversion means, (21) is a logic circuit that calculates the upper bits of output data, and (22) is a memory table that calculates the lower bits of output data. (23) is a logic circuit that calculates the monotonically increasing part, (24) is a logic circuit that calculates the monotonically decreasing part, and (25) is a selection means.

Claims (1)

[Scope of Claims] 1. A converting means for outputting tan^-^1X-X for input data (X), and means for adding the input data to the output data of the converting means. Arctangent calculation circuit. 2. The arctangent according to claim 1, wherein the conversion means comprises a logic circuit that calculates the upper bits of the output data and a memory table that calculates the lower bits of the output data. Arithmetic circuit.