JPH04259254A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method for a CMOS semiconductor device having a P-channel MOSFET which has relatively reduced number of steps, no variation in an inverting voltage and a gate electrode of P-type polycrystalline silicon. CONSTITUTION:An N-well 2, a P-well 3, a field oxide film 4, a gate oxide film 5, and a polycrystalline silicon 6 to become a gate electrode are formed on a board 1, and the silicon 6 of an N-well region is selectively doped to a P type. Then, a thermal oxide film 8 and a PSG film 9 are formed on the silicon 6, the film 9', the film 8' and a gate electrode 6' of a polycrystalline silicon film remain on a region to become a gate electrode, and removed, and BF2 is selectively ion implanted to form a P-type source.drain region 12. Then, the film 9' is removed, high concentration N-type impurities are selectively ion implanted, and N-type source.drain region 14 is formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a CMOS semiconductor device, and more particularly to a method of manufacturing a CMOS semiconductor device including a P-channel MOSFET having a gate electrode of P-type polycrystalline silicon.

0002

[Prior Art] In conventional CMOS semiconductor devices, both P-channel and N-channel MOSFETs
It has been common to use N-type polycrystalline silicon for the gate electrode. In this case, in the P-channel MOSFET,
In order to obtain an inversion voltage desirable for circuit operation, a buried channel type is usually used. However, embedded channel devices are prone to punch-through;
It is becoming difficult to respond to the miniaturization of devices.

[0003] For this reason, for example, IEDM technology
Cal Digest, p. 252, 1986, a method has been proposed in which P-type polycrystalline silicon is used for the gate electrode to make the P-channel MOSFET a surface channel type. At this time, N-channel MOSF
Since N-type polycrystalline silicon is used for the gate electrode of ET, to form a P-type polycrystalline silicon gate electrode, after forming a film of polycrystalline silicon, P-type and N-type are separated by a normal photo process and ion implantation process. The impurities are separately implanted, and then the gate electrodes are processed. Using these gate electrodes as masks, source and drain diffusion layers are formed by ion implantation.

0004

[Problems to be Solved by the Invention] However, in this method, P-type and N-type impurities are separately implanted into polycrystalline silicon, and impurities are implanted to form P-type and N-type source/drain diffusion layers. Since a total of four resist pattern forming steps are required for each step, the number of steps is significantly increased compared to the case where a conventional N-type polycrystalline silicon gate electrode is used. In addition, BF2 is used as a dopant for ion implantation of P-type source/drain diffusion layers, especially in micro devices, but when this is also implanted into the gate electrode, in the thermal process for activating the impurities, B
Fluorine contained in F2 promotes the diffusion of boron from polycrystalline silicon in the gate oxide film, and this intrudes into the channel region, resulting in a problem in that the inversion voltage fluctuates.

The present invention has been made to solve the above-mentioned problems in the conventional manufacturing method of CMOS semiconductor devices. An object of the present invention is to provide a method for manufacturing a CMOS semiconductor device including a P-channel MOSFET having an electrode.

[0006]

[Means and Operations for Solving the Problems] In order to solve the above problems, the present invention provides a step of forming a gate oxide film on a semiconductor substrate having a P-type region and an N-type region, and a step of forming a gate oxide film on the gate oxide film. selectively forming a multilayer film with a lower layer made of polycrystalline silicon, and using the multilayer film as a mask, selectively ion-implanting high concentration BF2 into the N-type region to form a P-type source/drain region. selectively removing the upper layer of the multilayer film; and selectively implanting high concentration N-type impurities into the P-type region using the lower layer of the multilayer film as a mask to form an N-type source. - A CMOS semiconductor device is manufactured through a process including a process of forming a drain region.

In this method of manufacturing a CMOS semiconductor device, when forming the N-type source/drain regions, the gate electrode is doped at the same time. No injection process required. Furthermore, when ion-implanting BF2 to form P-type source/drain regions, the upper layer of the multilayer film prevents BF2 from being implanted into the polycrystalline silicon that will become the gate electrode.
Fluctuations in the ET reversal voltage are prevented.

[0008]

[Example] Next, an example will be explained. 1 to 5 are manufacturing process diagrams for explaining a first embodiment of a method for manufacturing a CMOS semiconductor device according to the present invention. First, as shown in FIG. 1, an N well 2, a P well 3, a field oxide film 4, a gate oxide film 5, and polycrystalline silicon 6 which will become a gate electrode are formed on a semiconductor substrate 1. Further, a resist pattern 7 is formed in the P well 3 region, and boron ions are implanted to selectively dope the polycrystalline silicon 6 in the N well 2 region to P type. Next, as shown in FIG. 2, an extremely thin thermal oxide film 8 is formed on the polycrystalline silicon 6, and a PSG (or BPSG) film 9 is further formed on top of the thermal oxide film 8. A resist pattern 10 is formed.

Next, as shown in FIG. 3, a PSG film 9' is etched in the region that will become the gate electrode by reactive ion etching.
After removing the other parts except for the thermal oxide film 8' and the polycrystalline silicon film gate electrode 6', a resist pattern 11 is formed in the region of the P well 3, and BF2 is ion-implanted to form a P-type source. A drain region 12 is formed. At this time,
By injecting BF2 with low acceleration energy,
The PSG film 9' serves as a mask, and BF2 is applied to the gate electrode 6'.
can be prevented from being injected.

Next, as shown in FIG. 4, the PSG film 9' on the gate electrode 6' is selectively removed. At this time, 80℃
The PSG film 9' can be easily selectively removed by a normal cleaning process using a mixture of ammonia and hydrogen peroxide. Subsequently, as shown in FIG. 5, a resist pattern 13 is formed in the region of the N well 2, and arsenic As is ion-implanted to form an N-type source/drain region 14. At this time, since arsenic is also implanted into the gate electrode 6' on the P well 3 through the thin thermal oxide film 8', the gate electrode 6' made of polycrystalline silicon is also doped to be N-type. After that, the CM is processed through the usual interlayer insulating film and wiring layer formation process.
Complete the OS semiconductor device.

In the above embodiment, the case where the present invention was applied to a MOSFET having a single source/drain structure was described, but FIGS. This will be explained using FIG. First, by the same manufacturing process as in the first embodiment shown in FIGS. 1 to 3, a P-type source/drain region 12 is formed in the N well 2 region as in the first embodiment, and then as shown in FIG. , a resist pattern 21 is formed in the N-well 2 region, and low-concentration phosphorus ions are implanted to form N-type low-concentration source/drain regions 22 in the P-well 3 region. Next, as shown in FIG. 7, a silicon oxide film is formed on the entire surface by CVD, and this is etched back to form the sidewall 2.
Remove all but 3. Next, as shown in FIG. 8, after selectively removing the PSG film 9' on the gate electrode 6', a resist pattern 24 is formed on the N well 2, and highly concentrated arsenic is ion-implanted to form an N-type High concentration source/drain region 25
form. At this time, since arsenic is also implanted into the gate electrode 6' on the P well 3, this gate electrode 6' is also doped to be N-type. After that, the CMOS semiconductor device is completed through the usual steps of forming an interlayer insulating film and a wiring layer.

According to each of the embodiments described above, in the ion implantation step of BF2 for forming the P-type source/drain region 12, BF2 is transferred to the gate electrode 6 by the PSG film 9'.
′, no accelerated diffusion of boron due to fluorine occurs, and therefore P-channel MOS
The problem of fluctuations in the inversion voltage of the FET is eliminated, and furthermore, the formation of N-type source/drain regions 14 and 25 and the N-type
Since the doping of the N-type gate electrode 6' is performed at the same time, there is no need to separately form a resist pattern for doping the N-type gate electrode 6'.

[0013]

[Effect of the invention] As explained above based on the embodiments,
According to the present invention, a CMOS semiconductor device including a P-channel MOSFET having a P-type polycrystalline silicon gate electrode having a stable inversion voltage can be easily manufactured with a relatively small number of steps.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a manufacturing process for explaining a first embodiment of a method for manufacturing a CMOS semiconductor device according to the present invention.

FIG. 2 is a diagram showing a manufacturing process following the manufacturing process shown in FIG. 1.

3 is a diagram showing a manufacturing process following the manufacturing process shown in FIG. 2. FIG.

4 is a diagram showing a manufacturing process following the manufacturing process shown in FIG. 3. FIG.

5 is a diagram showing a manufacturing process following the manufacturing process shown in FIG. 4. FIG.

FIG. 6 is a diagram showing a manufacturing process for explaining a second embodiment of the present invention.

7 is a diagram showing a manufacturing process following the manufacturing process shown in FIG. 6. FIG.

8 is a diagram showing a manufacturing process following the manufacturing process shown in FIG. 7. FIG.

[Explanation of symbols]

1 Semiconductor substrate 2 N well 3 P well 4 Field oxide film 5 Gate oxide film 6 Polycrystalline silicon 7 Resist pattern 8 Thermal oxide film 9 PSG film 10 Resist pattern 11 Resist pattern 12 P-type source/drain region 13 Resist pattern 14 N-type source/drain region 21 Resist pattern 22 N-type low concentration source/drain region 23 Sidewall 24 Resist pattern

Claims (3)

[Claims] 1. A step of forming a gate oxide film on a semiconductor substrate having a P-type region and an N-type region, and a step of selectively forming a multilayer film having a lower layer of polycrystalline silicon on the gate oxide film. , a step of selectively ion-implanting high concentration BF2 into the N-type region using the multilayer film as a mask to form a P-type source/drain region; and a step of selectively removing an upper layer of the multilayer film. , a CMOS semiconductor device comprising the step of selectively ion-implanting high concentration N-type impurities into the P-type region using the lower layer of the multilayer film as a mask to form N-type source/drain regions. Production method. 2. A step of forming a gate oxide film on a semiconductor substrate having a P-type region and an N-type region, and a step of selectively forming a multilayer film having a lower layer of polycrystalline silicon on the gate oxide film. , using the multilayer film as a mask, selectively implanting high concentration BF2 into the N-type region to form a P-type source/drain region; and using the multilayer film as a mask, selectively implanting BF2 into the P-type region. a step of ion-implanting low concentration N-type impurities to form N-type low concentration source/drain regions; a step of forming sidewalls in the multilayer film; and a step of selectively removing an upper layer of the multilayer film. , comprising the step of selectively ion-implanting highly concentrated N-type impurities into the P-type region using the lower layer portion and the sidewalls of the multilayer film as masks to form N-type high-concentration source/drain regions. A method for manufacturing a CMOS semiconductor device. 3. At least the uppermost layer of the multilayer film is made of P.
3. The method of manufacturing a CMOS semiconductor device according to claim 1, wherein the film is an SG or BPSG film.