JPH04258173A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a region for merely isolating elements to isolate a lateral DMOS and a vertical DMOS and to reduce the area of a chip even for a lateral DMOS having a small series resistance by isolating a second conductivity type drain region by a first conductivity type region so formed as to reach a first conductivity type semiconductor substrate under a first conductivity type well region. CONSTITUTION:A p-type isolating region 30 for isolating an n-type drain region 12 is so formed as to reach a p-type semiconductor substrate 10 directly under a p-type well region 16. Thus, a vertical DMOS and a lateral DMOS are element-isolated. In the vertical DMOS region, an n<+> type high concentration buried layer 20 is buried in the bottom of an n-type drain region, and an n<+> type high concentration leading region 22 reaching the n-type drain region is formed from the layer 20. This layer 20 becomes a common drain region.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high-power power MOSIC using double-diffused MOS elements. Application fields for high-power power MOSICs include audio output circuits, actuator control circuits such as solenoid control circuits and relay circuits, and motor rotation control circuits, and the demand for them has increased rapidly in recent years. especially,
In the field of automobiles, with the advancement of car electronics, power MOSICs are becoming more popular in actuator control circuits.
demand is increasing. In addition, the frequency of switching power supplies has been increasing in recent years, and power MOSICs have come to be used as power elements.

A power IC, which is an integrated circuit that requires a large current and a large amount of power, is generally composed of a power element portion through which a large current flows and a drive circuit portion that operates with a relatively small current. Since the area of the power element portion increases in proportion to the consumed current, the larger the current power of the power IC, the larger the chip size and the higher the cost. Furthermore, when a plurality of power elements are used, such as in a motor rotation control circuit, an area for separating the elements is required, and the chip size becomes larger. Therefore, a major technical challenge is how to reduce the chip size while maintaining a large current.

0003

2. Description of the Related Art Compared to bipolar transistors, MOS transistors are characterized by being resistant to destruction because current concentration is less likely to occur, and fast switching of large currents since there is no minority carrier accumulation effect. For this reason, it is suitable as a power device for large currents, and is increasingly being integrated into LSIs with other devices.

Since the current capacity of a MOS transistor is proportional to the gate width, an effective method to increase the current capacity per unit area is to miniaturize each MOS transistor and connect a large number of MOS transistors in parallel. . With recent advances in LSI technology, MOS transistors have become smaller, making it possible to manufacture large current power devices.

[0005] In addition to increasing current capacity, the characteristics desired for a large current power device are high breakdown voltage and low on-resistance.
Transistors (DMOS) are often used. A conventional double diffused MOS transistor (DMOS) is shown in FIGS. 4 and 5. FIG. 4 shows a vertical DMOS, and FIG. 5 shows a horizontal DMOS.

As shown in FIG. 4, the vertical DMOS has an n-type drain region 12 formed on a p-type semiconductor substrate 10.
This n-type drain region 12 is separated by a p-type isolation region 14. In the n-type drain region 12, there are a plurality of p
A shaped well region 16 is formed. p-type well region 1
A plurality of n+ type heavily doped source regions 18 are formed within the region 6 . An n+ type high concentration buried layer 20 is buried in the bottom of the n type drain region 12, and from the n+ type high concentration buried layer 20, an n layer reaches the surface of the n type drain region 12.
A + type high concentration extraction region 22 is formed.

FIG. 4 shows two DMOS elements separated left and right by a p-type isolation region 14. In the DMOS on the left, the source electrode S1 is formed to be connected to the n+ type high concentration source region 18 and the p type well region 16, and the drain electrode D1 is formed to be connected to the n+ type high concentration extraction region 22. . The gate electrode G1 is n
It is formed on the p-type well region 16, spanning the +-type high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween. In the DMOS on the right, the source electrode S2 is n
It is formed so as to be connected to the + type high concentration source region 18 and the p type well region 16, and the drain electrode D2 is formed so as to be connected to the n+ type high concentration extraction region 22. The gate electrode G2 is formed on the p-type well region 16, spanning the n+ type high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween.

In the vertical DMOS shown in FIG. 4, the source electrode S1
, S2, electrons flow from the n+ type high concentration source region 18 to the p region under the gate electrodes G1 and G2.
It flows into the n-type drain region 12 through a channel on the surface of the well region 16 . The electrons flowing into the n-type drain region 12 gather in the n+ type heavily doped buried layer 20 and become n+
The drain electrodes D1 and D2 are connected to each other through the high concentration extraction region 22.
Follow the path to reach .

As shown in FIG. 5, the lateral DMOS has an n-type drain region 12 formed on a p-type semiconductor substrate 10.
This n-type drain region 12 is separated by a p-type isolation region 14. In the n-type drain region 12, there is a p-type well region 16, and on the left and right sides of the p-type well region 16, there are n+-type high concentration drain regions 17.
is formed. A plurality of n+ type high concentration source regions 18 are formed within the p type well region 16.

FIG. 5 shows two DMOS elements separated left and right by a p-type isolation region 14. In the DMOS on the left, the source electrode S1 is formed so as to be connected to the n+ type heavily doped source region 18 and the p type well region 16, and the drain electrode D1 is connected to the n+ type heavily doped drain region 1.
7. The gate electrode G1 includes an n+ type high concentration source region 18 and an n type drain region 1.
2 and is formed on the p-type well region 16 with a gate insulating film interposed therebetween. In the DMOS on the right, the source electrode S
2 is an n+ type high concentration source region 18 and a p type well region 1
6, and the drain electrode D2 is connected to n+
It is formed so as to be connected to the heavily doped drain region 17. The gate electrode G2 has an n+ type high concentration source region 18 and an n+ type high concentration source region 18.
The p-type well region 16 is formed over the p-type drain region 12 with a gate insulating film interposed therebetween.

In the lateral DMOS shown in FIG. 5, the source electrode S1
, S2, electrons flow from the n+ type high concentration source region 18 to the p region under the gate electrodes G1 and G2.
It flows into the n-type drain region 12 through a channel on the surface of the well region 16 . The electrons flowing into the n-type drain region 12 follow a path through which the n+-type high concentration drain region 17 reaches the drain electrodes D1 and D2.

0012

[Problems to be Solved by the Invention] As described above, in the conventional vertical DMOS, as shown in FIG.
2, the current path is long and the series resistance is large. To solve this problem, if the size of the n-type drain region 12 of the vertical DMOS is reduced, a large number of them are formed, and they are connected in parallel, the overall series resistance can be reduced, but the chip area is It will increase significantly.

On the other hand, in a lateral DMOS, the current path is short, so the series resistance can be reduced. is required, which increases the chip area. In particular, vertical DMOS and horizontal DMOS
When a plurality of power elements such as the above are integrated, a region is required for separating the elements, resulting in a problem that the chip area becomes larger.

An object of the present invention is to provide a semiconductor device in which a plurality of power elements can be integrated without increasing the chip area.

[0015]

[Means for Solving the Problems] The above object includes a first conductivity type semiconductor substrate, a first second conductivity type drain region formed on the first conductivity type semiconductor substrate, and a second conductivity type drain region formed on the first conductivity type semiconductor substrate. a first well region of the first conductivity type formed on the surface of the drain region of the conductivity type; a first high concentration source region of the second conductivity type formed on the surface of the first well region of the first conductivity type; a first conductivity type isolation region that reaches the first conductivity type semiconductor substrate from below the first conductivity type well region and isolates the first second conductivity type drain region; and the first high concentration second conductivity type isolation region. a first source electrode connected to the first high concentration second conductivity type source region; a first drain electrode connected to the first second conductivity type drain region; a first gate electrode formed on the first well region of the first conductivity type via a first gate insulating film so as to straddle the drain region of the second conductivity type; 1st
a first transistor having a conductivity type semiconductor substrate as a common source region; a second second conductivity type drain region formed on the first conductivity type semiconductor substrate and separated by the first conductivity type isolation region; a second first conductivity type well region formed on the surface of the second second conductivity type drain region; and a second high concentration second conductivity type well region formed on the surface of the second first conductivity type well region. a source region, a high concentration second conductivity type buried region buried in the bottom of the second second conductivity type drain region, and a second second conductivity type drain region from the high concentration second conductivity type buried region to the second second conductivity type drain region; a high concentration second conductivity type lead region reaching the surface, a second source electrode connected to the second high concentration second conductivity type source region, and a second high concentration second conductivity type lead region connected to the high concentration second conductivity type lead region. 2 drain electrode, and the second drain electrode.
is formed on the second first conductivity type well region with a second gate insulating film interposed therebetween so as to straddle the high concentration second conductivity type source region and the second second conductivity type drain region. This is achieved by a semiconductor device characterized in that it has a second gate electrode and a second transistor having the high concentration buried region of the second conductivity type as a common drain region.

[0016]

[Operation] According to the present invention, the drain region of the second conductivity type is separated by the first conductivity type region formed below the first conductivity type well region so as to reach the first conductivity type semiconductor substrate. This eliminates the need for a region solely for element isolation that separates the horizontal DMOS and vertical DMOS, and the chip area can be reduced.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, two vertical DMOSs whose drains are commonly connected are formed on the left side, and two horizontal DMOSs whose sources are commonly connected are formed on the right side. p
An n-type drain region 12 is formed in the entire region on the semiconductor substrate 10 . A plurality of p-type well regions 16 are formed in the n-type drain region 12 of the vertical DMOS formation region on the left, and a plurality of n+ well regions 16 are formed in the p-type well region 16.
A heavily doped source region 18 is formed. In the n-type drain region 12 of the horizontal DMOS formation region on the right side, p-type well regions 16 and n + -type high concentration drain regions 17 are alternately formed.
A + type high concentration source region 18 is formed.

In this embodiment, a p-type isolation region 30 separating the n-type drain region 12 is formed to reach the p-type semiconductor substrate 10 from directly below the p-type well region 16. This p-type isolation region 30 enables vertical DMOS and horizontal DMOS.
S is separated into elements. In the vertical DMOS formation area,
N+ type high concentration buried layer 2 at the bottom of n type drain region 12
0 is buried therein, and an n+ type high concentration extraction region 22 is formed from the n+ type high concentration buried layer 20 to reach the surface of the n type drain region 12. This n+ type heavily doped buried layer 20 serves as a common drain region.

In the vertical DMOS on the left, the source electrode S1
is an n+ type high concentration source region 18 and a p type well region 16
The gate electrode G1 is formed so as to be connected to n+
It is formed on the p-type well region 16, spanning the high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween. In the vertical DMOS on the right, the source electrode S2 is formed to connect to the n+ type high concentration source region 18 and the p type well region 16, and the gate electrode G2 is formed to connect to the n+ type high concentration source region 18 and the n type drain region 12. It is formed on the spanning p-type well region 16 with a gate insulating film interposed therebetween. The drain electrode D1 is common to the left and right vertical DMOSs, and is formed so as to be connected to the n+ type high concentration extraction region 22.

In the lateral DMOS formation region, the p-type semiconductor substrate 10 is connected to the p-type isolation region 30 to form a common source region. Of the two horizontal DMOS elements separated left and right by the p-type isolation region 30, the left horizontal DM
In the OS, a common source electrode S3 is formed to be connected to the n+ type high concentration source region 18 and the p type well region 16, and a drain electrode D3 is formed to be connected to the n+ type high concentration drain region 17. . Gate electrode G3
is an n+ type high concentration source region 18 and an n type drain region 1
2 and is formed on the p-type well region 16 with a gate insulating film interposed therebetween. In the horizontal DMOS on the right, a common source electrode S3 is formed so as to be connected to the n+ type high concentration source region 18 and the p type well region 16, and a drain electrode D4 is formed so as to be connected to the n+ type high concentration drain region 17. has been done. The gate electrode G4 is formed on the p-type well region 16, spanning the n+ type high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween.

As described above, according to this embodiment, since the horizontal DMOS and vertical DMOS are separated by the p-type isolation region 30, there is no need to provide a region only for device isolation, and the chip area can be reduced. can do. In addition, it is possible to integrate horizontal DMOS, vertical DMOS, and other elements, and it is possible to integrate drive circuits and the like with power elements, and it can be manufactured without adding new processes to conventional manufacturing processes. can do.

A specific example of a power MOSIC using a semiconductor device according to an embodiment of the present invention is shown in FIGS. 2 and 3. Figure 2
is the solenoid drive control circuit. A double diffused MOS transistor DM0 is connected in series to the solenoid SL0 on the positive power supply side. The double-diffused MOS transistor DM0 provided on the positive power supply side is called a high-side switch. Double diffused MOS transistors DM1 and DM2 are connected in series to the solenoids SL1 and SL2 on the negative power supply side. The double-diffused MOS transistors DM1 and DM2 provided on the negative power supply side are called low-side switches.

Note that high-side switches are often used in electrical equipment for automobiles. A vertical DMOS whose drains are commonly connected is used for the double diffused MOS transistor DM0, which is a high side switch, and the double diffused MOS transistor DM1, which is a low side switch.
For DM2, a horizontal DMOS whose sources are commonly connected is used. Therefore, it is possible to use a semiconductor device according to an embodiment of the present invention shown in FIG. 1 in which a vertical DMOS and a horizontal DMOS are integrated.

The solenoid SL is controlled by the gate drive circuit GD.
Drive signals to 0, SL1, and SL2 are generated. Double diffused MOS transistor DM, which is a high-side switch
Since it is necessary to apply a higher potential than the source potential to the gate to 0, the drive signal from the gate drive circuit GD is boosted by the booster circuit SC and applied to the gate of the double diffused MOS transistor DM0. Double diffusion type MOS
A drive signal to the gate drive circuit GD is directly input to the gates of the transistors DM1 and DM2. Double-diffused MOS transistors DM0, DM1, and DM2 are turned on and off according to the drive signal generated by the gate drive circuit GD, and the driving of the solenoids SL0, SL1, and SL2 is controlled.

FIG. 3 shows a motor forward/reverse control circuit. The motor MT to be controlled is a double diffusion type MOS connected in series.
It is connected to the midpoint of transistors DM3 and DM4 and to the midpoint of series-connected double diffused MOS transistors DM5 and DM6. Motor M by motor control circuit MD
Control signals are generated to the double diffused MOS transistors DM3, DM4, DM5, DM6.
input into the gate. The double diffusion type MOS transistors DM3 and DM are controlled by the control signal from the motor control circuit MD.
6 is turned on, the motor MT rotates in the forward direction, and when the double diffusion type MOS transistors DM4 and DM5 are turned on by the control signal from the motor control circuit MD, the motor MT is rotated in the reverse direction.

Double diffusion type M of this motor forward/reverse control circuit
The drains of the OS transistors DM3 and DM5 are commonly connected, and a vertical DMOS can be used. The sources of the double diffused MOS transistors DM4 and DM6 are commonly connected, and a horizontal DMOS can be used. Therefore, it is possible to use a semiconductor device according to an embodiment of the present invention shown in FIG. 1 in which a vertical DMOS and a horizontal DMOS are integrated.

The present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, a structure in which the p-type and n-type conductivity types in the above embodiments are exchanged may be used.

[0028]

[Effects of the Invention] As described above, according to the present invention, a vertical DMO
It is possible to integrate S and lateral DMOS without providing a region only for element isolation, and the chip area can be reduced. In addition, the DMO is reduced by the reduction in chip area.
By increasing the number of S cells, a power element that can flow a larger current can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a solenoid drive control circuit using a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a motor forward/reverse control circuit using a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional vertical double-diffused MOS transistor.

FIG. 5 is a diagram showing a conventional lateral double-diffused MOS transistor.

[Explanation of symbols]

10...p-type semiconductor substrate 12...n-type drain region 14...p-type isolation region 16...p-type well region 17...n+ type high concentration drain region 18...n+ type high concentration source region 20...n+ type high concentration buried layer 22... n+ type high concentration extraction region 30...p type isolation regions S1, S2, S3...source electrodes D1, D2, D3, D4...drain electrodes G1, G2, G
2, G4...Gate electrode DM0 to DM6...Double diffused MOS transistor SL0
~SL2... Solenoid GD... Gate drive circuit SC... Boost circuit MT... Motor MD... Motor control circuit

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate, a first second conductivity type drain region formed on the first conductivity type semiconductor substrate, and a first second conductivity type drain region formed on the surface of the first second conductivity type drain region. a first first conductivity type well region; a first high concentration second well region formed on the surface of the first first conductivity type well region;
a conductivity type source region; a first conductivity type isolation region that reaches the first conductivity type semiconductor substrate from below the first conductivity type well region and separates the first conductivity type drain region; a first source electrode connected to the first high concentration second conductivity type source region; a first drain electrode connected to the first second conductivity type drain region; A first well region formed on the first conductivity type well region with a first gate insulating film interposed therebetween so as to span the second conductivity type source region and the first second conductivity type drain region. a first transistor having a gate electrode and using the first conductivity type semiconductor substrate as a common source region; and a first transistor formed on the first conductivity type semiconductor substrate and separated by the first conductivity type isolation region. a second conductivity type drain region; a second first conductivity type well region formed on the surface of the second second conductivity type drain region; and a second first conductivity type well region formed on the surface of the second first conductivity type well region. a second high concentration second conductivity type source region, a high concentration second conductivity type buried region buried in the bottom of the second second conductivity type drain region, and a second high concentration second conductivity type buried region from the high concentration second conductivity type buried region. a high concentration second conductivity type lead region reaching the surface of the second second conductivity type drain region; a second source electrode connected to the second high concentration second conductivity type source region; 2nd conductivity type connected to the draw-out area
a second conductivity type well region on the second first conductivity type well region so as to straddle the second high concentration second conductivity type source region and the second second conductivity type drain region. and a second gate electrode formed through a gate insulating film,
a second transistor having the high concentration second conductivity type buried region as a common drain region.