JPH04258172A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a region for merely isolating elements and to reduce the area of a chip even for a lateral DMOS having a small series resistance by isolating a second conductivity type drain region by a first conductivity type region so formed as to reach a first conductivity type semiconductor substrate under a first conductivity type well region. CONSTITUTION:A p-type isolating region 30 for isolating an n-type drain region 12 is so formed as to reach a p-type semiconductor substrate 10 directly under a p-type well region 16, and the substrate 10 is used as a common source region. Electrons of carrier fed from a common source electrode S flow from an n<+> type high concentration source region 18 to an n-type drain region 12 through a channel on the surface of the region 16 under gate electrodes G1, G2. Electrons flowing into the region 12 are fed in a short current path reaching drain electrodes D1, D2 through an n<+> type high concentration drain region 17.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high-power power MOSIC using double-diffused MOS elements. Application fields for high-power power MOSICs include audio output circuits, actuator control circuits such as solenoid control circuits and relay circuits, and motor rotation control circuits, and the demand for them has increased rapidly in recent years. especially,
In the field of automobiles, with the advancement of car electronics, power MOSICs are becoming more popular in actuator control circuits.
demand is increasing. In addition, the frequency of switching power supplies has been increasing in recent years, and power MOSICs have come to be used as power elements.

A power IC, which is an integrated circuit that requires a large current and a large amount of power, is generally composed of a power element portion through which a large current flows and a drive circuit portion that operates with a relatively small current. Since the area of the power element portion increases in proportion to the consumed current, the larger the current power of the power IC, the larger the chip size and the higher the cost. Therefore, a major technical challenge is how to reduce the chip size while maintaining a large current.

0003

2. Description of the Related Art Compared to bipolar transistors, MOS transistors are characterized by being resistant to destruction because current concentration is less likely to occur, and fast switching of large currents since there is no minority carrier accumulation effect. For this reason, it is suitable as a power device for large currents, and is increasingly being integrated into LSIs with other devices.

Since the current capacity of a MOS transistor is proportional to the gate width, an effective method to increase the current capacity per unit area is to miniaturize each MOS transistor and connect a large number of MOS transistors in parallel. . With recent advances in LSI technology, MOS transistors have become smaller, making it possible to manufacture large current power devices.

[0005] In addition to increasing current capacity, the characteristics desired for a large current power device are high breakdown voltage and low on-resistance.
Transistors (DMOS) are often used. A conventional double diffused MOS transistor (DMOS) is shown in FIGS. 4 and 5. FIG. 4 shows a vertical DMOS, and FIG. 5 shows a horizontal DMOS.

As shown in FIG. 4, the vertical DMOS has an n-type drain region 12 formed on a p-type semiconductor substrate 10.
This n-type drain region 12 is separated by a p-type isolation region 14. In the n-type drain region 12, there are a plurality of p
A shaped well region 16 is formed. p-type well region 1
A plurality of n+ type heavily doped source regions 18 are formed within the region 6 . An n+ type high concentration buried layer 20 is buried in the bottom of the n type drain region 12, and from the n+ type high concentration buried layer 20, an n layer reaches the surface of the n type drain region 12.
A + type high concentration extraction region 22 is formed.

FIG. 4 shows two DMOS elements separated left and right by a p-type isolation region 14. In the DMOS on the left, the source electrode S1 is formed to be connected to the n+ type high concentration source region 18 and the p type well region 16, and the drain electrode D1 is formed to be connected to the n+ type high concentration extraction region 22. . The gate electrode G1 is n
It is formed on the p-type well region 16, spanning the +-type high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween. In the DMOS on the right, the source electrode S2 is n
It is formed so as to be connected to the + type high concentration source region 18 and the p type well region 16, and the drain electrode D2 is formed so as to be connected to the n+ type high concentration extraction region 22. The gate electrode G2 is formed on the p-type well region 16, spanning the n+ type high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween. Vertical DM in Figure 4
In the OS, electrons, which are carriers, flow from the source electrodes S1 and S2 from the n+ type high concentration source region 18 to the n type drain region 12 via the channel on the surface of the p type well region 16 under the gate electrodes G1 and G2. . Electrons flowing into the n-type drain region 12 gather in the n+-type heavily doped buried layer 20, and follow a path to reach the drain electrodes D1 and D2 via the n+-type heavily doped extraction region 22. In the lateral DMOS, as shown in FIG. 5, an n-type drain region 12 is formed on a p-type semiconductor substrate 10, and this n-type drain region 12 is separated by a p-type isolation region 14. A p-type well region 16 is provided within the n-type drain region 12.
N+ type high concentration drain regions 17 are formed on the left and right sides. A plurality of n+ type high concentration source regions 18 are formed within the p type well region 16.

FIG. 5 shows two DMOS elements separated left and right by a p-type isolation region 14. In the DMOS on the left, the source electrode S1 is formed so as to be connected to the n+ type heavily doped source region 18 and the p type well region 16, and the drain electrode D1 is connected to the n+ type heavily doped drain region 1.
7. The gate electrode G1 includes an n+ type high concentration source region 18 and an n type drain region 1.
2 and is formed on the p-type well region 16 with a gate insulating film interposed therebetween. In the DMOS on the right, the source electrode S
2 is an n+ type high concentration source region 18 and a p type well region 1
6, and the drain electrode D2 is connected to n+
It is formed so as to be connected to the heavily doped drain region 17. The gate electrode G2 has an n+ type high concentration source region 18 and an n+ type high concentration source region 18.
The p-type well region 16 is formed over the p-type drain region 12 with a gate insulating film interposed therebetween.

In the lateral DMOS shown in FIG. 5, the source electrode S1
, S2, electrons flow from the n+ type high concentration source region 18 to the p region under the gate electrodes G1 and G2.
It flows into the n-type drain region 12 through a channel on the surface of the well region 16 . The electrons flowing into the n-type drain region 12 follow a path through which the n+-type high concentration drain region 17 reaches the drain electrodes D1 and D2.

0010

[Problems to be Solved by the Invention] As described above, in the conventional vertical DMOS, as shown in FIG.
2, the current path is long and the series resistance is large. To solve this problem, if the size of the n-type drain region 12 of the vertical DMOS is reduced, a large number of them are formed, and they are connected in parallel, the overall series resistance can be reduced, but the chip area is It will increase significantly.

On the other hand, in the lateral DMOS, the current path is short, so the series resistance can be reduced; however, since the n+ type heavily doped drain region 17 is arranged on the surface,
There was a problem that the chip area increased. An object of the present invention is to provide a semiconductor device that can reduce series resistance without increasing chip area.

0012

[Means for Solving the Problems] The above object includes a first conductivity type semiconductor substrate, a second conductivity type drain region formed on the first conductivity type semiconductor substrate, and a second conductivity type drain region formed on the surface of the second conductivity type drain region. a first conductivity type well region formed, a high concentration second conductivity type source region formed on the surface of the first conductivity type well region, and a source electrode connected to the high concentration second conductivity type source region; a drain electrode connected to the second conductivity type drain region; and a gate insulator on the first conductivity type well region so as to straddle the high concentration second conductivity type source region and the second conductivity type drain region. In a semiconductor device having a gate electrode formed through a film, a first conductivity type region reaches the first conductivity type semiconductor substrate from below the first conductivity type well region and separates the second conductivity type drain region. This is achieved by a semiconductor device characterized in that the first conductivity type semiconductor substrate is formed as a common source region.

[0013]

[Operation] According to the present invention, the drain region of the second conductivity type is separated by the first conductivity type region formed below the first conductivity type well region so as to reach the first conductivity type semiconductor substrate. This eliminates the need for a region solely for element isolation, and the chip area can be reduced even in the case of a horizontal DMOS with small series resistance.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, two horizontal DMOSs whose sources are commonly connected are formed on the left side, and an npn bipolar transistor is formed on the right side of the horizontal DMOS. As shown in FIG. 1, the lateral DMOS has a p-type semiconductor substrate 10.
An n-type drain region 12 is formed thereon. In the n-type drain region 12, p-type well regions 16 and n+-type heavily doped drain regions 17 are alternately formed. A plurality of n+ type high concentration source regions 1 are provided in the p type well region 16.
8 is formed.

In this embodiment, the p-type isolation region 30 separating the n-type drain region 12 is formed to reach the p-type semiconductor substrate 10 from directly below the p-type well region 16, and the p-type semiconductor substrate 10 is connected to the common source region. It is distinctive in that it is Of the two horizontal DMOSs separated left and right by the p-type isolation region 30, in the left horizontal DMOS, the source electrode S is formed so as to be connected to the n+ type high concentration source region 18 and the p-type well region 16, A drain electrode D1 is formed to be connected to the n+ type heavily doped drain region 17. The gate electrode G1 is formed on the p-type well region 16, spanning the n+ type high concentration source region 18 and the n-type drain region 12, with a gate insulating film interposed therebetween. In the DMOS on the right, a source electrode S is formed so as to be connected to an n+ type high concentration source region 18 and a p type well region 16, and a drain electrode D2 is formed to connect to an n+ type high concentration drain region 17.
It is formed to connect to. The gate electrode G2 is
n+ type high concentration source region 18 and n type drain region 12
The p-type well region 16 is formed over the p-type well region 16 with a gate insulating film interposed therebetween.

An npn bipolar transistor is formed on the rightmost side of FIG. An n-type collector region 32 separated by a p-type isolation region 30 is formed on the p-type semiconductor substrate 10, and an n+-type high concentration collector region 34 and a p-type base region 36 are formed in the n-type collector region 32. An n + -type heavily doped emitter region 38 is formed within the p-type base region 36 . An n+ type heavily doped buried layer 40 is buried between the n type collector region 32 and the p type semiconductor substrate 10.

The emitter electrode E is formed to be connected to the n+ type high concentration emitter region 38, and the collector electrode C
is formed so as to be connected to the n+ type high concentration collector region 34, and the base electrode B is formed so as to be connected to the p type base region 36. In the horizontal DMOS in Figure 1,
Electrons, which are carriers, flowed from the common source electrode S from the n+ type high concentration source region 18 to the gate electrode G1.
, flows into the n-type drain region 12 through the channel on the surface of the p-type well region 16 under G2. n-type drain region 1
The electrons flowing into the n+ type high concentration drain region 17
The current traces a short current path through which it reaches the drain electrodes D1 and D2.

As described above, according to this embodiment, it is possible to reduce the chip area of a lateral DMOS having a short current path and low series resistance without providing a region only for element isolation. In addition, it is possible to integrate DMOS and other elements, and drive circuits and the like can be integrated with power elements, and can be manufactured without adding new processes to conventional manufacturing processes. .

A specific example of a power MOSIC using a semiconductor device according to an embodiment of the present invention is shown in FIGS. 2 and 3. Figure 2
is the solenoid drive control circuit. Solenoid SL1,
Double diffused MOS transistors DM1 and DM2 are connected in series to SL2, respectively. Gate drive circuit GD
drive signals to the solenoids SL1 and SL2 are generated, and these drive signals are transmitted to the double diffused MOS transistor D.
It is input to the gates of M1 and DM2. Gate drive circuit G
According to the drive signal generated by D, the double-diffusion type MOS
Transistors DM1 and DM2 are turned on and off, and driving of solenoids SL1 and SL2 is controlled.

The sources of the double-diffused MOS transistors DM1 and DM2 of this solenoid drive control circuit are commonly connected, and the semiconductor device according to the embodiment of the present invention shown in FIG. 1 can be used. FIG. 3 shows a motor forward/reverse control circuit. The motor MT to be controlled is connected to the midpoint of double diffused MOS transistors DM3 and DM4 connected in series,
double diffused MOS transistor DM5 connected in series;
It is connected to the midpoint of DM6. Motor control circuit MD
control signals to the motor MT are generated, and these control signals are transmitted to the double diffused MOS transistors DM3, DM4,
It is input to the gates of DM5 and DM6. When the double-diffused MOS transistors DM3 and DM6 are turned on by the control signal from the motor control circuit MD, the motor MT rotates in the forward direction, and the double-diffused MOS transistors DM4 and DM5 are turned on by the control signal from the motor control circuit MD. When turned on, motor MT rotates in the opposite direction.

Double diffusion type M of this motor forward/reverse control circuit
The sources of the OS transistors DM4 and DM6 are commonly connected, and the semiconductor device according to the embodiment of the present invention shown in FIG. 1 can be used. The present invention is not limited to the above embodiments, and various modifications are possible. For example, a structure in which the p-type and n-type conductivity types in the above embodiments are exchanged may be used.

[0022]

As described above, according to the present invention, it is possible to reduce the chip area of a lateral DMOS having a short current path and low series resistance without providing a region solely for element isolation. Furthermore, by increasing the number of DMOS cells by the reduction in chip area, a power element that can flow a larger current can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a solenoid drive control circuit using a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a motor forward/reverse control circuit using a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional vertical double-diffused MOS transistor.

FIG. 5 is a diagram showing a conventional lateral double-diffused MOS transistor.

[Explanation of symbols]

10...p-type semiconductor substrate 12...n-type drain region 14...p-type isolation region 16...p-type well region 17...n+ type high concentration drain region 18...n+ type high concentration source region 20...n+ type high concentration buried layer 22... n+ type high concentration extraction region 30...p type isolation region 32...n type collector region 34...n+ type high concentration collector region 36...p type base region 38...n+ type high concentration emitter region 40...n+ type high concentration buried layer S, S1, S2...Source electrode D, D1, D2...Drain electrode G1, G2...Gate electrode E...Emitter electrode C...Collector electrode B...Base electrode DM1-DM6...Double diffused MOS transistor SL1
, SL2...Solenoid GD...Gate drive circuit MT...Motor MD...Motor control circuit

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate, a second conductivity type drain region formed on the first conductivity type semiconductor substrate, and a first conductivity type drain region formed on the surface of the second conductivity type drain region.
a conductivity type well region, a high concentration second conductivity type source region formed on the surface of the first conductivity type well region, a source electrode connected to the high concentration second conductivity type source region, and the second conductivity type source region. a drain electrode connected to the drain region;
A semiconductor device comprising: a gate electrode formed on the first conductivity type well region with a gate insulating film interposed therebetween so as to straddle the high concentration second conductivity type source region and the second conductivity type drain region; forming a first conductivity type region extending from below the first conductivity type well region to the first conductivity type semiconductor substrate and separating the second conductivity type drain region; and connecting the first conductivity type semiconductor substrate to a common source region. A semiconductor device characterized by: