JPH04256645A - Image forming device - Google Patents

Abstract

PURPOSE:To increase the processing speed of a CPU 1, and make quick response to occurrence of an abnormal state such as jamming. CONSTITUTION:When output of a sensor S1 changes, the output is given to a buffer memory 12 a certain time delayed from the timing at which the output is given to another buffer memory 11, so that a NOR gate 13 connected with the buffer memories 11, 12 can sense the change in the output of sensor S1 at the time the sensor output changes. The NOR gate 13 having sensed the change in the output of the sensor S1 feeds an interrupt signal to the interrupt input terminal (4) of the CPU 1, which checks the condition of the sensor S1. Thus abnormality such as jamming is sensed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus equipped with a sensor and a control means for detecting a change in the state of the sensor.

0002

[Prior Art] Image forming apparatuses such as copying machines are equipped with various sensors, and detection signals from these sensors are used to detect C.
A PU (control unit) detects jamming, the insertion state of a paper feed cassette, and the like.

FIG. 5 shows a conventional example of this type of image forming apparatus, in which a CPU 1 reads a detection signal from a sensor S directly connected to its I/O port, and detects jamming and paper cassette insertion. It has a configuration that detects the state, etc. Figure 6
shows this detection procedure, and the CPU 1 performs step m2.
Prior to the main processing including the image forming process shown in step m1, the sensor input processing shown in step m1 is periodically performed, and here the detection signals of various sensors are read and the above detection is performed.

0004

[Problems to be Solved by the Invention] According to the above detection procedure, as the number of sensors S increases, the time required for reading, that is, the detection, increases accordingly.
processing speed decreases. For this reason, when an abnormal situation such as jamming occurs, a response operation such as stopping the main motor cannot be performed quickly, which places a heavy burden on the equipment and may cause problems such as damage.

Incidentally, in the above-mentioned conventional example, the time for reading the sensor occupies 5% to 10% of the processing time of the CPU 1.

SUMMARY OF THE INVENTION The present invention has been made to solve these drawbacks of the prior art, and aims to provide an image forming apparatus in which the processing speed of the control means can be improved and abnormal situations such as jamming can be quickly dealt with. do.

[0007]

[Means for Solving the Problems] An image forming apparatus of the present invention includes a sensor and a control means for detecting a change in the state of the sensor. first and second buffer memories;
Interrupt signal generation means for monitoring outputs of the first and second buffer memories, and outputting an interrupt signal for causing the control means to execute interrupt processing for checking the state of the sensor when the two outputs are different. The above object is thereby achieved.

Preferably, an initialization circuit is provided that makes data held in the first and second buffer memories match the state detection signal of the sensor when a reset signal is applied to the first and second buffer memories. .

[0009]

[Operation] According to the above configuration, when the sensor output does not change, the outputs latched in the first and second buffer memories are the same, but when the sensor output changes,
Since the changed sensor output is applied to the second buffer memory with a predetermined time delay than the timing at which the changed sensor output is applied to the first buffer memory, the first buffer memory at the time when the changed sensor output is applied to the first buffer memory and the output of the second buffer memory are different. Therefore, every time the sensor output changes, an interrupt signal is generated, and the control means that receives this signal checks the state of the sensor. Therefore, since the state of the sensor is checked only when necessary, the time required to read the sensor output relative to the processing time of the control means can be reduced.

0010

[Examples] Examples of the present invention will be described below.

FIG. 1 shows a sensor state detection circuit installed in the image forming apparatus of the present invention, and the CPU 1 is the control center of the image forming apparatus, and is responsible for main processing including the image forming process and the main processing. Each I/O port of CPU1 (I/O port ■, I/O port ■, I/O port ■)
Sensor input processing is performed to read detection signals from various sensors S1, S2, and S3 (for example, microswitches, phototransistors, and thermistors) connected to the sensor and detect changes in the states of the sensors S1, S2, and S3.

Buffer memories 11 and 12 are connected between sensor S1 and I/O port (2). Further, buffer memories 21 and 22 are connected between the sensor S2 and the I/O port (2), and buffer memories 31 and 32 are connected between the sensor S3 and the I/O port (2), respectively. These buffer memories 11, 12, 21, 22, 31
, 32 are, for example, D flip-flops shown in FIG.

In addition, an N0R gate 13 to which output data of the buffer memories 11 and 12 is applied is connected to the buffer memories 11 and 12. N0R gate 13
consists of an EX-N0R gate, and the buffer memory 11
and 12, and if the two output data are different, an interrupt signal is output to the interrupt input terminal of the CPU 1 via the AND gate 40. The output data of buffer memories 11 and 12 is also sent to the I/O port of CPU1.
given to.

Similarly, in the buffer memories 21 and 22,
A N0R gate 23 for monitoring these output data is connected, and a N0R gate 33 for monitoring these output data is connected to the buffer memories 31 and 32. N
Similarly, the 0R gates 23 and 33 output an interrupt signal to the interrupt input terminal of the CPU 1 via the AND gate 40. Specifically, the AND gate 40 includes at least one N
When an interrupt signal is given from the 0R gate 13 (or 23, 33), the interrupt signal is input to the interrupt input terminal of the CPU 1, and the CPU 1 that receives the interrupt signal executes sensor input processing (interrupt processing routine) to be described later.

FIG. 2 shows the details of the buffer memories 11 and 12 and the parts connected to them, and shows ON and OFF signals (hereinafter the ON signal is referred to as a high level signal "H") from the sensor S1 consisting of a microswitch. , the OFF signal is referred to as a low level signal “L”) is the buffer memory 11.
is applied to data input D of . On the other hand, buffer memory 1
A clock (clock pulse) is inputted to the clock input terminal CLK of No. 1 from the clock pulse generator 5 at a predetermined period. The buffer memory 11 reads and stores data from the sensor S1 at the rising edge of the clock input to the clock input terminal CLK, holds the data until the rising edge of the next clock, and buffers the held data from the data output Q. Data input D of memory 12 and N0R gate 1
Output to one terminal of 3.

Similarly, the buffer memory 12 holds and holds the data applied to the data input D from the buffer memory 11 from the rising edge of the clock applied to the clock input terminal CLK from the clock generator 5 until the rising edge of the next clock. Data is outputted from the data output Q to the I/O port (2) and the other terminal of the AND gate 40. Therefore, according to this embodiment, delayed data for two clock cycles is output to the I/O port (2) of the CPU1.

In addition, an initialization circuit 6 comprising OR gates 60, 61, 62 and an inverter 63 is connected to the buffer memories 11 and 12. When the data stored in the buffer memories 11 and 12 is cleared immediately after the power is turned on to the image forming apparatus, the initialization circuit 6 converts the data stored in the buffer memories 11 and 12 into the current state of the sensor S1 ("H"). ” or “L”) to prevent false detection from occurring. To explain a little now, the reset input CLR of buffer memories 11 and 12
When a reset signal is applied from the reset signal generation circuit 64, the initialization circuit 6 takes a predetermined logic based on the state signal of the sensor S1 at this time applied to one terminal of the OR gate 60, and outputs the buffer memories 11 and 12. Data corresponding to the state of the sensor S1 at the relevant time point is set in the set input PR of the sensor S1.

FIG. 3 shows the specific operation contents of the sensor state detection circuit described above, in which the sensor S1 changes from "L" to "H".
". Then, "H" state data is input to the data input D of the buffer memory 11, and the buffer memory 11 holds this "H" state data until the rise of the next clock. Therefore, at this time, an "H" state signal is input to one terminal of the N0R gate 13.

On the other hand, at this point, the buffer memory 12
Since data in the "H" state is not input to the data input D of the buffer memory 12, the buffer memory 12 holds data in the "L" state as shown. Therefore, at this time, an "L" state signal is input to the other terminal of the N0R gate 13. Here, the N0R gate 13 outputs an "H" state signal when there is no change in the state of the sensor S1. Therefore, when the state of sensor S1 changes from "L" to "H" as described above, at that point a signal of "H" state is input to one terminal and "L" state signal is input to the other terminal. The output of the N0R gate 13 changes from “H” to “L”
”, and this “L” state signal is input to the interrupt input terminal (2) of the CPU 1 via the AND gate 40 as an interrupt signal.

When an interrupt signal is input to the interrupt input terminal ■ from at least one N0R gate 13 (or 23, 33) via the AND gate 40, the CPU 1 interrupts the main processing currently being processed, as shown in FIG. The processing program is interrupted and interrupt processing, that is, sensor input processing is executed. In this sensor input processing, I/O ports ■, ■, ■
Check the status of. This check detects jamming and paper cassette insertion.

According to the above detection method, the processing speed of the CPU 1 can be improved by approximately 5% to 10% compared to the conventional method. In other words, jamming and paper cassette insertion detection do not occur very often, and according to the above detection method, it is only necessary to detect when these situations occur, so the CPU 1 is 5% to 1 of processing time
Processing speed increased by 5% compared to the conventional method that used 0%
It can be improved by ~10%.

Note that in the above embodiment, the AND gate 40
It was decided to give the outputs of N0R gates 13, 23, and 33 to the interrupt input terminal You may also choose to provide a configuration. However, since the number of interrupt input terminals is limited relative to the number of sensors, it is preferable to provide the AND gate 40 in terms of implementation.

[0023]

[Effects of the Invention] According to the present invention, each time the sensor output changes, the control means that receives the interrupt signal checks the state of the sensor, so that when it is necessary to check the state of the sensor, only. Therefore, the time required to read the sensor output relative to the processing time of the control means can be significantly reduced, and the processing speed of the control means can be improved.

[0024] Therefore, abnormal situations such as jamming can be quickly dealt with, so problems such as damage do not occur, and
Restoration work can be carried out reliably.

In particular, according to the image forming apparatus according to claim 2, when a reset signal is applied to the first and second buffer memories, the data held in the first and second buffer memories is transferred to the sensor. Since the configuration is provided with an initialization circuit that matches the state detection signal, even if the data held in the first and second buffer memories is cleared, such as immediately after the image forming apparatus is powered on, errors will not occur. No detection occurs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a general configuration of a sensor state detection circuit installed in an image forming apparatus of the present invention.

FIG. 2 is a circuit diagram showing in detail a part of the sensor state detection circuit shown in FIG. 1;

FIG. 3 is a drawing showing a specific operation of the circuit shown in FIG. 2;

FIG. 4 is a flowchart showing a CPU control procedure.

FIG. 5 is a drawing showing a circuit configuration of a conventional example.

FIG. 6 is a flowchart showing a CPU control procedure in a conventional example.

[Explanation of symbols]

1 CPU 5 Clock generator 6 Initialization circuit 11, 12, 21, 22, 31, 32 Buffer memory 13, 23, 33 N0R gate 40 AND gate S1, S2, S3 Sensor

Claims (2)

[Claims] Claims: 1. An image forming apparatus comprising a sensor and a control means for detecting a change in the state of the sensor, comprising first and second buffer memories connected between the sensor and the control means; interrupt signal generating means for monitoring the outputs of the first and second buffer memories and outputting an interrupt signal for causing the control means to execute interrupt processing for checking the state of the sensor when the two outputs are different; Image forming device equipped with 2. An initialization circuit that matches data held in the first and second buffer memories with a state detection signal of the sensor when a reset signal is applied to the first and second buffer memories. The image forming apparatus according to claim 1.