JPH04256058A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate time when a reading processing is not executed at the time of continuously executing a data read request. CONSTITUTION:A latch means 12 is provided between a micro program storage part 10 and a data read means 13 reading data from a memory 16 in accordance with the instruction of a micro program. When the next data read request is received at the time of reading data in a data read means, the latch means holds the data read request and the data read means immediately processes the held data read request after the previous read processing terminates.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus that uses a microprogram when successively reading a plurality of data.

0002

[Prior Art] Today, in general information processing devices,
Microprograms are used for various processes. This microprogram is a microprocessor program created using microinstructions that are instructions for basic computer operations.

FIG. 2 is a block diagram of an information processing device using a conventional microprogram. The illustrated device includes a microprogram storage section 1, a microprogram decoding section 2, a data read request holding flip-flop 3, a read data holding flip-flop 4, a memory 5, and a data calculation section 6. The microprogram storage section 1 is comprised of a read-only memory or random access memory, and stores a predetermined microprogram. The microprogram decoding unit 2 is
This is a decoder that reads a microprogram, decodes it, and determines whether there is a data read request. The data read request holding flip-flop 3 is a flip-flop that holds data read requests and types, and
Read data holding flip-flop 4 is a flip-flop that holds data read from memory 5. The memory 5 consists of random access memory, etc.
Data read by the microprogram is stored. The data calculation unit 6 is composed of an arithmetic circuit that performs calculations using the contents of the data held in the read data holding flip-flop 4.

Next, the operation of the information processing apparatus having the above configuration will be explained. First, when a data read request is received from an external device (not shown), a microprogram instruction is read from the microprogram storage section 1, and the microprogram decoding section 2 decodes it. If this command is a data read request as described above, the information is set in the data read request holding flip-flop 3 and data read processing is performed. Data reading from memory 5 is completed,
After the read data is set in the read data holding flip-flop 4, the data read request holding flip-flop 3 is reset and the data read state is released.

FIGS. 3 and 4 show a flow chart and a time chart of a microprogram that performs such continuous data reading. First, in step S1, a first data read request is made and a wait is made. Here, waiting refers to a command to wait for the next process after a certain data read request is issued until the read request is completed. That is, this is a command to wait for execution of the next step until data is stored in the read data holding flip-flop 4. Further, the process of step S1 corresponds to the operation at times T1 to T3 in the time chart of FIG. That is, at time T1, the first
Upon receiving the read request, the data read request holding flip-flop 3 is set at time T2, and then, when the processing of the first data read request is completed at time T3, the data read request holding flip-flop 3 is reset,
The read data holding flip-flop 4 is set. Also, from time T2 to time T3, there is a waiting state.

Next, since the processing of the first data read request has been completed, the first data is retrieved from time T3, a second data read request is received, and the data read request holding flip-flop 3 is activated at time T4. set. That is, the setting is performed in the next cycle of the clock. Then, at time T5, the data read request holding flip-flop 3 is reset, and the read data holding flip-flop 4 is set, and from time T4 to T5.
Until then, it will be in a waiting state. Incidentally, the read data holding flip-flop 4 is reset at the timing when data extraction is completed. The above is the process of step S2 in FIG. After that, the i-1st data is retrieved, the i-th data read request is made, and the waiting state (step S3) is performed.
, . . . performs retrieval of the (n-1)th data, requests to read the nth data, and waits (step S4);
Finally, the n-th data is retrieved (step S5),
Ends data read request processing.

[0007]

However, in the above-mentioned conventional information processing device, the data read request holding flip-flop 3 must be fixed during the data read processing period. , a new data read request could not be received. That is, to explain with reference to FIG. 4, for example, while the first data read request is being processed (times T2 to T3), the second data read request cannot be issued because it is in a waiting state. Therefore, the second data read request can be issued in the next cycle (after time T4) after the first data read process is completed. Therefore, when performing continuous data reading, as shown at times T3 to T4, etc., there is one cycle of time during which no reading processing is performed between processing of each data reading request, which is longer than the actual data reading processing time. The problem is that it takes a lot of time.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object of the present invention is to provide an information processing device that can shorten the processing time when continuously making data read requests. do.

[0009]

[Means for Solving the Problems] An information processing device of the present invention is an information processing device that performs data processing using a microprogram. a memory for storing data; a data reading means for reading data from the memory according to instructions of a microprogram stored in the microprogram storage; and a data reading means provided between the microprogram storage and the data reading means; When the data reading means receives a next data reading request while the data reading means is executing data reading, the data reading means is provided with a latch means for holding this data reading request.

0010

[Operation] The device of the present invention provides a latch means between the microprogram storage section and the data reading means for reading data from the memory according to the instructions of the microprogram,
When the data reading means receives the next data reading request while executing data reading, the latch means holds the data reading request, and the data reading means reads out the held data after the previous reading process is completed. Process the request immediately. Therefore, when data read requests are made continuously, there is no time during which read processing is not performed, and the data read processing time can be shortened.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention. The illustrated device includes a microprogram storage section 10, a microprogram decoding section 11, a next data read request holding latch means 12, a data read request holding flip-flop 14 and a read data holding flip-flop 15 constituting the data reading means 13.
, a memory 16 , and a data calculation section 17 . In these configurations, the microprogram storage section 10, the microprogram decoding section 11, the memory 16, and the data calculation section 17 are different from the conventional microprogram storage section 1,
Since it has the same configuration as the microprogram decoding section 2, memory 5, and data calculation section 6, detailed explanation in this section will be omitted.

FIG. 5 shows a concrete block diagram of the above information processing apparatus. That is, the next data read request holding latch means 12 is constituted by a D latch circuit, and the data read request holding flip-flop 14 and read data holding flip-flop 15 are constituted by D flip-flops. The control circuit 18 also includes RS flip-flops 19 and 2.
Consists of 0. The output of the microprogram decoder 11 is input to the set terminal of the flip-flop 19, and the output of the AND circuit 21 is input to the reset terminal. A signal 22 and an output signal of the flip-flop 20 are input to the input of the AND circuit 21 via an inverter 23. Here, the signal 22 is the memory 1
6 to the read data holding flip-flop 15 is a signal indicating that the data is valid. The output terminal Q of the flip-flop 19 is connected to the input of an AND circuit 24 and also connected to an OR circuit 26 via an inverter 25.
is connected to the input terminal of The output of the microprogram decoder 11 is input to the other input terminal of the AND circuit 24, and the output is connected to the set terminal of the flip-flop 20. Further, a signal 22 is input to the reset terminal of the flip-flop 20. The output of the flip-flop 20 is input to the AND circuit 21 via the inverter 23 and also to the AND circuit 27 as described above. A clock is input to the other input of the AND circuit 27, and its output is the latch circuit 1.
It is input to the control input G of No. 2. In addition, the OR circuit 26
A signal 22 is input to the other input of the circuit, and its output is input to a NAND circuit 28. A clock is input to the other input of the NAND circuit 28, and the output is input to the clock terminal of the data read request holding flip-flop 14. Further, the clock terminal of the read data holding flip-flop 15 is input with the output of the NAND circuit 29 into which the signal 22 and the clock signal are input. Furthermore, a memory 16 is connected to the D input of the read data holding flip-flop 15.
The output Q is connected to the input terminal of the data calculation section 17.

Next, the operation of the information processing apparatus having the above configuration will be explained. Figure 6 is a flowchart of the operation, Figure 7
The time charts for each part are shown below. First, when a data read request is made, a first data read request is taken out from the microprogram storage section 10, decoded by the microprogram decode section 11, and held in the data read request holding flip-flop 14. At this time, the latch circuit 12 is in an open state, and the data read request is sent as is to the flip-flop 14 (step S11).
. Next, the second data read request is taken out from the microprogram storage section 10, similarly decoded by the microprogram decoding section 11, and held in the latch circuit 12, again entering a waiting state (step S12). Then, when the processing of the first data request is completed, the second data read request held in the latch circuit 12 is held in the flip-flop 14, and processing for the second data read request is performed (step S13)
.

That is, the RS flip-flop 1 shown in FIG.
9, when one or more read requests are received and being processed, the output Q becomes high level, and the RS flip-flop 2
In the case of 0, when two read requests are received and are being processed, the output Q becomes high level. Therefore, the clock control signal (c) of the AND circuit 27 connected to the control input G of the latch circuit 12 becomes low level from time T2 to T4. As a result, the contents held by the latch circuit 12 hold the second data read request during the first data read process, as shown in FIG. 7(j). Note that ■ to ■ in FIG. 7 indicate the first to fourth data read instructions, and (1) and (2) indicate the first and second read data. Furthermore, (a) to ((
i) corresponds to signals (a) to (i) in FIG.

Further, the condition that the clock control signal (e) of the NAND circuit 28 connected to the clock input CK of the flip-flop 14 becomes low level is that during the read process (
This is the case when the output Q of the flip-flop 19 is at high level) or the signal 22(g) is at low level. Therefore, the clock control signal (e) becomes low level at times T1 to T3 as shown in FIG. 7E, and the flip-flop 14 holds the first data read request at times T1 to T4. Since the clock control signal (h) of the NAND circuit 29 connected to the input terminal is the signal 22, it becomes high level at time T3 as shown in FIG.
The data (f) from 6 to flip-flop 15 is at time T.
3, and data transmission (i) from the flip-flop 15 to the data calculation unit 17 is performed from time T4.

In this way, the first data processing is performed at time T1.
~T4, and the second data read process is performed at time T4.
will be carried out immediately. Therefore, after that, the i-2nd data retrieval, the i-th data read request, and the waiting state (
Step S14), retrieving the n-2nd data, processing the n-th data read request and waiting state (step S15), then retrieving the n-1st data and waiting (step S16), and retrieving the n-th data (step S17). ) to complete the data read process. As described above, in the above embodiment, the next read process is immediately performed when consecutive data read requests are made, and a cycle in which no read process is performed does not occur.

[0017] In the above embodiment, the case where there is one latch circuit 12 has been described, but the number is not limited to this, and the same effect can be achieved even when a plurality of latch circuits are provided. Further, although the control circuit 18 is constructed using an RS flip-flop, it can also be constructed using a D flip-flop and a predetermined combination circuit.

[0018]

As explained above, according to the information processing apparatus of the present invention, when data read requests are made continuously using a microprogram, data read processing and reception of other data read requests can be performed. Since the latch means is used to simultaneously perform the processing, successive data read requests can be processed without any interval, and it is therefore possible to expect an improvement in the processing speed of the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing device of the present invention.

FIG. 2 is a block diagram of a conventional information processing device.

FIG. 3 is a flowchart showing the operation of a conventional information processing device.

FIG. 4 is a time chart showing the operation of a conventional information processing device.

FIG. 5 is a detailed block diagram of the information processing device of the present invention.

FIG. 6 is a flowchart showing the operation of the information processing apparatus of the present invention.

FIG. 7 is a time chart showing the operation of the information processing device of the present invention.

[Explanation of symbols]

10 Microprogram storage section 12 Next data read request holding latch means 1213
Data reading means 16 Memory 17 Data calculation section

Claims (1)

[Claims] 1. An information processing device that performs data processing using a microprogram, comprising: a microprogram storage unit that stores a microprogram; a memory that stores data read by the microprogram; and a memory that stores data read by the microprogram. a data reading means for reading data from the memory according to instructions of a microprogram that has been read; and a data reading means provided between the microprogram storage section and the data reading means, when the data reading means is executing data reading. , and latch means for holding the next data read request when the next data read request is received.