JPH04253249A - Data transfer device - Google Patents

Abstract

PURPOSE:To collect fault information and to execute fault analysis without interrupting a processing under execution at another channel when a fault is generated. CONSTITUTION:When the fault is generated at a unit 0, the processing of data transfer executed between a peripheral controller 3 and a main storage device not shown in the figure is stopped, and a transfer control circuit 20 detecting the fault loads interruption to a firmware executing means 26 and sets the contents of the detected fault to a fault information identification flag means 21. The firmware executing means 26 informs the fault generation of a unit control circuit 32 and successively instructs a select circuit 25 so as to store the control information of a control register group 24 in the case of the fault generation in a memory 27. Units 1-3 also successively store the control information of respective control registers in own memories 35, 41 and 51. The firmware executing means 26 reads fault information identification flag means 21, 34, 40 and 50, edits the information into the readable form of a firmware executing means 12 and sets it to a channel device fault flag 23. Afterwards, the fault state is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention is utilized for data transfer between a main storage device and a peripheral control device. The present invention relates to a data transfer device that can collect detailed failure information at high speed. 2. Description of the Related Art FIG. 2 is a block diagram showing the configuration of a conventional data transfer device. A conventional data transfer device is composed of a channel control device 1 and a channel device 2',
The channel control device 1 is controlled by a firmware execution means 12 and includes a channel device control circuit 11 that controls an interface with a plurality of channel devices 2', and a data buffer 10 that controls read data and write data. The channel device 2' also includes a data buffer 62 for controlling read data and write data.
, a transfer control circuit 60 that controls transfer with the channel control device 1 and operation instructions from the channel device control circuit 11, an interrupt control circuit 61 that controls interrupts to the channel control device 1, and It includes a control register group 63 that stores the status and information necessary for transfer, and a selection circuit 64 that selects the contents of the control register group 63 in response to a control information selection instruction from the firmware execution means 12. Each control circuit of the channel device 2' has a function of verifying a fault and issuing an interrupt to the interrupt control circuit 61. However, a signal line for interrupting the interrupt control circuit 61 is omitted in FIG. [0005] If a failure occurs in the channel device 2',
The transfer control circuit 60 that has detected the failure issues an interrupt to the interrupt control circuit 61 . The interrupt control circuit 61 notifies the channel device control circuit 11 via the interface signal line 200 that a failure has occurred. When the channel device control circuit 11 is notified of the occurrence of a failure, it interrupts the firmware execution means 12 and determines a failure handling routine. The firmware execution means 12 sequentially gives instructions to select the control register group 63 via the interface signal line 201. The selection circuit 64 sequentially selects the control register group 63 and transfers it to the firmware execution means 12 via the interface signal line 202. [0007] As described above, the conventional device is controlled so that it cannot collect anything other than failure information from registers that can be read from the firmware execution means 12, so the amount of information is small. Furthermore, when collecting fault information other than readable registers, the entire channel control device is occupied before collecting the fault information. [0008] The above-mentioned conventional fault information transfer method has limitations because it is controlled so that only fault information in registers that can be read from the firmware execution means of the channel control device can be collected. It is not possible to perform a sufficient fault analysis with only the fault information provided, and if detailed fault information of a channel device is required, detailed fault information cannot be collected unless the entire channel control device to which the channel device is connected is occupied. Since it is in control, it has the disadvantage that all processes being executed on other channels must be interrupted. [0009] The present invention solves these problems, and aims to provide a device that can collect necessary failure information and perform failure analysis without interrupting processes being executed on other channels. purpose. [0010] The present invention comprises a channel control device connected to a main storage device and controlling data transfer, and a plurality of channel devices connected to a peripheral control device controlling data transfer. , the channel control device includes a firmware execution unit that executes firmware, a channel device control circuit that controls an interface between the plurality of channel devices, and a data buffer that temporarily stores data; , a transfer control circuit that controls data transfer according to operation instructions from the channel control device, an interrupt control circuit that controls interrupts to the channel control device, a data buffer that temporarily stores data, and a plurality of buffers that store control information. In the data transfer device, the channel device includes a control register group configured of control registers, and a selection circuit that selects control information stored in the control register group. The first unit includes the transfer control circuit, interrupt control circuit, data buffer, control register group, and selection circuit, and second firmware execution means for controlling the own unit;
Selecting a memory that stores the control information selected by the selection circuit as fault information and controls read processing based on the read address and transfer byte count given from the firmware execution means, and information from this memory or the peripheral control device. and a fault information identification flag means for setting and transmitting a flag indicating the type of fault when a fault occurs in the own unit; , the control register group, firmware execution means, memory,
and a fault information identification flag means; a third selection circuit that selects control information stored in the control register group; and a third selection circuit that controls data transfer according to an operation instruction from the first unit; and a unit control circuit that controls an instruction to complete storage of fault information to the unit. The firmware execution means of the first unit includes:
reading a flag from the fault information identification flag means;
It is preferable to include means for editing the channel device failure flag and sending it to the channel control device, and the second unit can be composed of a plurality of units. [Operation] When a failure occurs in any of the units constituting the channel device, the control information in the control register group is saved as failure information in the memory of each unit, and a channel device failure flag is created. Each control circuit of a channel device that has become inoperable due to a failure is once reset to an operable state. At the same time, the channel control device determines the channel device fault flag from the channel device, confirms the content of the fault, reads only necessary information, and transfers the fault information to the main storage device using the same method as normal data transfer. 0
[012] Thereby, only the necessary fault information can be read out and collected at high speed without interrupting the processing being executed on other channels. [Embodiment] Next, an embodiment of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The embodiment of the present invention includes a channel control device 1 that is connected to a main storage device (not shown) and controls data transfer, and a plurality of channel devices 2 that are connected to a peripheral control device 3 and control data transfer. A channel control device 1 includes a firmware execution means 12 for executing firmware, a channel device control circuit 11 for controlling an interface between a plurality of channel devices 2, and a data buffer 10 for temporarily storing data. 2 is composed of a first unit 0 and a plurality of second units 1, 2, and 3, and the first unit 0 is a transfer control circuit 2 that controls data transfer according to operation instructions from the channel control device 1.
0, an interrupt control circuit 22 for controlling interrupts to the channel control device 1, a data buffer 29 for temporarily storing data, a control register group 24 composed of a plurality of control registers for storing control information, and a control register group 24 for controlling interrupts. Selection circuit 2 that selects control information stored in register group 24
5, and firmware execution means 2 that controls the own unit.
6, a memory 27 that stores the control information selected by the selection circuit 25 as failure information and controls the read process based on the read address and transfer byte count given from the firmware execution means 26; and this memory 27 or the peripheral control device 3. a selection circuit 28 that selects information from the unit and stores it in the data buffer 29; and a failure information identification flag means 21 that sets the type of failure in a flag and sends it when a failure occurs in its own unit; The unit 1 includes a control register group 30, a firmware execution means 33, a memory 35, and a failure information identification flag means 3.
4, a selection circuit 31 that selects control information stored in the control register group 30, and a selection circuit 31 that controls data transfer according to operation instructions from the first unit 0 and instructs the first unit 0 to complete storage of failure information. A unit control circuit 32 that controls
The second units 2 and 3 have fault information identification flag means 40 and 50, memories 41 and 51, and other components included in the first unit 0, respectively. The firmware execution means 26 of the first unit 0 includes means for reading the flag from the fault information identification flag means 21, editing it into a channel device fault flag 23, and sending it to the channel control device 1. , consists of multiple units. In this embodiment, in order to simplify the explanation, entries other than the fault information identification flags 40, 50 and memories 41, 51 are omitted from the second units 2 and 3 in FIG. Processing and operations for transferring fault information are performed in the same way as in unit 1. Each of the control circuits of units 0, 1, 2, and 3 has a function of detecting a fault and interrupting the firmware execution means of its own unit, and setting the content of the detected fault to the fault information identification flag of its own unit. After the firmware of the units 1 to n is notified of the function and the reset instruction from the firmware execution means 26, the firmware has a function of resetting each control circuit of its own unit. In FIG. 1, a signal line for interrupting the firmware execution means, a signal line for setting a fault information identification flag, and a signal line for the firmware execution means to reset each control circuit are omitted. Next, the operation of the embodiment of the present invention constructed as described above will be explained. When a failure occurs in the unit 0, the data transfer process being performed between the peripheral control device 3 and the main storage device (not shown) is stopped, and the transfer control circuit 20 that has detected the failure executes the firmware execution means 26. and sets the details of the detected failure in the failure information identification flag means 21 (signal lines are omitted in FIG. 1). The firmware execution means 26 notifies the unit control circuit 32 via the data path 118 that a failure has occurred. The firmware execution means 26 also controls the control register group 2 when a failure occurs.
In order to store the control information of No. 4 in the memory 27 as failure information, all control register numbers are sequentially instructed to the selection circuit 25 via the selection instruction signal line 106. The fault information selected by the control register number is taken into the internal register of the firmware execution means 26 via the data path 110.
The unit 0 fault information storage area (addresses 0000-0FFF) of the memory 27 is sequentially stored through the memory 27 via the memory 27. On the other hand, in the unit 1, when data transfer is being performed between the peripheral control device 3 and the main storage device due to a fault occurrence notification from the firmware execution means 26, the processing is stopped, and the unit control circuit 32 transfers data to the data path 120.
The firmware execution means 33 is interrupted via the . The firmware execution means 33 is issued a failure handling routine by this interrupt, and sequentially transfers all control register numbers to the selection circuit 31 via the selection instruction signal line 108. The fault information selected by this control register number is taken into the internal register of the firmware execution means 33 via the data path 127 and sequentially stored in the memory 35 via the data path 121. The failure occurrence notification from the firmware execution means 26 is also notified to the units 2 and 3. With this notification, units 2 and 3, like unit 1, sequentially store the control information in the control register in their own memories 41 and 51. Firmware execution means 33 of unit 1
When the information of all control registers is stored in the memory 35,
The unit control circuit 32 is notified via the data path 120 of the completion of storing the fault information. The unit control circuit 32 is
This notification notifies the firmware execution means 26 via the data path 118 of the completion of storing the fault information. When the firmware execution means 26 detects the failure information storage completion notification from the units 1, 2, and 3 and the failure information storage completion of the unit 0, the firmware execution means 26 detects the failure information identification flag means 21, 34 of the units 0, 1, 2, and 3. 40 and 50 are read via data paths 113 , 119 , 123 , and 125 , respectively, and edited into a format readable by firmware execution means 12 . The edited result is set in the channel device fault flag 23 via the data path 111, and the completion of channel device fault flag creation is notified to the interrupt control circuit 22 via the data path 112. When the flag creation is completed, the firmware execution means 26 executes the data bus 1 in order to reset the failure state of the channel device that has become inoperable due to the occurrence of a failure.
18 to notify the unit control circuit 32 of the unit 1 reset instruction. In response to this reset instruction, the unit control circuit 32 interrupts the firmware execution means 33 via the data path 120 and issues a failure state reset processing routine. [0026] The firmware execution means 33 stores the memory 3
Reset the control circuits other than 5, and reset the data path 120,
Completion of unit 1 reset is notified to firmware execution means 26 via unit control circuit 32 and data path 118. Similarly, the firmware execution means 26
Units 2 and 3 are also notified of the unit 2 reset instruction and unit 3 reset instruction, respectively. In response to this notification, the firmware execution means of units 2 and 3 reset the control circuits other than the memory 41 and memory 51, and notify the firmware execution means 26 of completion of unit 2 reset and completion of unit 3 reset, respectively. On the other hand, in the unit 0, the firmware execution means 26 resets the memory 27 and the control circuits other than the channel device failure flag 23. When the reset of unit 0 is completed, the firmware execution means 26 checks the notification factors from units 1, 2, and 3, and if the reset completion is notified, the firmware execution means 26 executes the
In order to store the fault information of the memories 35, 41, and 51 of Nos. 2 and 3 in the memory 27, a fault information movement instruction is notified to the unit control circuit of each unit. Upon receiving this notification via data path 118, unit control circuit 32
The fault information movement instruction is notified to the firmware execution means 33 via. In response to this notification, the firmware execution means 33 reads out all the fault information stored in the memory 35 via the data path 121 .
0, the unit control circuit 32, and the firmware execution means 26 via the data path 118. The firmware execution means 26 stores the read failure information in the unit 1 failure information storage area (addresses 1000-1FFF) of the memory 27 via the data path 116. The fault information movement instruction from the firmware execution means 26 is also notified to the unit 2 and unit 3, and similarly to the unit 1, the fault information stored in the memory 41 is transferred to the unit 2 fault information storage area of the memory 27 ( 2000-2FFF address),
The fault information stored in the memory 51 is also stored in the unit 3 fault information storage area (addresses 3000-3FFF) of the memory 27. The fault information of each unit is moved to the memory 27, and when the storage is completed, the firmware execution means 26 moves the fault information of each unit to the memory 27.
12 to notify the interrupt control circuit 22 of the completion of the failure information movement. When the interrupt control circuit 22 detects the channel device failure flag creation completion notification and failure information movement completion from the firmware execution means 26, it interrupts the channel device control circuit 11 via the interface signal line 102. The channel device control circuit 11 interrupts the firmware execution means 12 via the data path 109 in response to an interrupt from the channel device 2. This interrupt causes the firmware execution means 12 to read the channel device fault flag 23 via the interface signal line 103 and determine the type of fault. Based on this determination, a control table prepared in advance (a table that associates the type of failure, the read address of the memory of the channel device, and the byte count of the failure information to be transferred) is stored in the memory of the channel device 2. Create a read address and transfer byte count to read fault information. Firmware execution means 12 provides the created read address and transfer byte count to channel device control circuit 11 via data path 109 . The channel device control circuit 11 sends a read address (for example, reading from address "0500"), a transfer byte count (for example, "2048" byte transfer), and a fault to the transfer control circuit 20 via the interface signal line 101. Notify information transfer start instruction. The transfer control circuit 20 interrupts the firmware execution means 26 via the data path 114 in response to this fault information transfer start instruction, and issues a fault information transfer processing routine. The firmware execution means 26 reads the read address and the transfer byte count from the transfer control circuit 20 via the data path 114, and reads the read address and transfer byte count from the transfer control circuit 20 via the data path 114, and reads the read address and transfer byte count from the memory 2 via the data path 116.
7 is given an address (“0500”) and a transfer byte count (“2048”), and an instruction to select the memory 27 is given to the selection circuit 28 via the selection instruction signal line 107. The memory 27 stores data from address “0500” to “2”.
The read fault information is transferred to the transfer control circuit 20 via the data buffer 29 and the data path 115 in the same manner as normal data transfer, and is further transferred to the interface signal line. 100, and is transferred to the main memory device via the interface signal line 104. [Effects of the Invention] As explained above, according to the present invention, a channel device is configured. If a failure occurs in any of the units, the control information in the control register group is saved as failure information in the memory of each unit, a channel device failure flag is created, and each control of the channel device that has become inoperable due to the failure is By once resetting the circuit (excluding the channel device fault flag and memory), the channel device can be made operational, and by the channel control device determining the channel device fault flag and knowing the details of the fault,
Only the necessary information can be read from the channel device. Furthermore, by transferring fault information to the read main memory using the same method as normal data transfer, it is possible to store a large amount of detailed fault information saved in the memory of each unit without occupying the entire channel control device. It has the effect of being able to collect data quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional example.

[Explanation of symbols]

1 Channel control device 2, 2' Channel device 3 Peripheral control device 10, 29, 62 Data buffer 11
Channel device control circuit 12, 26, 33 Firmware execution means 20
, 60 Transfer control circuit 21, 34, 40, 50 Fault information identification flag means 22, 61 Interrupt control circuit 23 Channel device fault flag 24, 30, 63 Control register group 25, 28,
31, 64 selection circuit 27, 35, 41, 51
Memory (unit 0) 32 Unit control circuit

Claims (3)

[Claims] 1. A channel control device connected to a main storage device to control data transfer, and a plurality of channel devices connected to a peripheral control device to control data transfer, wherein firmware is executed on the channel control device. firmware execution means, a channel device control circuit that controls an interface between the plurality of channel devices, and a data buffer that temporarily stores data; a control register group consisting of a transfer control circuit for controlling transfer, an interrupt control circuit for controlling interrupts to the channel control device, a data buffer for temporarily storing data, and a plurality of control registers for storing control information; , and a selection circuit that selects control information stored in the control register group, wherein the channel device includes a first unit and a second unit, and the first unit includes: storing the transfer control circuit, the interrupt control circuit, the data buffer, the control register group, the selection circuit, a second firmware execution means for controlling the own unit, and the control information selected by the selection circuit as fault information; a memory that controls read processing based on a read address and a transfer byte count given from the firmware execution means; a second selection circuit that selects information from this memory or the peripheral control device and stores it in the data buffer; and a self-unit unit. and a fault information identification flag means for setting and transmitting a flag indicating the type of fault when a fault occurs in the system, and the second unit includes the control register group, firmware execution means, memory, and fault information identification flag means. a flag means; a third selection circuit for selecting control information stored in the control register group; and a third selection circuit for controlling data transfer according to an operation instruction from the first unit, and providing fault information to the first unit. A data transfer device comprising: a unit control circuit that controls a storage completion instruction. 2. The firmware execution means of the first unit includes means for reading the flag from the fault information identification flag means, editing it into a channel device fault flag, and sending it to the channel control device. data transfer equipment. 3. The data transfer device according to claim 1, wherein the second unit is composed of a plurality of units.