JPH0425176A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0425176A JPH0425176A JP2129767A JP12976790A JPH0425176A JP H0425176 A JPH0425176 A JP H0425176A JP 2129767 A JP2129767 A JP 2129767A JP 12976790 A JP12976790 A JP 12976790A JP H0425176 A JPH0425176 A JP H0425176A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- impurities
- silicon
- type
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 239000012535 impurity Substances 0.000 claims abstract description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052786 argon Inorganic materials 0.000 claims abstract description 7
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 7
- 239000011737 fluorine Substances 0.000 claims abstract description 7
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000005234 chemical deposition Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052796 boron Inorganic materials 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a semiconductor device.
Ｐ型Ｍ■Ｓトランジスタのゲート電極としてＰ型不純物
から成る多結晶シリコンを使う場合、ボロン等のＰ型不
純物を多結晶シリコンに導入する前に、チッ素、フッ素
、アルゴン、シリコン、ゲルマニウム等の何れか１つ又
は複数の不純物をイオン注入あるいは化学的堆積法によ
り多結晶シリコン中へ導入しておく。When using polycrystalline silicon made of P-type impurities as the gate electrode of a P-type M■S transistor, before introducing P-type impurities such as boron into the polycrystalline silicon, nitrogen, fluorine, argon, silicon, germanium, etc. One or more impurities are introduced into polycrystalline silicon by ion implantation or chemical deposition.
多結晶シリコン中へこれらの不純物を導入すると、多結
晶シリコン中へＰ型不純物を導入した後、Ｍ Ｔ Ｓ
ｌ−ランジスタ形成までに経る熱工程による多結晶シリ
コンのダレインの成長が抑制される。When these impurities are introduced into polycrystalline silicon, after introducing P-type impurities into polycrystalline silicon, MTS
The growth of polycrystalline silicon dalein due to the thermal process required to form the l-transistor is suppressed.
この結果、多結晶シリコン中のダレインに沿うＰ型不純
物の拡散が抑制され、Ｐ型不純物がＭＴＳトランジスタ
の絶縁膜を通過し、シリコン表面にまで達することが抑
制される。その結果、スレッショルド電圧の変動、１−
ランジスタ特性の不安定性のないＰ型不純物を導入した
多結晶シリコンをゲート電極として持つＰ型ＭＩＳトラ
ンジスタを得ることができる。As a result, the diffusion of the P-type impurity along the dale in the polycrystalline silicon is suppressed, and the P-type impurity is suppressed from passing through the insulating film of the MTS transistor and reaching the silicon surface. As a result, the threshold voltage variation, 1-
A P-type MIS transistor having a gate electrode made of polycrystalline silicon into which P-type impurities are introduced without causing instability in transistor characteristics can be obtained.
［１１ｆ−来の技術〕
［）型不純物をノリ人した多結晶シリＪＪンをＭＩＳト
ランジスタのり−Ｉ・電極として使う場合、従来、多結
晶シリコン中・・、■）型不純物（最も一般的にはポ「
Ｊン）をイ」ン注入又は化学的堆積法で導入していた。[11f - Current technology] When using polycrystalline silicon containing [) type impurities as an MIS transistor glue/electrode, conventionally, polycrystalline silicon containing..., ■) type impurities (most commonly is po'
J) was introduced by ion implantation or chemical deposition.
導入後、Ｍ 、Ｉ Ｓ ｌ−ランジスタが形成されるま
でに複数回の熱二「程を経る。それらの熱工程により多
結晶シリコンのグレインは成長し、大きいもの６，１１
ミク１．−Ｉン稈度にまで成長する。After introduction, multiple thermal cycles are required to form the M,I S l-transistor.Through these thermal processes, the polycrystalline silicon grains grow, and large grains6,11
Miku 1. -Grows to culm size.
第２図はＩｉＡ来のＰ型不純物から成る多結晶シリンを
う−ｌ−電（彼とずろｌｖｌ Ｉ Ｓ ｌ・ランノスク
の最ａ３的な熱１−程を経た後の断面＋１１１造を示す
。２１はＮ型Ｔ勇体シリ−１ン基板、２２ｉ；Ｉケ−１
・酸化膜、２３はう一−ｌ−電極となる多結晶シリコン
膜、２４は多結晶シリコンのグレイン、２５の大い線は
グＬツインの境界を示′づ。グレインが非常に大きく成
長しているのか分かる。多結晶シリ１：１ン中・＼導入
された不純物Ｇ；１、クリ？工程により拡散する場合、
多く １，１グレインの境界２５に沿っ、て拡ｉＢ４
シていく。タレ・インか大きくなればなる程、グ［／イ
ンの境界１−１短い距翻［て多結晶シリコンの１−面か
ら下面に到達し、不純物の多結晶シリコン中での拡ｊ１
９．が容易となる。Figure 2 shows a cross section of polycrystalline silane made of P-type impurities from IiA after it has been subjected to the most a3 heat treatment. 21 is an N type T body series 1 board, 22i; I case 1
・An oxide film, 23 is a polycrystalline silicon film serving as another L-electrode, 24 is a grain of polycrystalline silicon, and a large line 25 indicates the boundary of the G-L twin. It can be seen that the grains have grown very large. In polycrystalline silicon 1:1 \Introduced impurity G; 1, clear? If it is diffused due to the process,
Many 1,1 grains along the boundary 25, expanded iB4
I'm going to go. The larger the slope becomes, the shorter the distance between the boundary 1-1 of the slope and the lower surface of the polycrystalline silicon.
9. becomes easier.
又、ＭＩＳＩ・ランシスクの代表的な構造である全屈・
酸化膜、半導体（ＭＯＳ）ｌ−ランジスタの場合、ボロ
ンは酸化膜中ても拡散し、ゲート電極となる多結晶シリ
コン中にあるＰ型不純物のボロンは酸化膜を通過し、第
２図におりるシリコン表面２６にまで容易に到達する。In addition, full flexion, which is a typical structure of MISI/Lansisk,
In the case of an oxide film, semiconductor (MOS) l-transistor, boron diffuses into the oxide film, and boron, which is a P-type impurity in the polycrystalline silicon that serves as the gate electrode, passes through the oxide film, as shown in Figure 2. easily reaches the silicon surface 26.
その結果、スレノショルｌ電圧が変動し易い、あるいは
不安定なｌ−ランジスタ特性を持つＭＩＳ）ランシスタ
になるという欠点を持っていた。As a result, the MIS transistor has the drawback that the threshold voltage easily fluctuates or has unstable l-transistor characteristics.
前記した従来の欠点を改善するため、Ｐ型不純物のボｌ
Ｊンが多結晶シリコン中で容易に拡散しないように、本
発明はＭＩＳＩ・ランジスタが形成されるまでに経る多
くの熱工程によっても多結晶シリコンのグし・インの成
長を抑制することを目的としたものである。以下、図面
を参照し、本発明の詳細な説明する。In order to improve the above-mentioned conventional drawbacks, the volume of P-type impurity
The purpose of the present invention is to suppress the growth of nitrogen in polycrystalline silicon even during the many thermal processes that go through before MISI transistors are formed, so that silicon does not easily diffuse into polycrystalline silicon. That is. Hereinafter, the present invention will be described in detail with reference to the drawings.
Ｍ［Ｓ］・フンシスタのり”−１・電極となる多結晶ソ
リ丁ｌンにＰ型不純物をイオン注入あるいは化学的１１
１積法により多結晶シリコンに導入する前に、チッ素、
フッ４８、アルゴン、シリコン、ケルマニ・：Ｊ Ｊ、
、雪の不純物の何れか１つ又は複数の不純物をイオン注
入又は化学的ｌｌＩ積法により多結晶ンリコン中−２ｍ
入する。P-type impurity is ion-implanted or chemically applied to the polycrystalline silicate that will become the electrode.
Before introducing nitrogen into polycrystalline silicon using the one product method,
Fu48, argon, silicon, kermani: J J,
, one or more of snow impurities is added to polycrystalline silicon by ion implantation or chemical III product method.
Enter.
ＭＩＳＩ・ランシスタか形成されるまで経る多くの熱に
稈によっても、それらの不純物を多結晶シリニＪン中・
＼！ｎ大することにより、多結晶シリコン中のグレイン
の成長を抑制することかできる。その結果、多結晶シリ
′：１ン中てのＰ型不純物ボロンの拡散を抑制し、史に
りｍ＝１・絶縁膜中をｊｍ過してＭＩＳＩ・ランシスタ
のチャネル領域へのボロンの侵入をＩＶｊ ＜ごとかて
きる。The culm undergoes a lot of heat to form MISI and lancista, and these impurities are removed from the polycrystalline silicone.
\! By increasing n, the growth of grains in polycrystalline silicon can be suppressed. As a result, the diffusion of P-type impurity boron in polycrystalline silicon':1 is suppressed, and boron is prevented from penetrating into the channel region of MISI/Lancistor through m = 1 insulating film. IVj ＜ is written.
第１図（・」）〜（（：）に、本発明の３１′導体装置
の製造方法の実施例を示す。第１図（ｉ］）において１
１は半導体、／す′１ンノ１（］反、１２ Ｌｅｔツノ
−１・絶８イｌ模となる熱酸化■榮、１３はケート電極
となる多結晶シリコン膜を表わす。Fig. 1(・'') to ((:) show an embodiment of the method for manufacturing a 31' conductor device of the present invention. In Fig. 1(i), 1
Reference numeral 1 represents a semiconductor, 12 represents a thermal oxidation process that becomes an absolute model, and 13 represents a polycrystalline silicon film that becomes a gate electrode.
まず多結晶ンリコン膜１３中へ窒素１４のイオン注入を
行う。イオン注入直後の窒素の分布が、ゲート酸化膜１
２やシリコン基板１１には達しないようにする。次に第
１図（ｂｌに示すように、多結晶シリコンゲート電極を
Ｐ型化するため、ボロン１５をイオン注入する。更に、
第１図（Ｃ１に示すように〕第１・リソグラフィ工程に
より多結晶シリコンの一部をエツチングし、ゲート電極
１６が形成する。First, ions of nitrogen 14 are implanted into the polycrystalline silicon film 13. The distribution of nitrogen immediately after ion implantation is similar to that of gate oxide film 1.
2 and the silicon substrate 11. Next, as shown in FIG. 1 (bl), boron 15 is ion-implanted to make the polycrystalline silicon gate electrode P-type.Furthermore,
In FIG. 1 (as shown in C1), a part of the polycrystalline silicon is etched by a first lithography step, and a gate electrode 16 is formed.
なお、多結晶シリコン中ヘボロンをイオン注入する前に
、イオン注入又は化学的堆積法で多結晶シリコン中へ導
入する不純物は、前記した窒素以外にフッ素、アルゴン
、シリコン、ゲルマニウム等の何れか又はそれらの複数
の組み合ねゼでも良い。Before ion-implanting Heboron into polycrystalline silicon, the impurity introduced into polycrystalline silicon by ion implantation or chemical deposition may be fluorine, argon, silicon, germanium, etc., or any of them in addition to the nitrogen mentioned above. It may be a combination of multiple.
ボロンのイオン注入１１１Ｊ、多結晶シリコン中に窒素
、フッ素、アルゴン等の不純物を導入すると、それらの
不純物を導入しない場合におけるグレイン２４（第２図
）に比べ、１−ランジスタ形成までに終わる熱工程によ
る多結晶シリコンのグレイン１７（第１図）の成長は抑
えられる。グレインＩ７が小さいと、不純物の多結晶シ
リコンの拡散は抑えられる。このため、窒素やフッ素を
ホロンのイオン注入前に多結晶シリコン中へ導入してお
くと、熱工程による多結晶シリコン中のボロンの拡散が
抑えられ、ひいてはゲート絶縁膜中を通過し、Ｐ型Ｍ
Ｉ Ｓ ＋−ランジスタのチャネル領域（第Ｊ図ＦＣ）
１８）へのボ１−ｚンの拡散が抑制される。Boron ion implantation 111J, when impurities such as nitrogen, fluorine, and argon are introduced into polycrystalline silicon, the thermal process ends before the formation of 1-transistor, compared to the grain 24 (Fig. 2) when these impurities are not introduced. The growth of polycrystalline silicon grains 17 (FIG. 1) due to the oxidation is suppressed. If the grain I7 is small, diffusion of impurity polycrystalline silicon can be suppressed. Therefore, if nitrogen or fluorine is introduced into polycrystalline silicon before holon ion implantation, the diffusion of boron in polycrystalline silicon due to the thermal process will be suppressed, and the boron will pass through the gate insulating film and become P-type. M
Channel region of I S +- transistor (Figure J FC)
18), the diffusion of balls 1-z to 18) is suppressed.
以上、詳細に説明したように、本発明の半導体装置の製
造方法においては、熱工程による多結晶ノリコンのグレ
イン成長を抑え、ボロンの多結晶シリコン中の拡１）ｋ
を卯え、その結果、ボロンのゲ１箱オ子）膜中“（の拡
散も（…え、ＭＩＳトランジスタのヂ→・ネル領域への
侵入を防く効果を有する。As described above in detail, in the method of manufacturing a semiconductor device of the present invention, grain growth of polycrystalline silicon due to a thermal process is suppressed, and boron is expanded in polycrystalline silicon.
As a result, the diffusion of boron into the film also has the effect of preventing its intrusion into the genus region of the MIS transistor.
このため、スレソショルト電圧の変動が少ない、しかも
安定な！・ランジスタ特性を持つ、Ｐ型不純物から成る
多結晶シリコンをゲート電極として持つＩ）型ＭＩＳＩ
〜ランシスタを得ることができる多大な効果を持ってい
る。For this reason, there is little fluctuation in the threshold voltage, and it is stable!・I) type MISI that has transistor characteristics and has polycrystalline silicon made of P-type impurities as a gate electrode
~Rancista can be obtained and has a great effect.
第１図ｆａ）〜（Ｃ１は本発明の半導体装置の製造方法
を示す工程順断面図、第２図は従来の半導体装置の１析
面図である。
半導体基板
ゲート絶縁膜
多結晶シリコン
チッ素イオン注入
ボロンイオン注入
グレイン
以
」二Figures 1 (fa) to (C1) are step-by-step cross-sectional views showing the method of manufacturing a semiconductor device of the present invention, and Figure 2 is a cross-sectional view of a conventional semiconductor device. Semiconductor substrate Gate insulating film Polycrystalline silicon nitride Ion-implanted boron ion-implanted grain
Claims (1)
トランジスタ）のゲート電極をＰ型不純物を導入した多
結晶シリコンで形成する半導体装置の形成方法において
、Ｐ型不純物をイオン注入あるいは化学的堆積法により
多結晶シリコンに導入する前に、チッ素、フッ素、アル
ゴン、シリコン、ゲルマニウム等の不純物の何れか１つ
又は複数の不純物をイオン注入又は化学的堆積法により
多結晶シリコン中へ導入することを特徴とする半導体装
置の製造方法。(1) In a method for forming a semiconductor device in which the gate electrode of a P-type MIS transistor (metal/insulating film/semiconductor transistor) is formed of polycrystalline silicon doped with P-type impurities, the P-type impurity is ion-implanted or chemically deposited. Before introducing into polycrystalline silicon, one or more impurities such as nitrogen, fluorine, argon, silicon, germanium, etc. are introduced into polycrystalline silicon by ion implantation or chemical deposition method. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2129767A JPH0425176A (en) | 1990-05-18 | 1990-05-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2129767A JPH0425176A (en) | 1990-05-18 | 1990-05-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425176A true JPH0425176A (en) | 1992-01-28 |
Family
ID=15017704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2129767A Pending JPH0425176A (en) | 1990-05-18 | 1990-05-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425176A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07226510A (en) * | 1993-10-28 | 1995-08-22 | Lg Semicon Co Ltd | Doping of semiconductor polysilicon layer and manufacture of pmosfet using this |
| WO1998013880A1 (en) * | 1996-09-25 | 1998-04-02 | Advanced Micro Devices, Inc. | POLY-Si/POLY-SiGe GATE FOR CMOS DEVICES |
| EP0859402A2 (en) * | 1997-01-21 | 1998-08-19 | Texas Instruments Incorporated | Method of manufacturing a MOS electrode |
| US5866930A (en) * | 1995-08-25 | 1999-02-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5901084A (en) * | 1997-03-10 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device having floating gate electrode |
| US6300664B1 (en) | 1993-09-02 | 2001-10-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
| US6720626B1 (en) | 1998-01-26 | 2004-04-13 | Renesas Technology Corp. | Semiconductor device having improved gate structure |
| US6744104B1 (en) | 1998-11-17 | 2004-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit including insulated gate field effect transistor and method of manufacturing the same |
| WO2008078363A1 (en) * | 2006-12-22 | 2008-07-03 | Renesas Technology Corp. | Process for producing semiconductor device and semiconductor device |
| JP2008218661A (en) * | 2007-03-02 | 2008-09-18 | Fujitsu Ltd | Field-effect semiconductor device and manufacturing method therefor |
| JP2009010417A (en) * | 2008-09-05 | 2009-01-15 | Renesas Technology Corp | Manufacturing method of semiconductor device |
| JP2011029661A (en) * | 1993-09-02 | 2011-02-10 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
-
1990
- 1990-05-18 JP JP2129767A patent/JPH0425176A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300664B1 (en) | 1993-09-02 | 2001-10-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
| JP2011029661A (en) * | 1993-09-02 | 2011-02-10 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
| US6521527B1 (en) | 1993-09-02 | 2003-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
| JPH07226510A (en) * | 1993-10-28 | 1995-08-22 | Lg Semicon Co Ltd | Doping of semiconductor polysilicon layer and manufacture of pmosfet using this |
| US5866930A (en) * | 1995-08-25 | 1999-02-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| WO1998013880A1 (en) * | 1996-09-25 | 1998-04-02 | Advanced Micro Devices, Inc. | POLY-Si/POLY-SiGe GATE FOR CMOS DEVICES |
| EP0859402A3 (en) * | 1997-01-21 | 1999-08-25 | Texas Instruments Incorporated | Method of manufacturing a MOS electrode |
| EP0859402A2 (en) * | 1997-01-21 | 1998-08-19 | Texas Instruments Incorporated | Method of manufacturing a MOS electrode |
| US5901084A (en) * | 1997-03-10 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device having floating gate electrode |
| US6720626B1 (en) | 1998-01-26 | 2004-04-13 | Renesas Technology Corp. | Semiconductor device having improved gate structure |
| US6744104B1 (en) | 1998-11-17 | 2004-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit including insulated gate field effect transistor and method of manufacturing the same |
| WO2008078363A1 (en) * | 2006-12-22 | 2008-07-03 | Renesas Technology Corp. | Process for producing semiconductor device and semiconductor device |
| JPWO2008078363A1 (en) * | 2006-12-22 | 2010-04-15 | 株式会社ルネサステクノロジ | Semiconductor device manufacturing method and semiconductor device |
| JP2008218661A (en) * | 2007-03-02 | 2008-09-18 | Fujitsu Ltd | Field-effect semiconductor device and manufacturing method therefor |
| JP2009010417A (en) * | 2008-09-05 | 2009-01-15 | Renesas Technology Corp | Manufacturing method of semiconductor device |
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