JP2008218661A - Field-effect semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To constitute a film, containing at least nitrogen and whose principal constituent is silicon, with superior composition control properties, without giving damages to a gate insulating film, regarding a field-effect semiconductor device and its manufacturing method. <P>SOLUTION: A conductive film containing silicon and nitrogen, which is 5-30 atomic number% with respect to silicon, is employed as at least one part of a gate electrode 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect semiconductor device and a method for manufacturing the same, and more particularly, to a field effect semiconductor device characterized by a configuration for suppressing crystallization of a silicon film which is a main component of a gate electrode and a method for manufacturing the same. It is about the method.

  In recent years, with the demand for higher performance and higher speed of semiconductor integrated circuit devices, there has also been a demand for miniaturization of MOSFETs constituting the semiconductor integrated circuit devices. To that end, the gate width (channel length) of MOSFETs has been reduced. In recent years, it has become necessary to control the variation in the gate width of a fine MOSFET on the order of nm.

Polycrystalline silicon that has been conventionally used as a gate electrode is a gate electrode material with excellent workability, but there is a problem of variations in gate width affected by the crystal grain size.
That is, although it is an amorphous film at the stage of film formation at a low temperature, it undergoes a thermal process such as activation of implanted ions, but rather changes to a polycrystal having a large crystal grain size, and is 50 nm or less, for example, 20 to 30 nm. In the patterning process of the width gate electrode, the influence of the crystal grain boundary becomes a problem.

  In addition, it is difficult to uniformly and abundantly add impurities for imparting conductivity to polycrystalline silicon that has been transformed into a large crystal grain size. Increased depletion of the gate electrode at the gate electrode / gate insulating film interface becomes a problem.

  In order to suppress the crystallization associated with such a thermal process, it is effective to contain nitrogen in silicon, thereby suppressing the crystallization of the silicon film, which can generate ultrafine polycrystals (nanocrystals). become.

It is also known that a nitrogen-containing silicon film having a low nitrogen concentration is closer to a polycrystalline silicon film or an amorphous silicon film as a semiconductor than a silicon nitride film as an insulating film, that is, a Si ₃ N ₄ film, and can be doped. (For example, see Non-Patent Document 1 to Non-Patent Document 3).

  On the other hand, in order to solve the problem of increase in wiring resistance due to miniaturization, MOSFETs using metal electrodes instead of polycrystalline silicon gate electrodes have been developed. In this case, a gate insulating film is used as the metal electrode. In view of reactivity with silicon, heat resistance, barrier resistance, and the like, use of metal silicide, metal nitride materials such as TiN, or metal silicon nitride materials has been studied.

Although the threshold voltage of the MOSFET of the metal gate electrode is defined by the work function of the metal used, it is known that the work function of the metal silicon nitride film depends greatly on the film composition (for example, Non-Patent Document 4 or Non-Patent Document 4). Therefore, it is possible to form a gate electrode having an optimal work function by controlling the film composition.
Jpn. J. et al. Appl. Phys. , L811-L813, 1981 J. et al. Crys. Groth, Vol. 95, p464-467, 1989 Thin Solid Films, Vol. 184, p373-377, 1990 J. et al. Vac. Sci. Technol. , Vol. B21, pp. 11-17, 2003 IEEE ELECTRON DEVICE LETTERS, Vol. 24, p. 429-431, 2003

However, when nitrogen is contained in silicon, film formation by chemical vapor deposition (CVD) is desirable in order to ensure the reliability of the gate insulating film, but CVD using NH ₃ as a nitrogen source Then, particles are generated by a strong gas phase reaction between NH ₃ and silicon source gas (SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ ), or composition fluctuation of nitrogen-containing silicon film and composition control difficulty are problems. Occurs.

  Further, since the CVD method generally has poor composition controllability, there is a problem that even if a metal silicon nitride film is formed, a film having a composition having an optimal work function for transistor characteristics cannot always be deposited.

  Therefore, an object of the present invention is to configure a film containing at least nitrogen and containing silicon as a main component with good composition controllability without damaging the gate insulating film.

FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
Reference numerals 1, 5, and 6 in the figure denote a semiconductor substrate, a source region, and a drain region, respectively.
In order to solve the above-described problems, the present invention provides a field effect semiconductor device in which a conductive film containing silicon as a main component and containing 5 to 30 atomic% of nitrogen with respect to silicon is gated. It is used as at least a part of the electrode 4.

Thus, by using a conductive film containing nitrogen of 5 to 30 atomic% with respect to silicon as at least a part of the gate electrode 4, it is possible to suppress polycrystallization of the gate electrode 4 and The conductivity required for the gate electrode 4 can also be maintained by setting the additive to 5 to 30 atomic%.
Note that “at least a part of the gate electrode 4” means the entire gate electrode 4, a material constituting the gate electrode 4, or a nitrogen-containing silicon layer constituting the gate electrode 4 having a stacked structure.

  As the structure of the gate electrode 4 in this case, the entire gate electrode 4 may be composed of the silicon film 3 containing nitrogen of 5 to 30 atomic%, and the gate is more depleted than the conventional polycrystalline silicon gate MOSFET. Suppressed and stable characteristics can be obtained.

  Alternatively, the entire gate electrode 4 may be composed of metal silicon nitride containing a metal element of 30 to 200 atomic% with respect to silicon, and by controlling the film composition with high accuracy, an optimum work function for transistor characteristics can be obtained. The gate electrode 4 having the composition can be realized, and the conductivity can be increased as compared with the nitrogen-containing silicon film.

  Alternatively, the gate electrode 4 is formed from a metal silicon nitride film containing a metal element of 30 to 200 atomic% and silicon film 3 containing nitrogen of 5 to 30 atomic% with respect to silicon from the gate insulating film 2 side. You may comprise from the laminated structure laminated | stacked.

  In general, a metal silicon nitride film has poor etching processability, it is difficult to obtain a rectangular pattern, has a tapered shoulder, and is inferior in controllability of the gate width. By using a metal silicon nitride film, variation in gate width can be reduced.

  Furthermore, the gate electrode 4 may have a laminated structure in which a metal silicon nitride film containing a metal element of 30 to 200 atomic% relative to silicon and a metal film are laminated from the gate insulating film 2 side. Thus, the resistance of the gate electrode 4 can be reduced. In particular, when applied to a CMOS, the gate electrode 4 of the p-channel MOSFET may be formed of a metal film constituting a laminated structure, so that the number of manufacturing steps is reduced. It will contribute to the reduction of.

  In this case, as the metal element constituting the metal silicon nitride film, Ti, Ta, W, Mo, Co are used in the case of using the CVD method, and the above-mentioned in the case of using the PVD method. In addition to metals, Ni, Ru, and Pt can be used.

In addition, the present invention provides a method for manufacturing a field effect semiconductor device, in which 5-30 atomic% nitrogen is used without using NH ₃ by using a chemical vapor deposition method using an inorganic silicon raw material containing nitrogen. And a step of using the deposited silicon film 3 containing 5 to 30 atomic% nitrogen as the gate electrode 4.

Thus, when forming a film by a chemical vapor deposition method (CVD method), by using an inorganic silicon raw material containing nitrogen, it is not necessary to use NH ₃ whose reaction is radical as a nitrogen source. The silicon film 3 containing 5 to 30 atomic% of nitrogen is deposited without damaging the gate insulating film 2 and without generating a large amount of particles, while suppressing composition variation and with good composition controllability. It becomes possible.

Further, in the step of depositing the silicon film 3 containing nitrogen of 5 to 30 atomic%, SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , or SiH _{2 is applied} to the inorganic silicon raw material containing nitrogen. By mixing any of Cl ₂ , the silicon film containing nitrogen having an arbitrary composition ratio within the range of 5 to 30 atomic% without being regulated by the N: Si ratio in the inorganic silicon raw material containing nitrogen 3 can be deposited.

  Further, in the step of using the deposited silicon film 3 containing 5 to 30 atomic% nitrogen as the gate electrode 4, the deposition process of the silicon film 3 containing 5 to 30 atomic% nitrogen, It may be configured to include a step of forming a metal silicon nitride film by heat treatment after alternately repeating the deposition steps, whereby the metal silicon nitride film can be deposited with good composition controllability.

  In the metal film deposition process in this case, any of Ti, Ta, W, Mo, Co, or a chloride or fluoride of which the deposition mechanism is well known and carbon (C) contamination can be suppressed. It is desirable to use

Further, as an inorganic silicon raw material containing nitrogen, trisilylamine (N [SiH ₃ ] ₃ ) is typical.
It is possible to form the silicon film 3 containing nitrogen by using an organic silicon raw material containing nitrogen, for example, an organic compound having a silazane bond, but it is not desirable because carbon is mixed therein.

  According to the present invention, a nitrogen-containing silicon film or metal silicon nitride film having a uniform composition can be formed without damaging the gate insulating film, thereby suppressing polycrystallization of the gate electrode. Therefore, variations in gate width can be reduced and depletion of the gate electrode can be suppressed.

The present invention provides, for example, an inorganic silicon raw material containing nitrogen when a silicon film containing nitrogen of 5 to 30 atomic% is deposited by CVD on a gate insulating film made of a high-k film such as HfSiON. In particular, trisilylamine (N [SiH ₃ ] ₃ ) is used and mixed with a silicon source such as SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , or SiH ₂ Cl _{2 as} necessary. Without using NH ₃ , a silicon film containing 5 to 30 atomic% nitrogen is deposited, and the deposited silicon film containing 5 to 30 atomic% nitrogen is used as a gate electrode. The whole is a nitrogen-containing silicon film, or as a material constituting the metal silicon nitride film, and further, a nitrogen-containing silicon layer constituting the gate electrode having a laminated structure.

  In the case of forming a metal silicon nitride film, a deposition process of a silicon film containing nitrogen of 5 to 30 atomic%, and Ti, Ta, W, Mo, Co when using a CVD method, When the PVD method is used, a metal silicon nitride film is formed by heat treatment after alternately repeating a deposition process of a metal film using Ni, Ru or Pt in addition to the metal.

Here, with reference to FIG. 2 thru | or FIG. 4, the manufacturing process of MISFET of Example 1 of this invention is demonstrated.
See Figure 2
First, after forming the element isolation region 12 on the p-type silicon substrate 11, an insulating film to be a gate insulating film is formed on the entire surface.
For example, the HfSiO ₂ film 13 to be a gate insulating film having a thickness of 1.6 nm to 5.0 nm, for example, 2.4 nm is deposited by using a low pressure chemical vapor deposition method (LPCVD method).
Of course, an insulating film made of another material such as a silicon oxide film may be formed.

In this deposition step, (t-C ₄ H ₉ O) ₄ Hf is used as the Hf source, Si ₂ H ₆ is used as the Si source, O ₂ or O ₃ is used as the O source, and N ₂ gas is used as the carrier gas. After the film formation, N is introduced by, for example, nitriding with NH ₃ at 650 ° C. or N ₂ plasma processing at 450 ° C. or lower, and the composition ratio of the HfSiO ₂ film 13 is (t-C ₄ Control with a flow rate of H ₉ O) ₄ Hf.

Next, it is a silicon film containing nitrogen that becomes a gate electrode at a substrate temperature of 500 ° C. to 650 ° C., for example, 570 ° C., by CVD using trisilylamine (N [SiH ₃ ] ₃ ) as a source gas. For example, the Si _x N film 14 is deposited to a thickness of 100 nm.
In this case, the composition ratio x of the Si _x N film 14 reflects the composition ratio of the raw material trisilylamine (N [SiH ₃ ] ₃ ) as will be described later, and is approximately x = 3 (the number of nitrogen atoms is%). Is 25 atomic percent).

Next, a gate structure including the gate insulating film 15 and the gate electrode 16 is formed by forming the Si _x N film 14 and the HfSiO ₂ film 13 into a width of 50 nm or less, for example, 30 nm using a photolithography process and a dry etching process. Form.

  Next, the n-type extension region 17 is formed by implanting P (phosphorus) ions shallowly using the gate structure as a mask.

See Figure 3
Next, after forming a SiO ₂ film on the entire surface, anisotropic etching is performed to form sidewalls 18, and then n ions are implanted by using the gate structure and sidewalls 18 as a mask to implant P ions. The region 19 is formed and the gate electrode 16 is doped with P.

  Next, a Co film is deposited on the entire surface and then alloyed by heat treatment to form a Co silicide electrode 20 on the surface of the n-type source / drain region 19 and a Co nitride electrode 21 on the surface of the gate electrode 16. And the unreacted Co film is removed.

  Next, after an interlayer insulating film 22 made of BPSG is deposited on the entire surface, via holes are formed for the Co silicide electrode 20 and the nitrided Co silicide electrode 21, and then the via holes are filled with W via a TiN film to form plugs 23. , 24 is completed, the basic structure of the MISFET of Example 1 of the present invention is completed.

See Figure 4
FIG. 4 is an explanatory diagram of the film formation temperature dependence of the composition ratio x in the Si _x N film, and also shows the temperature dependence of the film formation rate.
As is apparent from the figure, the composition ratio x in the Si _x N film is substantially constant x = 3 regardless of the temperature, which is the number of atoms of the starting material trisilylamine (N [SiH ₃ ] ₃ ). It is considered that the ratio Si / N = 3 is reflected.
Note that some variation in the figure is a measurement error associated with measurement accuracy.

Therefore, in Example 1 of the present invention, a Si _x N film having a stable composition ratio and no composition unevenness can be accurately formed.
Further, in the film forming process of the Si _x N film, since the CVD method not using NH ₃ is used, the gate insulating film is not damaged.

In addition, the Si _x N film is not polycrystallized in the thermal process associated with source / drain formation, and is in a nanocrystal or microcrystal state close to an amorphous state, so that impurities can be doped at a high concentration, Thereby, an increase in depletion of the gate electrode at the interface with the gate insulating film can be suppressed.

Next, with reference to FIG. 5, the manufacturing process of the MISFET of Example 2 of the present invention will be described.
See Figure 5
First, in the same manner as in the first embodiment, after the element isolation region 12 is formed on the p-type silicon substrate 11, the thickness is 1.6 nm to 5.0 nm, for example, 2.4 nm using the LPCVD method on the entire surface. An HfSiO ₂ film 13 to be a gate insulating film is deposited.

Next, nitrogen serving as a gate electrode is contained by a CVD method using trisilylamine (N [SiH ₃ ] ₃ ) and Si ₂ H ₆ as source gases at a substrate temperature of 500 ° C. to 650 ° C., for example, 570 ° C. A Si _x N film 31 that is a silicon film is deposited to a thickness of, for example, 100 nm.
In this case, the composition ratio x of the Si _x N film 31 is a value reflecting the flow rate ratio of the raw material trisilylamine (N [SiH ₃ ] ₃ ) and Si ₂ H _6. Sets the flow rate ratio to be 5-25 atomic%, for example, 15 atomic%.

Thereafter, the Si _x N film 31 and the HfSiO ₂ film 13 are again formed into a width of 50 nm or less, for example, 30 nm, using the photolithography process and the dry etching process, exactly as in the first embodiment. Thus, a gate structure including the gate insulating film 15 and the gate electrode 32 is formed.

Next, using the gate structure as a mask, P-type (phosphorus) ions are implanted shallowly to form an n-type extension region 17, and then an SiO ₂ film is formed on the entire surface, followed by anisotropic etching to form a sidewall. Next, n-type source / drain regions 19 are formed by implanting P ions using the gate structure and sidewalls 18 as a mask, and the gate electrode 32 is doped with P.

  Next, a Co film is deposited on the entire surface, and then alloyed by heat treatment to form a Co silicide electrode 20 on the surface of the n-type source / drain region 19 and a Co nitride electrode 33 on the surface of the gate electrode 32. And the unreacted Co film is removed.

  Next, after depositing an interlayer insulating film 22 made of BPSG over the entire surface, via holes for the Co silicide electrode 20 and the nitrided Co silicide electrode 33 are formed, and then the via holes are filled with W via a TiN film to form plugs 23. , 34 is completed, the basic structure of the MISFET of Example 2 of the present invention is completed.

In Example 2 of the present invention, when forming a Si _x N film to be a gate electrode, not only trisilylamine (N [SiH ₃ ] ₃ ) but also Si ₂ H ₆ which is a Si source is used as a source gas. In addition, the composition ratio x of the Si _x N film can be set to an arbitrary value of 3 or more, and the resistance increases as x increases.
However, if x is too large, it will not be different from polycrystalline silicon and the problem of crystallization due to the thermal process will occur. Therefore, it is desirable that the number of nitrogen atoms is 5 atomic percent or more and x is 19 or less. .

Next, with reference to FIGS. 6 and 7, the manufacturing process of the MISFET of Example 3 of the present invention will be described.
See FIG.
First, in the same manner as in the first embodiment, after forming the element isolation region 12 in the p-type silicon substrate 11, the thickness is 1.6 nm to 5.0 nm, for example, 2.4 nm using the LPCVD method on the entire surface. An HfSiO ₂ film 13 to be a gate insulating film is deposited.

Next, the thickness is, for example, 10 nm at a substrate temperature of 500 ° C. to 650 ° C., for example, 570 ° C., by a CVD method using trisilylamine (N [SiH ₃ ] ₃ ) and Si ₂ H ₆ as source gases. A Si _w N film 41 is deposited.
In this case, the flow ratio is set so that the composition ratio w of the Si _w N film 41 is 5 to 25 atomic%, for example, 15 atomic%, as the atomic% of nitrogen.

Next, a Ti film 42 having a thickness of, for example, 10 nm is deposited by thermal CVD using TiCl ₄ as a source gas and H ₂ as a carrier gas.
This process is repeated alternately as many times as necessary as a gate insulating film, so that the total thickness is, for example, 50 nm.

Next, by annealing at a substrate temperature of 500 ° C. to 650 ° C., for example, 650 ° C. in an H ₂ atmosphere, the laminated film 43 made of (Si _w N film / Ti film) _{n is changed} to a Ti _x Si _y N _z film 44. Convert to

The composition ratio of Ti _x Si _y N _z film 44 in this case, Si _w composition ratio and w of the N layer 41, determined by the film thickness ratio of Si _w N layer 41 and the Ti film 42.
At this time, the Cl derived from TiCl ₄ contained in (Si _w N film / Ti film) _n can be reduced and removed by the reducing action of H ₂ .

See FIG.
Thereafter, the Ti _x Si _y N _z film 44 and the HfSiO ₂ film 13 are again made to have a width of 50 nm or less, for example, 30 nm using the photolithography process and the dry etching process, exactly as in the first embodiment. A gate structure including the gate insulating film 15 and the gate electrode 45 is formed by molding.

Next, using the gate structure as a mask, P-type (phosphorus) ions are implanted shallowly to form an n-type extension region 17, and then an SiO ₂ film is formed on the entire surface, followed by anisotropic etching to form a sidewall. Next, n-type source / drain regions 19 are formed by implanting P ions using the gate structure and sidewalls 18 as a mask, and the gate electrode 45 is doped with P.

  Next, a Co film is deposited on the entire surface and then alloyed by heat treatment to form a Co silicide electrode 20 on the surface of the n-type source / drain region 19 and a Co nitride electrode 46 on the surface of the gate electrode 45. And the unreacted Co film is removed.

  Next, after depositing an interlayer insulating film 22 made of BPSG over the entire surface, via holes for the Co silicide electrode 20 and the nitrided Co silicide electrode 46 are formed, and then the via holes are filled with W via a TiN film to form plugs 23. , 47 is completed, the basic structure of the MISFET of Example 3 of the present invention is completed.

In Example 3 of the present invention, the gate electrode is formed of a Ti _x Si _y N _z film, that is, a metal silicon nitride film, and trisilylamine (N [SiH ₃ ] ₃ ) is used as the Si _w N raw material. Therefore, it is possible to form a Ti _x Si _y N _z film having no composition unevenness and a stable composition ratio, and to form a gate electrode having a composition having an optimum work function for transistor characteristics. Become.

Next, a MISFET according to a fourth embodiment of the present invention will be described with reference to FIG. 8. The basic manufacturing process is the same as that of the first to third embodiments except that the gate electrode structure is different. Therefore, only the gate electrode structure will be described.
See FIG.
FIG. 8 is a schematic cross-sectional view of a MISFET according to a fourth embodiment of the present invention. The gate electrode 51 includes a lower gate composed of a Ti _x Si _y N _z film 52 and an upper gate composed of a Si _x N film 53. It is formed by a layer structure.

In this case, the Ti _x Si _y N _z film 52 is formed by the same method as in the third embodiment, and the thickness is, for example, 10 nm, while the Si _x N film 53 is formed as described above. The film is formed by exactly the same method as in Example 1 or Example 2, and the thickness is, for example, 100 nm.

In the fourth embodiment, the Ti _x Si _y N _z film 52 that is inferior in dry etching processability is thinned, and the Si _x N film 53 that has the same dry etching processability as polycrystalline silicon is thickened. The processing accuracy of the structure can be kept high.

Further, since the work function related to the transistor characteristics reflects the work function of the Ti _x Si _y N _z film 52, a gate electrode having a composition having an optimum work function for the transistor characteristics is formed as in the third embodiment. It becomes possible to form.

Next, referring to FIG. 9, the MISFET according to the fifth embodiment of the present invention will be described. In this case, the basic manufacturing process is the same as that of the third embodiment except that the gate electrode structure is different. Only the gate electrode structure will be described.
See FIG.
FIG. 9 is a schematic cross-sectional view of a MISFET according to Example 5 of the present invention, in which the gate electrode 61 has a two-layer structure of a lower layer gate made of a Ti _x Si _y N _z film 62 and an upper layer gate made of a Ru film 63. It is formed by.

In this case, the Ti _x Si _y N _z film 62 is formed by exactly the same method as in the third embodiment, and the thickness is, for example, 10 nm. On the other hand, the thickness of the Ru film 63 is, for example, , 100 nm.

In the fifth embodiment, Ru having excellent dry etching processability is used as the upper gate in the metal film, so that the processing accuracy of the gate structure can be kept high.
In addition, since the work function related to the transistor characteristics reflects the work function of the Ti _x Si _y N _z film 62, a gate electrode having a composition having an optimum work function for the transistor characteristics is formed as in the third embodiment. It becomes possible to form.

  In the fifth embodiment, since Ru is used as the gate electrode of the p-channel type MISFET as the upper gate, when applied to the CMOS manufacturing process, the p-channel type is used in the Ru deposition process of the upper gate. By depositing also on the MISFET side, it becomes possible to simultaneously form the upper gate of the n-channel type MISFET and the gate electrode of the p-channel type MISFET.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations, conditions, and numerical values shown in the embodiments, and various modifications are possible. For example, in the above embodiments, Is described as an n-channel type MISFET, but may be applied to a p-channel type MISFET although it has a relationship with a work function.

Further, in the above-mentioned embodiments, although using the currently available trisilylamine (N [SiH _{3] 3)} as the silicon raw material containing nitrogen, in principle, trisilylamine (N [SiH ₃ ] It is not limited to ₃ ), and may be any inorganic compound that does not contain C and O and contains N and Si as main components.

In Example 2 described above, Si ₂ H ₆ is used as the Si source mixed with trisilylamine (N [SiH ₃ ] ₃ ), but is not limited to Si ₂ H ₆ , and SiH ₄ Other silanes such as Si ₃ H ₈ or SiH ₂ Cl ₂ may be used.

In the third embodiment, TiCl ₄ is used as the metal source. However, it is not limited to TiCl ₄ , and other metal chlorides such as TaCl ₅ may be used.
For example, a chloride of W, Mo, Co or a fluoride of Ti, Ta, W, Mo, Co may be used.

  Further, in Example 4 described above, the metal is formed by the CVD method, but may be formed by the PVD method such as the evaporation method. In that case, in addition to the above-described metal, Ni , Ru or Pt may be deposited as a metal film.

Further, in the above-mentioned embodiments, although using HfSiON a High-k film as a gate insulating film is not limited to the HfSiON, for example, HfO _2, HfSiO, HfAlO, or other such HfAlON A high-k film may be used.

Furthermore, the gate insulating film is not limited to the high-k film, and an insulating film such as SiO ₂ , SiON, or Si ₃ N ₄ may be used.

Here, referring to FIG. 1 again, the detailed features of the present invention will be described again.
Again see Figure 1
(Supplementary Note 1) A field effect semiconductor device using a conductive film containing silicon and nitrogen of 5 to 30 atomic% with respect to the silicon as at least a part of the gate electrode 4.
(Additional remark 2) The field effect type semiconductor device characterized by using as a gate electrode 4 the silicon silicon nitride layer which contains silicon and 30-200 atomic percent metal element with respect to the said silicon.
(Supplementary Note 3) The gate electrode 4 includes the metal silicon nitride film formed on the gate insulating film 2 and the silicon film 3 containing 5 to 30 atomic% nitrogen formed on the metal silicon nitride film. 2. The field effect semiconductor device according to appendix 2, wherein the field effect semiconductor device has a laminated structure in which
(Additional remark 4) The said gate electrode 4 consists of a laminated structure of the said metal silicon nitride film formed on the gate insulating film 2, and the metal film formed on the said metal silicon nitride film. 3. The field effect semiconductor device according to 2.
(Supplementary note 5) Any one of Supplementary notes 2 to 4, wherein the metal element constituting the metal silicon nitride film is at least one of Ti, Ta, W, Mo, Co, Ni, Ru, or Pt. 2. The field effect semiconductor device according to claim 1.
(Additional remark 6) Forming an insulating film on the semiconductor substrate 1, and 5-30 atomic% nitrogen using the chemical vapor deposition method using the inorganic silicon raw material containing nitrogen on the said insulating film A field effect type comprising: a step of depositing a silicon film 3 containing silicon; a step of patterning the silicon film 3; and a step of forming a source region 5 and a drain region 6 in the semiconductor substrate 1. A method for manufacturing a semiconductor device.
(Supplementary Note 7) In the step of depositing the silicon film 3, any of SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , or SiH ₂ Cl ₂ is mixed with the inorganic silicon raw material containing nitrogen. The method for manufacturing a field effect semiconductor device according to appendix 6, wherein:
(Supplementary note 8) The field effect semiconductor according to supplementary note 6 or 7, further comprising a step of forming a metal film in a laminated form with the silicon film 3 and reacting the metal film and the silicon film by heat treatment. Device manufacturing method.
(Supplementary note 9) The electric field according to supplementary note 9, wherein the metal film deposition step is performed by a CVD method using a chloride or fluoride of Ti, Ta, W, Mo, or Co as a raw material. Method of manufacturing effect type semiconductor device.
(Supplementary Note 10) inorganic silicon raw material containing the nitrogen, producing a field effect semiconductor device according to any one of Appendices 6 to 9, characterized in that a trisilylamine (N [SiH _{3] 3)} Method.

  As a practical example of the present invention, the gate electrode of an insulated gate transistor is typical, but the invention is not limited to the gate electrode, and it is also used as an internal local wiring.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of MISFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 2 of MISFET of Example 1 of this invention. Composition ratio of Si _x N film is an explanatory view of a deposition temperature dependence of x. It is explanatory drawing of the manufacturing process of MISFET of Example 2 of this invention. It is explanatory drawing of the manufacturing process to the middle of MISFET of Example 3 of this invention. It is explanatory drawing of the manufacturing process after FIG. 6 of MISFET of Example 3 of this invention. It is a schematic sectional drawing of MISFET of Example 4 of this invention. It is a schematic sectional drawing of MISFET of Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Silicon film containing nitrogen 4 Gate electrode 5 Source region 6 Drain region 11 P-type silicon substrate 12 Element isolation region 13 HfSiO ₂ film 14 Si _x N film 15 Gate insulating films 16, 32, 45 Gate electrode 17 N-type extension region 18 Side wall 19 N-type source / drain region 20 Co silicide electrodes 21, 33, 46, 54 Co nitride silicide electrodes 23, 24, 34, 47, 55, 64 Plug 31 Si _x N film 41 Si _w N film 42 Ti film 43 Laminated film 44 Ti _x Si _y N _z film 51 Gate electrode 52 Ti _x Si _y N _z film 53 Si _x N film 61 Gate electrode 62 Ti _x Si _y N _z film 63 Ru film

Claims (5)

A step of forming an insulating film on a semiconductor substrate; and a silicon film containing 5 to 30 atomic% of nitrogen on the insulating film using a chemical vapor deposition method using an inorganic silicon raw material containing nitrogen And a step of patterning the silicon film; and a step of forming a source region and a drain region in the semiconductor substrate. In the step of depositing the silicon film, any one of SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , or SiH ₂ Cl ₂ is mixed with an inorganic silicon raw material containing nitrogen. Item 2. A method for manufacturing a field-effect semiconductor device according to Item 1. 3. The method of manufacturing a field effect semiconductor device according to claim 1, further comprising a step of forming a metal film on the silicon film in a layered manner and reacting the metal film and the silicon film by heat treatment. . The method for manufacturing a field effect semiconductor device according to any one of claims 1 to 3, wherein the nitrogen-containing inorganic silicon raw material is trisilylamine (N [SiH ₃ ] ₃ ). A field-effect semiconductor device using silicon and a conductive film containing nitrogen of 5 to 30 atomic% with respect to silicon as at least part of a gate electrode.

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