JPH04246200A - Method for electroplating substrate - Google Patents

Method for electroplating substrate

Info

Publication number
JPH04246200A
JPH04246200A JP868391A JP868391A JPH04246200A JP H04246200 A JPH04246200 A JP H04246200A JP 868391 A JP868391 A JP 868391A JP 868391 A JP868391 A JP 868391A JP H04246200 A JPH04246200 A JP H04246200A
Authority
JP
Japan
Prior art keywords
substrate
auxiliary electrode
conductive tape
plating
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP868391A
Other languages
Japanese (ja)
Inventor
Hideo Mogi
茂木 英男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP868391A priority Critical patent/JPH04246200A/en
Publication of JPH04246200A publication Critical patent/JPH04246200A/en
Pending legal-status Critical Current

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  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To uniformize the thickness of a plating without wasting a part of a substrate and to electroplate the substrate. CONSTITUTION:An auxiliary electrode 13 is frame shaped and opposed to the surface 10a of a substrate 10 to be plated. A negative voltage is impressed on the auxiliary electrode 13 from an auxiliary power source 15. The current density of the auxiliary electrode 13 is controlled to several times that of the substrate 10. The auxiliary electrode 13 absorbs an electric current flowing toward the periphery of the substrate 10 in a plating soln., and the thickness of the plating on the periphery of the substrate 10 is not increased.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はセラミック基板にパネル
メッキを電解メッキ法によって形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming panel plating on a ceramic substrate by electrolytic plating.

【0002】セラミック基板の表面の配線パターンは、
研磨したセラミック基板の表面にスパッタリングにより
金属膜を形成し、この後、レジストパターンを形成し、
次いで電解メッキ法によってCu,Ni,Auのパネル
メッキを形成し、レジストパターンを剥離し、パネルエ
ッチングを行って形成している。
[0002] The wiring pattern on the surface of the ceramic substrate is
A metal film is formed on the surface of the polished ceramic substrate by sputtering, and then a resist pattern is formed,
Next, panel plating of Cu, Ni, and Au is formed by electrolytic plating, the resist pattern is peeled off, and panel etching is performed.

【0003】配線パターンが厚くなりすぎると、熱が吸
収されてはんだののりが悪くなり、逆に薄くなりすぎる
と、電気抵抗値が大となったり、断線し易くなる。
[0003] If the wiring pattern becomes too thick, heat will be absorbed and the solder will not adhere well, whereas if it becomes too thin, the electrical resistance value will increase or wires will be easily broken.

【0004】従って、セラミック基板の品質の向上を図
るためには、配線パターンは、セラミック基板の全面に
亘って均一な電気的特性を有していることか必要である
Therefore, in order to improve the quality of the ceramic substrate, it is necessary that the wiring pattern has uniform electrical characteristics over the entire surface of the ceramic substrate.

【0005】このためには、パネルメッキがセラミック
基板の全面に亘って厚さを均一とされて形成されること
が必要とされる。
[0005] For this purpose, it is necessary that the panel plating be formed with a uniform thickness over the entire surface of the ceramic substrate.

【0006】[0006]

【従来の技術】図12は、基板の電解メッキ方法の基本
構成を示す。
2. Description of the Related Art FIG. 12 shows the basic structure of an electrolytic plating method for a substrate.

【0007】1はスパッタリング済のセラミック基板,
2はアノード,3は電源である。メッキ槽内において、
電流は符号4で示すように流れ、セラミック基板1のス
パッタリング膜上にパネルメッキ膜5が形成される。
1 is a sputtered ceramic substrate;
2 is an anode, and 3 is a power supply. In the plating tank,
A current flows as indicated by reference numeral 4, and a panel plating film 5 is formed on the sputtered film of the ceramic substrate 1.

【0008】メッキ膜5の厚さは、電流密度に比例する
。電流4は、基板1の中央より周辺部分に集中し易く、
基板1の周辺部分の電流密度が中央部分より高くなる。 このため、メッキ膜5は、基板1の周囲部分の厚さt1
 が中央部分の厚さt2 より厚くなってしまう。
The thickness of the plating film 5 is proportional to the current density. The current 4 is more likely to concentrate on the periphery than the center of the substrate 1,
The current density in the peripheral portion of the substrate 1 is higher than that in the central portion. Therefore, the plating film 5 has a thickness t1 around the substrate 1.
becomes thicker than the thickness t2 of the central portion.

【0009】図12の構成は、図5中■に対応し、図6
に示すように、中央部分の厚さt2 に1.74μmで
あるのに対し、周辺部分の厚さt1は3.58μmとな
り、周辺部分が中央部分に対して厚い割合は100%と
もなってしまう。
The configuration in FIG. 12 corresponds to (■) in FIG.
As shown in the figure, the thickness t2 of the central portion is 1.74 μm, while the thickness t1 of the peripheral portion is 3.58 μm, and the ratio of the peripheral portion being thicker than the central portion is 100%.

【0010】そこで、上記の問題を解決するため、従来
は、特公昭58−58835号に示すように、基板を、
周辺に、連結用リブを介して、ダミースペースとしての
外形枠を設けた構成とし、電解メッキを行った後に、連
結用リブを折って外形枠を除去する方法を取っていた。
Therefore, in order to solve the above problem, conventionally, as shown in Japanese Patent Publication No. 58-58835, the substrate was
A method was used in which an outer frame was provided as a dummy space on the periphery via a connecting rib, and after electrolytic plating was performed, the connecting rib was broken and the outer frame was removed.

【0011】この方法によれば、メッキ膜が厚くなった
部分は除去され、基板におけるメッキ膜の厚さは均一化
される。
According to this method, the thickened portion of the plating film is removed, and the thickness of the plating film on the substrate is made uniform.

【0012】0012

【発明が解決しようとする課題】しかし、上記の方法に
よれば、各基板について外形枠の部分が無駄となってし
まい、その分、製造コストが高くなってしまう。
However, according to the above method, the outer frame portion of each board is wasted, and the manufacturing cost increases accordingly.

【0013】本発明は、製造コストを上昇させることな
くメッキ厚さの均一化を可能とした基板の電解メッキ方
法を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for electrolytic plating of a substrate, which makes it possible to make the plating thickness uniform without increasing manufacturing costs.

【0014】[0014]

【課題を解決するための手段】請求項1の発明は、内側
縁が電解メッキされる基板と実質上同じ大きさを有する
枠形状の補助電極を、上記基板のうちアノードに対向す
る面の近傍に、且つ上記アノード側からみて上記基板を
囲むように配設すると共に、該補助電極に、負電圧を印
加する構成としたものである。
[Means for Solving the Problems] The invention according to claim 1 provides a frame-shaped auxiliary electrode whose inner edge has substantially the same size as the substrate to be electrolytically plated, in the vicinity of the surface of the substrate facing the anode. The auxiliary electrode is arranged so as to surround the substrate when viewed from the anode side, and a negative voltage is applied to the auxiliary electrode.

【0015】請求項2の発明は、電解メッキされる基板
を保持する保持枠のうち、アノードに対向する面に、導
電性のテープを、上記基板を囲撓して且つ剥離可能に貼
着すると共に、該導電性テープに負電圧を印加する構成
としたものである。
[0015] According to a second aspect of the invention, a conductive tape is attached to the surface of the holding frame that holds the substrate to be electrolytically plated, facing the anode, so as to surround the substrate and to be able to peel it off. At the same time, a negative voltage is applied to the conductive tape.

【0016】請求項3の発明は、内側縁が電解メッキさ
れる基板と実質上同じ大きさを有する枠形状の補助電極
を、上記基板のうちアノードに対向する面の近傍に、且
つ上記アノード側からみて上記基板を囲むように配設す
ると共に、該補助電極に、負電圧を印加する構成とし、
且つ上記基板を保持する保持枠のうち、アノードに対向
する面に、導電性のテープを、上記基板を囲撓して且つ
剥離可能に貼着すると共に、該導電性テープに負電圧を
印加する構成としたものである。
According to the third aspect of the invention, a frame-shaped auxiliary electrode whose inner edge is substantially the same size as the substrate to be electrolytically plated is provided near the surface of the substrate facing the anode and on the anode side. The auxiliary electrode is arranged so as to surround the substrate when viewed from above, and a negative voltage is applied to the auxiliary electrode,
A conductive tape is attached to the surface of the holding frame that holds the substrate facing the anode so as to be able to bend and peel off the substrate, and a negative voltage is applied to the conductive tape. It is structured as follows.

【0017】[0017]

【作用】請求項1の発明において、補助電極はメッキ液
中を基板の周辺部に向かって流れる電流を吸収する。
According to the first aspect of the invention, the auxiliary electrode absorbs the current flowing through the plating solution toward the periphery of the substrate.

【0018】請求項2の発明において、導電性テープは
前記従来例におけるダミーパターンとしての役割を果た
す。
In the second aspect of the invention, the conductive tape serves as a dummy pattern in the conventional example.

【0019】導電性テープは、常に新しいものと交換可
能である。請求項3の発明において、補助電極は、基板
の周辺部に流れる電流を吸収する。導電性テープは交換
可能なダミーパターンとして機能する。
[0019] The conductive tape can always be replaced with a new one. In the invention according to claim 3, the auxiliary electrode absorbs the current flowing in the peripheral portion of the substrate. The conductive tape functions as a replaceable dummy pattern.

【0020】[0020]

【実施例】図1は本発明の第1実施例を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention.

【0021】図中、10はセラミック基板,11は保持
枠,12はアノード,13は補助電極,14は電圧V1
 の主電源,15は電圧V2 の補助電源である。
In the figure, 10 is a ceramic substrate, 11 is a holding frame, 12 is an anode, 13 is an auxiliary electrode, and 14 is a voltage V1.
, and 15 is an auxiliary power source with a voltage of V2.

【0022】セラミック基板10は、ダミーパターンの
外枠部分は有さず、完成品であるセラミックプリント配
線板と同じ大きさである。
The ceramic substrate 10 does not have an outer frame portion of the dummy pattern and has the same size as the finished ceramic printed wiring board.

【0023】保持枠11は、図2に示すように、一対の
枠16,17とよりなる。枠16と17とは、基板10
を挟んだ状態でねじ18により固定され、基板10は、
周囲を挟み込まれて保持枠11に固定される。
The holding frame 11 consists of a pair of frames 16 and 17, as shown in FIG. The frames 16 and 17 are connected to the substrate 10.
The board 10 is fixed with screws 18 while sandwiching the
The periphery is sandwiched and fixed to the holding frame 11.

【0024】枠16,17はフック部16a等を除いて
樹脂により被覆されて絶縁されている。
The frames 16 and 17 are covered with resin and insulated, except for the hook portions 16a and the like.

【0025】補助電極13は、矩形枠形状を有し、且つ
内側縁13aが基板10と実質上同じ大きさを有する。
The auxiliary electrode 13 has a rectangular frame shape, and an inner edge 13a has substantially the same size as the substrate 10.

【0026】この補助電極13は、基板10のうちアノ
ード12に対向する面10aの近傍に、且つ、図3に示
すように、アノード12側からみて基板10を囲撓する
ように配設してある。
The auxiliary electrode 13 is arranged near the surface 10a of the substrate 10 facing the anode 12, and so as to surround the substrate 10 when viewed from the anode 12 side, as shown in FIG. be.

【0027】図1中、基板10と補助電極13との間の
距離L1 と、補助電極13とアノード12との間の距
離L2 との比、L1 :L2 は、例えば1:3であ
る。
In FIG. 1, the ratio of the distance L1 between the substrate 10 and the auxiliary electrode 13 to the distance L2 between the auxiliary electrode 13 and the anode 12, L1:L2, is, for example, 1:3.

【0028】また補助電極13に接続される補助電源1
5の電圧V2 は、補助電極13の電流密度A1 (A
/cm2 )が基板10の電流密度A2 (A/cm2
 )の約3倍となるように定めてある。
[0028] Also, the auxiliary power supply 1 connected to the auxiliary electrode 13
The voltage V2 of 5 is the current density A1 (A
/cm2) is the current density A2 (A/cm2) of the substrate 10
) is set to be approximately three times as large.

【0029】電解メッキ時、図4に示すように、メッキ
液中を電流19が流れ、基板10の面10aの上にメッ
キ膜20が形成される。
During electrolytic plating, as shown in FIG. 4, a current 19 flows through the plating solution, and a plating film 20 is formed on the surface 10a of the substrate 10.

【0030】電流19のうち、補助電極13が無いなら
ば、基板10の周辺部に流れ込む電流19aは、図4に
示すように、補助電極15に吸収される。基板10には
、補助電極13の内側を通り抜けた電流19bだけが流
れ込む。このため、基板10の面10a内における電流
密度の分布をみてみると、中央部分は従来と略同じで、
周辺部分が従来に比べて低く抑えられる。
If the auxiliary electrode 13 is not present in the current 19, the current 19a flowing into the periphery of the substrate 10 will be absorbed by the auxiliary electrode 15, as shown in FIG. Only the current 19b that has passed through the inside of the auxiliary electrode 13 flows into the substrate 10. Therefore, when looking at the current density distribution within the surface 10a of the substrate 10, the central portion is approximately the same as the conventional one;
The surrounding area can be kept lower than before.

【0031】これにより、メッキ膜20は図5及び図6
の■に併せて示すように、中央部分の厚さt2 が1.
88μmとなって従来より若干増え、周辺部分の厚さt
1 が2.85となって、従来より大幅に減っている。
As a result, the plating film 20 is formed as shown in FIGS. 5 and 6.
As shown in conjunction with (■), the thickness t2 of the central portion is 1.
It is 88μm, which is slightly larger than before, and the thickness of the peripheral part is t.
1 became 2.85, which is significantly lower than before.

【0032】これにより、周辺部分が中央部分に比べて
厚い割合は51%程度に抑えられる。
[0032] As a result, the ratio of the peripheral portion being thicker than the central portion can be suppressed to about 51%.

【0033】図7は本発明の第2実施例を示す。図1中
、補助電極13を除去し、保持枠11のうちアノード1
2に対向する面11aに導電性テープ30を基板10を
囲むように貼着し、この導電性テープ30に主電源14
の負電圧V1を基板10と同様に印加した構成である。
FIG. 7 shows a second embodiment of the invention. In FIG. 1, the auxiliary electrode 13 is removed and the anode 1 of the holding frame 11 is removed.
A conductive tape 30 is attached to the surface 11a facing the substrate 10 so as to surround the substrate 10, and the main power source 14 is connected to the conductive tape 30.
This is a configuration in which a negative voltage V1 of V1 is applied in the same manner as in the substrate 10.

【0034】導電性テープ30は、図8に示すように、
枠16に剥離可能に貼着される。メッキ液中を電流31
が図9に示すように流れ、基板10及び導電性テープ3
0上に、メッキ膜32が形成される。
[0034] As shown in FIG. 8, the conductive tape 30 has
It is removably attached to the frame 16. Current 31 through the plating solution
flows as shown in FIG. 9, and the substrate 10 and the conductive tape 3
0, a plating film 32 is formed.

【0035】電流31は、基板10の外側に位置する導
電性テープ30が基板の周辺部であるかのように流れ、
導電性テープ30上のメッキ膜32が最も厚くなる。電
解メッキの上では、基板10の周辺部分は、みかけ上基
板の周辺部分より中央寄りの部分となる。
The current 31 flows through the conductive tape 30 located outside the substrate 10 as if it were the periphery of the substrate.
The plating film 32 on the conductive tape 30 is the thickest. After electrolytic plating, the peripheral portion of the substrate 10 appears to be closer to the center than the peripheral portion of the substrate.

【0036】このため、基板10上のメッキ膜32は、
図5及び図6の■に併せて示すように、中央部分厚さt
2 が1.82μmであり、従来と殆ど変わらず、周辺
部分の厚さt1 は3.04μmであり、従来より相当
減っている。
Therefore, the plating film 32 on the substrate 10 is
As shown in FIGS. 5 and 6, the central portion thickness t
2 is 1.82 μm, which is almost the same as before, and the thickness t1 of the peripheral portion is 3.04 μm, which is considerably smaller than before.

【0037】周辺部分が中央部分に比べて厚い割合は、
67%程度に抑えられている。メッキが付いた導電性テ
ープをそのまま使用するとメッキが付着する面積が徐々
に変化してしまい、メッキ条件が変化することになるた
め、一回のメッキの終了毎に剥離して新しいものを貼り
換える。
The ratio of the thickness of the peripheral part compared to the central part is
It has been suppressed to around 67%. If a conductive tape with plating is used as is, the area to which the plating adheres will gradually change, and the plating conditions will change, so it must be peeled off and replaced with a new one after each plating. .

【0038】図10は、本発明の第3実施例を示す。本
実施例では、前記の第1実施例と第2実施例とを組み合
わせたものであり、図10中、図1及び図7に示す構成
部分と対応する部分には同一符号を付す。
FIG. 10 shows a third embodiment of the invention. This embodiment is a combination of the first embodiment and the second embodiment, and in FIG. 10, the same reference numerals are given to the parts corresponding to those shown in FIGS. 1 and 7.

【0039】図11は、メッキ液中の電流の流れの状態
を示す。アノード12より出る電流40のうち、基板1
0の周辺部に向かう電流40aは、補助電極13に吸収
される。
FIG. 11 shows the state of current flow in the plating solution. Of the current 40 output from the anode 12, the substrate 1
The current 40a directed toward the periphery of 0 is absorbed by the auxiliary electrode 13.

【0040】補助電極13の内側を通過した電流40b
は、導電性テープ30が基板の周辺部であるかのように
、拡がって導電性テープ30に多く、基板10に少なく
流れ込む。
Current 40b passing inside the auxiliary electrode 13
spreads out and flows more into the electrically conductive tape 30 and less into the substrate 10, as if the electrically conductive tape 30 were at the periphery of the substrate.

【0041】これにより、基板10上のメッキ膜41は
、図5及び図6の■に併せて示すように、中央部分の厚
さt2 が1.96μm、周辺部分の厚さt1 が2.
46μmとなった。周辺部分が中央部分に比べて厚い割
合は、25%程度にまで抑えられている。
As a result, the plating film 41 on the substrate 10 has a thickness t2 of 1.96 μm at the central portion and a thickness t1 of 2.0 μm at the peripheral portion, as shown in FIGS.
It became 46 μm. The ratio of the peripheral portion being thicker than the central portion is suppressed to about 25%.

【0042】[0042]

【発明の効果】以上説明した様に、請求項1の発明によ
れば、基板の一部を廃棄して無駄とすることなく、基板
のメッキ厚の均一化を図ることが出来る。
As described above, according to the invention of claim 1, it is possible to make the plating thickness of the substrate uniform without discarding a part of the substrate and wasting it.

【0043】請求項2の発明によれば、基板の一部を廃
棄するという無駄を生ぜずに、且つ補助電極を使用する
場合に比べて簡易に、基板のメッキ厚の均一化を図るこ
とが出来る。
[0043] According to the invention of claim 2, the plating thickness of the substrate can be made uniform more easily than in the case of using an auxiliary electrode without causing waste such as discarding a part of the substrate. I can do it.

【0044】請求項3の発明によれば、基板の一部を廃
棄するという無駄を生ぜずに、基板のメッキ厚の均一化
を効果的に図ることが出来る。
According to the third aspect of the present invention, it is possible to effectively uniformize the plating thickness of the substrate without causing waste such as discarding a part of the substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の基板の電解メッキ方法の第1実施例を
示す図である。
FIG. 1 is a diagram showing a first embodiment of the electrolytic plating method for a substrate according to the present invention.

【図2】図1中の保持枠の構成を示す図である。FIG. 2 is a diagram showing the configuration of a holding frame in FIG. 1;

【図3】図1中、アノード側からみた補助電極と基板と
の位置関係を示す図である。
FIG. 3 is a diagram showing the positional relationship between an auxiliary electrode and a substrate viewed from the anode side in FIG. 1;

【図4】図1中のメッキ液中の電流の流れを示す図であ
る。
FIG. 4 is a diagram showing the flow of current in the plating solution in FIG. 1.

【図5】補助電極と導電性テープとの組合せを示す図で
ある。
FIG. 5 is a diagram showing a combination of an auxiliary electrode and a conductive tape.

【図6】図5の組合せに対応するメッキ厚さを示す図で
ある。
FIG. 6 is a diagram showing plating thicknesses corresponding to the combination of FIG. 5;

【図7】本発明の基板の電解メッキ方法の第2実施例を
示す図である。
FIG. 7 is a diagram showing a second embodiment of the electrolytic plating method for a substrate according to the present invention.

【図8】図7中の保持枠の構成を示す図である。8 is a diagram showing the configuration of the holding frame in FIG. 7. FIG.

【図9】図7中のメッキ液中の電流の流れを示す図であ
る。
9 is a diagram showing the flow of current in the plating solution in FIG. 7. FIG.

【図10】本発明の基板の電解メッキ方法の第3実施例
を示す図である。
FIG. 10 is a diagram showing a third embodiment of the electrolytic plating method for a substrate according to the present invention.

【図11】図10中のメッキ液中の電流の流れを示す図
である。
11 is a diagram showing the flow of current in the plating solution in FIG. 10. FIG.

【図12】電解メッキ時のメッキ液中の電流の一般的な
流れを示す図である。
FIG. 12 is a diagram showing a general flow of current in a plating solution during electrolytic plating.

【符号の説明】[Explanation of symbols]

10  セラミック基板 11  保持枠 12  アノード 13  補助電極 14  主電源 15  補助電源 19,31,40  メッキ液中を流れる電流20,3
2,41  メッキ膜 30  導電性テープ
10 Ceramic substrate 11 Holding frame 12 Anode 13 Auxiliary electrode 14 Main power supply 15 Auxiliary power supply 19, 31, 40 Current flowing in the plating solution 20, 3
2,41 Plated film 30 Conductive tape

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  内側縁(13a)が電解メッキされる
基板(10)と実質上同じ大きさを有する枠形状の補助
電極(13)を、上記基板(10)のうちアノード(1
2)に対向する面(10a)の近傍に、且つ上記アノー
ド側からみて上記基板を囲むように配設すると共に、該
補助電極(13)に、負電圧(V2 )を印加する構成
としたことを特徴とする基板の電解メッキ方法。
1. A frame-shaped auxiliary electrode (13) whose inner edge (13a) has substantially the same size as the substrate (10) to be electrolytically plated is attached to the anode (1) of the substrate (10).
The auxiliary electrode (13) is arranged near the surface (10a) facing the auxiliary electrode (10a) and surrounding the substrate when viewed from the anode side, and is configured to apply a negative voltage (V2) to the auxiliary electrode (13). A method for electrolytic plating of a substrate, characterized by:
【請求項2】  電解メッキされる基板(10)を保持
する保持枠(11)のうち、アノード(12)に対向す
る面に、導電性のテープ(30)を、上記基板(10)
を可撓して且つ剥離可能に貼着すると共に、該導電性テ
ープ(30)に、負電圧(V1 )を印加する構成とし
たことを特徴とする基板の電解メッキ方法。
2. A conductive tape (30) is placed on the side of the holding frame (11) that holds the substrate (10) to be electrolytically plated, which faces the anode (12).
A method for electrolytic plating of a substrate, characterized in that the conductive tape (30) is attached in a flexible and peelable manner, and a negative voltage (V1) is applied to the conductive tape (30).
【請求項3】  内側縁(13a)  が電解メッキさ
れる基板(10)と実質上同じ大きさを有する枠形状の
補助電極(13)を、上記基板(10)のうちアノード
(12)に対向する面(10a)の近傍に、且つ上記ア
ノード側(12)からみて上記基板(10)を囲むよう
に配設すると共に、該補助電極(13)に、負電圧(V
2 )を印加する構成とし、且つ上記基板(10)を保
持する保持枠(11)のうち、アノード(12)に対向
する面に、導電性のテープ(30)を、上記基板(10
)を囲撓して且つ剥離可能に貼着すると共に、該導電性
テープ(30)に負電圧(V1 )を印加する構成とし
たことを特徴とする基板の電解メッキ方法。
3. A frame-shaped auxiliary electrode (13) whose inner edge (13a) has substantially the same size as the substrate (10) to be electrolytically plated is placed opposite to the anode (12) of the substrate (10). The auxiliary electrode (13) is provided with a negative voltage (V
A conductive tape (30) is placed on the surface facing the anode (12) of the holding frame (11) which holds the substrate (10) and which applies the voltage (2).
1. A method for electrolytic plating of a substrate, characterized in that the electrically conductive tape (30) is wrapped and removably adhered to the electrically conductive tape (30), and a negative voltage (V1) is applied to the electrically conductive tape (30).
JP868391A 1991-01-28 1991-01-28 Method for electroplating substrate Pending JPH04246200A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP868391A JPH04246200A (en) 1991-01-28 1991-01-28 Method for electroplating substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP868391A JPH04246200A (en) 1991-01-28 1991-01-28 Method for electroplating substrate

Publications (1)

Publication Number Publication Date
JPH04246200A true JPH04246200A (en) 1992-09-02

Family

ID=11699723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP868391A Pending JPH04246200A (en) 1991-01-28 1991-01-28 Method for electroplating substrate

Country Status (1)

Country Link
JP (1) JPH04246200A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1164209A2 (en) * 2000-05-24 2001-12-19 Yamamoto-Ms Co, Ltd. Cathode cartridge of testing device for electroplating and testing device for electroplating
JP2007131931A (en) * 2005-11-11 2007-05-31 Sumitomo Bakelite Co Ltd Plating fixture for printed circuit board
US7767065B2 (en) 2002-09-04 2010-08-03 Atotech Deutschland Gmbh Device and method for electrolytically treating an at least superficially electrically conducting work piece

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55152200A (en) * 1979-05-17 1980-11-27 Fujitsu Ltd Electroplating
JPS5858835A (en) * 1981-10-05 1983-04-07 株式会社東芝 Method of controlling power converter
JPS60187700A (en) * 1984-03-07 1985-09-25 Fujitsu Ltd Power source system for plating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55152200A (en) * 1979-05-17 1980-11-27 Fujitsu Ltd Electroplating
JPS5858835A (en) * 1981-10-05 1983-04-07 株式会社東芝 Method of controlling power converter
JPS60187700A (en) * 1984-03-07 1985-09-25 Fujitsu Ltd Power source system for plating

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1164209A2 (en) * 2000-05-24 2001-12-19 Yamamoto-Ms Co, Ltd. Cathode cartridge of testing device for electroplating and testing device for electroplating
EP1164209A3 (en) * 2000-05-24 2003-02-12 Yamamoto-Ms Co, Ltd. Cathode cartridge of testing device for electroplating and testing device for electroplating
US7767065B2 (en) 2002-09-04 2010-08-03 Atotech Deutschland Gmbh Device and method for electrolytically treating an at least superficially electrically conducting work piece
JP2007131931A (en) * 2005-11-11 2007-05-31 Sumitomo Bakelite Co Ltd Plating fixture for printed circuit board

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