JPS622639A - Manufacture of lead frame with supporting body - Google Patents

Manufacture of lead frame with supporting body

Info

Publication number
JPS622639A
JPS622639A JP60141782A JP14178285A JPS622639A JP S622639 A JPS622639 A JP S622639A JP 60141782 A JP60141782 A JP 60141782A JP 14178285 A JP14178285 A JP 14178285A JP S622639 A JPS622639 A JP S622639A
Authority
JP
Japan
Prior art keywords
metal foil
film
resist pattern
lead frame
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60141782A
Other languages
Japanese (ja)
Inventor
Takao Hashimoto
貴夫 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP60141782A priority Critical patent/JPS622639A/en
Publication of JPS622639A publication Critical patent/JPS622639A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the number of entire processes, by using a photoresist mask, which is provided on the side of the surface of a metal foil, as a plating mask at first, then using the film as a resist pattern for etching, and using a metal as a corrosion resisting material in etching. CONSTITUTION:On one surface of a metal foil 1, a supporting film 2, in which an inserting hole 3 is provided, is laminated. Then, positive photoresist films 4 and 5 are formed on the upper and lower surfaces. An exposing plate is applied on the photoresist film 4. The film 4 is exposed with light including rich ultraviolet rays. After development, a first resist pattern 6 is formed. Then, alloy is electrodeposited on the surface of the metal foil 1, which is exposed through opening parts 7 to a thickness of 10-30mum. Thus, metal electrodeposited parts 8 are formed. A second resist pattern 9 is formed by the similar way. The unnecessary part of the metal foil 1 is etched away. Finally, the remaining resist film is dissolved and removed, and the device is washed with water.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は支持体付きリードフレームの製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a lead frame with a support.

〔従来の技術〕[Conventional technology]

半導体チップのパッドは、外部と電気信号の授受の為1
通常はアルミニウム配線回路のベースの上にクロム層を
500〜100OAの厚さに蒸着によシ形成し、更にそ
の上に銅層を同じく500〜100OAの厚さに蒸着に
より形成し、その上に金層を電着などの方法で10〜2
0μmの厚さに形成することにより作製される。そして
このように作製されたパッドに対して通常は金線による
ボンディングが行なわれる。
The pads of semiconductor chips are used for sending and receiving electrical signals from the outside.
Usually, a chromium layer is formed on the base of the aluminum wiring circuit by vapor deposition to a thickness of 500 to 100 OA, and then a copper layer is formed on the base of the aluminum wiring circuit to a thickness of 500 to 100 OA by vapor deposition. 10-2 gold layers are deposited by electrodeposition or other methods.
It is manufactured by forming it to a thickness of 0 μm. Then, bonding using a gold wire is usually performed on the pads produced in this way.

以上のように、従来、半導体チップの微細なエリアに幾
層もの重金属の層を蒸着法や電着法によシ形成しなけれ
ばならないため、半導体チップのパッドの作製には長時
間を要し、又、工程数が多いことによシ歩留低下をまね
き易いという製造上の問題点があった。
As mentioned above, conventionally, many layers of heavy metals have to be formed in minute areas of semiconductor chips by vapor deposition or electrodeposition, so it takes a long time to fabricate pads for semiconductor chips. In addition, there was a manufacturing problem in that the large number of steps could easily lead to a decrease in yield.

また、半導体用リードフレームのインナーリード先端部
を半導体チップのパッドに達するように長く形成し、ワ
イヤボンディングによラスに直接に半導体チップに接合
することも行なわれたが、その場合においても、例えば
、半田接合による場合、アルミニウム配線回路のベース
の上に、X着によってチタン層と鉛層を夫々500〜1
00OAの厚さに形成してパッドを盛り上げる必要があ
った。
In addition, the tips of the inner leads of semiconductor lead frames were formed long enough to reach the pads of the semiconductor chip, and were bonded directly to the semiconductor chip by wire bonding, but even in that case, for example, , in the case of solder bonding, a titanium layer and a lead layer of 500 to 100% each are placed on the base of an aluminum wiring circuit by
It was necessary to form the pad to a thickness of 00 OA and raise the pad.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

そこで本発明が解決しようとする問題点は半導体チップ
のパッド部の盛9上げがなくても半導体チップとリード
フレーム間の接合が可能な支持体付きリードフレームの
製造方法を提供し、ウニへ作製プロセスの工程数を少な
くし、歩留向上を図ることにある。
Therefore, the problem to be solved by the present invention is to provide a method for manufacturing a lead frame with a support that enables bonding between a semiconductor chip and a lead frame without raising the pad portion of the semiconductor chip. The aim is to reduce the number of process steps and improve yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明者は上記問題点を解決すべく研究の結果、金属箔
の片面に半導体デバイス挿入用孔を開口した支持フィル
ムをラミネートし1次いで金属箔に支持フィルムをラミ
ネートしたものの両面にポジ型フォトレジストを塗布し
、支持フィルム側に塗布形成したポジ型フォトレジスト
膜面に露光用原版をあてがい露光した後、現像してイン
ナーリード先端部のバンプ形成個所に相当する部分が開
口した第1レジストパターンを形成し5次いで第1レジ
ストパターンの開口部より露出する金属箔蘭上に金、銀
、鉛、または金、銀、錫、鉛、クロムなどよりなる合金
を10〜30μ重の厚さ迄電着し、前記電着後、金属箔
側に塗布形成したポジ型°フォトレジスト膜面に露光用
原版をあてがい露光した後、現像してテップキャリアー
テープのインナーリードフレーム、或は半導体用リード
フレームに相当する領域以外の領域が開口した第2レジ
ストパターンを形成し5次いで第2レジストパターン側
よりエ、fングして不要な金属箔部分を腐食除去し、最
後に残存するレジスト膜を剥離することによ)、バンプ
(突出部)をインナーリード先端部に備えた支持体付き
リードフレームを少ない工程数で簡単に得ることができ
ることを見いだし、かかる知見にもとづいて本発明を完
成したものである。
As a result of research to solve the above problems, the inventors of the present invention laminated a support film with holes for semiconductor device insertion on one side of metal foil, and then laminated the support film on the metal foil, but coated both sides with positive photoresist. A master plate for exposure is applied to the surface of the positive photoresist film coated and formed on the support film side, and after exposure, development is performed to form a first resist pattern in which the portion corresponding to the bump formation location at the tip of the inner lead is opened. 5 Then, gold, silver, lead, or an alloy made of gold, silver, tin, lead, chromium, etc. is electrodeposited on the metal foil layer exposed through the opening of the first resist pattern to a thickness of 10 to 30 μm. After the electrodeposition, an original plate for exposure is applied to the surface of the positive type photoresist film coated on the metal foil side, exposed, and then developed to form an inner lead frame of a TEP carrier tape or a lead frame for semiconductors. A second resist pattern is formed in which areas other than the areas to be exposed are open, and then unnecessary metal foil portions are corroded away by etching from the second resist pattern side, and finally the remaining resist film is peeled off. The inventors have discovered that a lead frame with a support having bumps (protrusions) at the tips of inner leads can be easily obtained with a small number of steps, and the present invention has been completed based on this knowledge.

本発明の支持体付きリードフレームの製造方法は金属箔
の片面に半導体デバイス挿入用孔を開口した支持フィル
ムをラミネートする工程と、金属箔に支持フィルムをラ
ミネートしたものの両面にポジ型フォトレジストを塗布
する工程と、支持フィルム側に塗布形成したポジ型フォ
トレジスト膜面に露光用原版をあてがい露光した後、現
像してインナーリード先端部のバンプ形成個所に相当す
る部分が開口した第1レジストパターンを形成する工程
と、第1レジストパターンの開口部よシ露出する金属箔
面上に金、銀、鉛。
The manufacturing method of the lead frame with a support of the present invention includes the steps of laminating a support film with holes for semiconductor device insertion on one side of metal foil, and applying positive photoresist on both sides of the support film laminated to the metal foil. After applying an exposure master plate to the surface of the positive photoresist film coated and formed on the support film side and exposing it to light, it is developed to form a first resist pattern in which the portion corresponding to the bump formation location at the tip of the inner lead is opened. In the process of forming gold, silver, and lead on the metal foil surface exposed through the opening of the first resist pattern.

または金、銀、錫、鉛、クロムなどよυなる合金を10
〜30μmの厚さ迄電着する工程と、前記電着後、金属
箔側に塗布形成したポジ型フォトレジスト膜面に露光用
原版をあてがい露光した後、現像してチップキャリアー
テープのインナーリードフレーム、或は半導体用リード
フレームに相当する領域以外の領域が開口した第2レジ
ストパターンを形成する工程と、第2レジストパターン
側よりエッチングして不要な金属箔部分を腐食除去する
工程と、残存するレジスト膜を剥離する工程とからなる
Or υ alloys such as gold, silver, tin, lead, chromium, etc.
A process of electrodeposition to a thickness of ~30 μm, and after the electrodeposition, an exposure master plate is applied to the surface of the positive photoresist film coated on the metal foil side, exposed, and then developed to form the inner lead frame of the chip carrier tape. , or a step of forming a second resist pattern in which a region other than the region corresponding to the semiconductor lead frame is open, and a step of etching from the second resist pattern side to remove unnecessary metal foil portions by corrosion, It consists of a step of peeling off the resist film.

而して本発明において、金属箔として0.015〜0.
301111の電気良導体で銅を主体とするもの、或←
は銅を主体とする、銅と他の金属種(亜鉛。
In the present invention, the metal foil is 0.015 to 0.0.
301111 electrically conductive material mainly made of copper, or ←
is mainly copper, with copper and other metal species (zinc.

鉄etii*鉛など)の合金、或は鉄、二、ケル。Alloys of iron (e.g. lead, etc.) or iron, metal, etc.

錫、亜鉛、アルミニウム、タンタルなどの金属、或、い
は上記金属種間のクラ、ドタイプのものよりなる金属箔
を適用し得る。
Metal foils made of metals such as tin, zinc, aluminum, tantalum, or metals of the above-mentioned metal types can be used.

次に支持フィルムの材料として厚さ50〜150μmポ
リイミド、ポリエステル、ガラス繊維充填エボキン樹脂
、トリアジン樹脂よシなるものを適用し得る。
Next, as a material for the support film, a material having a thickness of 50 to 150 .mu.m such as polyimide, polyester, glass fiber-filled Evokin resin, triazine resin, etc. can be applied.

次にポジ型フォトレジストとして0FPR−800(東
京応化11り1人z−1350(ヘキストシャハン製)
などのキノン・ジアザイド系フォトレジストを適用し得
る。
Next, as a positive photoresist, 0FPR-800 (Tokyo Ohka 11ri1nin z-1350 (manufactured by Hoechstshahan) was used.
Quinone diazide photoresists such as quinone diazide photoresists can be applied.

次に本発明において第1レジストパターンの開口部よシ
露出する金属箔面上に金、銀、鉛。
Next, in the present invention, gold, silver, and lead are deposited on the metal foil surface exposed through the opening of the first resist pattern.

または金、銀、錫、鉛、クロムなどよりなる合金を10
〜30 Pll の厚さに電着しているのは、この電着
部分はインナーリードのバンプを形成するものであシ、
バンプの突出高さが10μ翼以下であると半導体チッブ
のパッド部との接合がうまくいかないからであυ、一方
30μm以上突出させるのは経済的ではないからである
。また、突起部分(バンプ)があまシ高いと半導体チ。
Or an alloy consisting of gold, silver, tin, lead, chromium, etc.
The reason why it is electrodeposited to a thickness of ~30 Pll is that this electrodeposited part forms the bump of the inner lead.
This is because if the protruding height of the bump is less than 10 μm, the bonding with the pad portion of the semiconductor chip will not be successful.On the other hand, it is not economical to make the bump protrude more than 30 μm. Also, if the protruding parts (bumps) are too high, semiconductor chips may occur.

プのパッド部とバンプ付きインナーリード部の接合の際
に、横方向に曲ったシ、溶融過剰になりはみ出して他の
配線に悪影響をおよぼしかねないからである。
This is because when bonding the pad portion of the bump to the inner lead portion with the bump, the wire bent in the lateral direction may be excessively melted and protrude, which may adversely affect other wiring.

次に本発明において、金、銀などの金属を電着シ、次い
で第2レジストパターンを形成したのちに行なう、不要
な金属箔部分の腐食除去は金属箔は腐食するが金、銀な
どの金属の電着部分は腐蝕しないか、或はわずかじか腐
蝕しない腐蝕液、めっき条件により行なうことが必要で
ある。
Next, in the present invention, after electrodepositing a metal such as gold or silver and then forming a second resist pattern, corrosion removal of unnecessary metal foil parts is performed by electrodepositing a metal such as gold or silver, which corrodes the metal foil. It is necessary to use an etchant and plating conditions that do not corrode or only slightly corrode the electrodeposited portion.

〔作 用〕[For production]

本発明において金属箔側に塗布形成したポジ型フォトレ
ジスト膜は金、銀などの金属をめっきするときのめっき
マスクとしての機能を果すと共に、露光、現像して第2
レジストパターンを形成したのちは、工、チング用マス
クとしての機能を果すものである。
In the present invention, the positive photoresist film coated on the metal foil side functions as a plating mask when plating metals such as gold and silver, and also serves as a plating mask when exposed to light and developed.
After forming the resist pattern, it functions as a mask for etching and etching.

〔実施例〕〔Example〕

以下、本発明の実゛施例につき1図面を参照しながら詳
細に説明する。
Hereinafter, an embodiment of the present invention will be described in detail with reference to one drawing.

先ず、第1図示の如く、厚さ0.015〜0.30諺の
電気良導体で銅を主体とするもの、銅を主体とする銅と
他の金属′Hj、(亜鉛、鉄、錫、鉛など)との合金、
或は鉄、二、ケル、錫、亜鉛。
First, as shown in the first diagram, a good electrical conductor with a thickness of 0.015 to 0.30 and mainly composed of copper, copper mainly composed of copper and other metals (zinc, iron, tin, lead), etc. etc.),
Or iron, two, kel, tin, zinc.

アルミニウム、タンタルなどの金属、或は上記金属種間
のクラ、ドタイブより金属箔(1)の片面に半導体テッ
プなどを挿入する半導体デバイス挿入用孔(3)を開口
した厚さ50〜150μmのポリイミド、ポリエステル
、ガラス繊維充填エポキシ樹脂。トリアジン樹脂などよ
シなる支持フィルム(2)を接着剤を介して接着するか
或←は熱圧着によりラミネートする。
Polyimide with a thickness of 50 to 150 μm with a hole (3) for inserting a semiconductor device into which a semiconductor tip or the like is inserted on one side of the metal foil (1) made of metal such as aluminum or tantalum, or a crack or dowel between the above metals. , polyester, glass fiber filled epoxy resin. A supporting film (2) made of triazine resin or the like is adhered via an adhesive or laminated by thermocompression bonding.

次いで第2図示の如く、金属箔(1)に支持フィルムを
ラミネートしたものの表裏にポジ型フォトレジスト、例
えばキノン・ジアザイド系フォトレジスト(AZ−13
50,ヘキストジャバン製)を塗布し、乾燥してポジ型
フォトレジスト膜+41. (51を形成する。
Next, as shown in the second figure, a positive photoresist such as a quinone diazide photoresist (AZ-13) is applied to the front and back sides of the metal foil (1) laminated with a support film.
50, manufactured by Hoechst Javan) and dried to form a positive photoresist film +41. (Form 51.

次いで支持フィルム(2)側に塗布形成したポジ型フォ
トレジスト膜(4)面に露光用原版をあてがい、紫外線
に富んだ光によって露光した後、現像して第3図示の如
くインナーリード先端部のバンプ形成個所に相当する部
分が開口した第1レジストパターン(6)を形成する。
Next, an exposure original plate is applied to the surface of the positive photoresist film (4) coated on the support film (2) side, exposed to light rich in ultraviolet rays, and developed to form the inner lead tips as shown in the third figure. A first resist pattern (6) is formed in which portions corresponding to bump formation locations are open.

尚、第3図において(7)は第1レジストパターンの開
口部を示す。
In FIG. 3, (7) indicates the opening of the first resist pattern.

次いで第4図示の如く、電着法によシ第1レジストパタ
ーン(6)の開口部(7)より露出する金属箔(1)面
上に金、銀、鉛、または金、銀、錫、鉛。
Next, as shown in the fourth figure, gold, silver, lead, or gold, silver, tin, lead.

クロムなどよりなる合金を10〜30μmの厚さ迄電着
して金、銀などの金属の電着部(8)を形成する。電着
は例えば銅箔上に金を電着する場合にはめつき液として
例えば金めつき液、テンペレジス)7T(日本高純度化
学製)を用い、80℃±1℃、電流密度5人±0.5人
/d−の条件下で行なう。
An alloy made of chromium or the like is electrodeposited to a thickness of 10 to 30 μm to form an electrodeposited portion (8) of metal such as gold or silver. For electrodeposition, for example, when electrodepositing gold on copper foil, use a gold plating liquid (Tempere Regis) 7T (manufactured by Nippon Kojundo Kagaku) as a plating liquid, at 80°C ± 1°C, current density of 5 people ± 0. .5 people/d-.

次いで金属箔(1)側に塗布形成したポジ型フォトレジ
ス+4(5)面に露光用原版をあてがい紫外線に富んだ
光によって露光した後、現像して第5図示の如くt、プ
キャリアーテープのインナーリードフレーム、或は半導
体用リードフレームに相当する領域以外の領域が開口し
た第2レジストパターン(9)を形成する。
Next, an exposure original plate is applied to the +4 (5) side of the positive photoresist coated on the metal foil (1) side, exposed to light rich in ultraviolet rays, and developed to form a carrier tape as shown in Figure 5. A second resist pattern (9) is formed in which a region other than the region corresponding to the inner lead frame or semiconductor lead frame is open.

次いでエツチングして金属箔(11の不要部を第6図示
の如く腐食除去する。金属箔(1)として厚さ35μ虱
の銅箔を用いる場合の工、チング条件圧;1.θ〜1.
5%、腐蝕時間;2.5〜3分間である。
Then, etching is performed to remove unnecessary parts of the metal foil (11) by corrosion as shown in Figure 6. When a copper foil with a thickness of 35 μm is used as the metal foil (1), the etching conditions and pressure are: 1.θ to 1.
5%, corrosion time: 2.5 to 3 minutes.

最後に第7図示の如くアルカリの剥膜液によって残存レ
ジスト膜を溶解剥離し、水洗することにより、第8図示
のようなチ、プキャリアーテープ或は第9図示のような
半導体用リードフレームを得ることが出来る。尚、第8
図、及び−第9図において顛はインナーリード、(Iυ
は金により形成したバンブを示す。
Finally, as shown in Figure 7, the remaining resist film is dissolved and peeled off using an alkaline film removal solution, and washed with water to form a carrier tape as shown in Figure 8 or a semiconductor lead frame as shown in Figure 9. You can get it. Furthermore, the 8th
In Fig. 9, the inner lead, (Iυ
indicates a bump made of gold.

第10図は本発明の製造方法により得られた支持体付き
リードフレームを用いて半導体チ。
FIG. 10 shows a semiconductor chip using a lead frame with a support obtained by the manufacturing method of the present invention.

プを実装した状態を示す。This shows the state in which the module is implemented.

第10図示の如く、半導体チップa3のパッド部α罎の
盛上げがなくてもパッド部o1とインナーリード間の接
合を容易に行なうことができる。
As shown in FIG. 10, the pad portion o1 and the inner leads can be easily bonded without raising the pad portion α of the semiconductor chip a3.

〔発明の効果〕〔Effect of the invention〕

以上詳記した通り、本発明によれば、金属箔面側に設け
たフォトレジスト膜を先ず、金、銀などの金属のめっき
の際のめっきマスクとして利用し、次いでそのフォトレ
ジスト膜をパターン化して工、チング用レジストパター
ンとして用いて二つの用途に用いたこと、及び金属箔面
に付着させた金、銀などの金属をレジストパターンと共
に工、チングの際の耐食性材料として用いたことにより
、全体の工程数をへらし、少ない工程数で長時間を要せ
ずして、インナーリード先端部にバンブを有する支持体
付きリードフレームを簡単に得ることができる。
As detailed above, according to the present invention, the photoresist film provided on the metal foil side is first used as a plating mask when plating metals such as gold and silver, and then the photoresist film is patterned. By using it for two purposes: as a resist pattern for machining and ching, and by using metals such as gold and silver attached to the metal foil surface together with the resist pattern as a corrosion-resistant material during machining and ching. A lead frame with a support having a bump at the tip of the inner lead can be easily obtained by reducing the total number of steps and without requiring a long time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第7図は本発明の製造方法の製造過程の断
面図、第8図、及び第9図は本発明の製造方法によシ製
造した支持体付きリードフレームの平面図、第10図は
リードフレームに半導体チップを実装した状態の断面図
である。 1・・・・・・・・・金属箔 2・・・・・・・・・支持フィルム 3・・・・・・・・・半導体デバイス挿入用孔4.5・
・・・・・ポジ型フォトレジスト膜6・・・・・・・・
・第1のレジストパターン7・・・・・・・・・開口部
1 to 7 are cross-sectional views of the manufacturing process of the manufacturing method of the present invention, FIGS. 8 and 9 are plan views of a lead frame with a support manufactured by the manufacturing method of the present invention, and FIG. The figure is a cross-sectional view of a semiconductor chip mounted on a lead frame. 1...Metal foil 2...Support film 3...Semiconductor device insertion hole 4.5.
...Positive photoresist film 6...
・First resist pattern 7...Opening part

Claims (1)

【特許請求の範囲】[Claims] 金属箔の片面に半導体デバイス挿入用孔を開口した支持
フィルムをラミネートする工程と、金属箔に支持フィル
ムをラミネートしたものの両面にポジ型フォトレジスト
を塗布する工程と、支持フィルム側に塗布形成したポジ
型フォトレジスト膜面に露光用原版をあてがい露光した
後、現像してインナーリード先端部のバンプ形成個所に
相当する部分が開口した第1レジストパターンを形成す
る工程と、第1レジストパターンの開口部より露出する
金属箔面上に金、銀、鉛、または金、銀、錫、鉛、クロ
ムなどよりなる合金を10〜30μmの厚さ迄電着する
工程と、前記電着後、金属箔側に塗布形成したポジ型フ
ォトレジスト膜面に露光用原版をあてがい露光した後、
現像してチップキャリアーテープのインナーリードフレ
ーム、或は半導体用リードフレームに相当する領域以外
の領域が開口した第2レジストパターンを形成する工程
と、第2レジストパターン側よりエッチングして不要な
金属箔部分を腐食除去する工程と、残存するレジスト膜
を剥離する工程とからなることを特徴とする支持体付き
リードフレームの製造方法。
A process of laminating a support film with a hole for semiconductor device insertion on one side of the metal foil, a process of applying a positive photoresist to both sides of the laminated support film on the metal foil, and a process of applying a positive photoresist coated on the side of the support film. A step of applying an exposure master plate to the surface of the mold photoresist film, exposing it to light, and then developing it to form a first resist pattern in which a portion corresponding to the bump formation location at the tip of the inner lead is opened; and an opening in the first resist pattern. A step of electrodepositing gold, silver, lead, or an alloy consisting of gold, silver, tin, lead, chromium, etc. to a thickness of 10 to 30 μm on the more exposed surface of the metal foil, and after the electrodeposition, the metal foil side After applying the exposure master plate to the surface of the positive photoresist film coated on the surface and exposing it,
A process of developing to form a second resist pattern with openings in areas other than the area corresponding to the inner lead frame of the chip carrier tape or the semiconductor lead frame, and etching from the second resist pattern side to remove unnecessary metal foil. 1. A method for manufacturing a lead frame with a support, comprising a step of corroding a portion and a step of peeling off a remaining resist film.
JP60141782A 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body Pending JPS622639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60141782A JPS622639A (en) 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60141782A JPS622639A (en) 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body

Publications (1)

Publication Number Publication Date
JPS622639A true JPS622639A (en) 1987-01-08

Family

ID=15300038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60141782A Pending JPS622639A (en) 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body

Country Status (1)

Country Link
JP (1) JPS622639A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205332A (en) * 1989-02-03 1990-08-15 Toppan Printing Co Ltd Film carrier and manufacture thereof
KR100530755B1 (en) * 1997-11-11 2006-02-28 삼성테크윈 주식회사 The method of making lead frame

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205332A (en) * 1989-02-03 1990-08-15 Toppan Printing Co Ltd Film carrier and manufacture thereof
JP2751308B2 (en) * 1989-02-03 1998-05-18 凸版印刷株式会社 Film carrier and manufacturing method thereof
KR100530755B1 (en) * 1997-11-11 2006-02-28 삼성테크윈 주식회사 The method of making lead frame

Similar Documents

Publication Publication Date Title
US5226232A (en) Method for forming a conductive pattern on an integrated circuit
JP2797542B2 (en) Lead frame manufacturing method
TW200423373A (en) Electronic parts packaging structure and method of manufacturing the same
JP3971500B2 (en) Manufacturing method of wiring board for mounting semiconductor element
JPH07506217A (en) Method of forming electrode connections on manufactured semiconductor die
JP3003624B2 (en) Semiconductor device
JP2809088B2 (en) Protruding electrode structure of semiconductor device and method for forming the protruding electrode
JP2000195984A (en) Semiconductor device, its manufacture carrier substrate therefor and its manufacture
JPH03178152A (en) Molded ic and its manufacture
JPH09283925A (en) Semiconductor device and manufacture thereof
JPH11121646A (en) Semiconductor package and manufacture thereof
JPS622639A (en) Manufacture of lead frame with supporting body
JP3661343B2 (en) Semiconductor device substrate and method of manufacturing the same
JP2003209342A (en) Circuit board and method for manufacturing the same
JPS622643A (en) Manufacture of lead fame with supporting body
JPS622640A (en) Manufacture of lead frame with supporting body
JPS622642A (en) Manufacture of lead frame with supporting body
JP2953163B2 (en) Method for manufacturing substrate for mounting semiconductor device
JPS62272546A (en) Film carrier for semiconductor device
JP2002100655A (en) Tape carrier and semiconductor device using the same
JPH02220440A (en) Manufacture of semiconductor device
JPH0443418B2 (en)
JPH0437042A (en) Film carrier, semiconductor device using film carrier and its manufacture
JPS622644A (en) Manufacture of lead frame with supporting body
GB2244176A (en) Method and apparatus for forming a conductive pattern on an integrated circuit