JPS622642A - Manufacture of lead frame with supporting body - Google Patents

Manufacture of lead frame with supporting body

Info

Publication number
JPS622642A
JPS622642A JP60141785A JP14178585A JPS622642A JP S622642 A JPS622642 A JP S622642A JP 60141785 A JP60141785 A JP 60141785A JP 14178585 A JP14178585 A JP 14178585A JP S622642 A JPS622642 A JP S622642A
Authority
JP
Japan
Prior art keywords
metal foil
resist pattern
gold
lead
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60141785A
Other languages
Japanese (ja)
Inventor
Takao Hashimoto
貴夫 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP60141785A priority Critical patent/JPS622642A/en
Publication of JPS622642A publication Critical patent/JPS622642A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the amount of noble metal used, by forming a thin film comprising gold with a thickness of 5-10mum at the tip part of an inner lead, then lightly etching the thin film, and protruding a bump by 10-30mum. CONSTITUTION:On one surface of a metal foil 1, a supporting film 2, in which a semiconductor-device inserting hole 3 is provided, is laminated. Positive type photoresist films 4 and 5 are formed on the upper and lower surfaces of the metal foil 1. An exposing plate is applied on the surface of a photoresist film 4 and exposure is carried out. After development, a first resist pattern 6 is formed. Then alloy is electrodeposited on the surface of the metal foil 1, which is exposed through holes 7, to a thickness of 10-30mum. A second resist pattern 9 is similarly formed. The, the unnecessary part of the metal foil 1 is etched away. After the first resist pattern is removed, the surface of the exposed metal foil is lightly etched and the electrodeposited part is protruded from the inner lead part other than the electrodeposited part by 10-30mum. Finally, the remaining resist film is dissolved and removed, then the device is washed with water.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 本発明は支持体付きリードフレームの製造方法に関する
。 〔従来の技術〕 半導体チップのパッドは、外部と電気信号の授受の為、
通常はアルミニウム配線回路のベースの上ζニクロム層
を500〜1.000大の厚さに蒸着により形成し更に
その上に銅j―を同じく500〜i、000Aの厚さに
蒸着により形成しその上書=金層を電着などの方法で1
0〜20)1mの厚さに形成することにより作製される
。そしてこのように作製されたパッドに対して金線によ
るボンディングが行なわれる。 以上のように、従来、半導体チップの微細なエリアC:
幾層もの重金属の層を蒸暑法や電電法により形成しなけ
ればならないため、半導体チップのパッドの作製には長
時間を要し、又、工程数が多いことにより歩留低下をま
ねき易いという問題点があった。 また、半導体用リードフレームのインナーリード先端部
を半導体チップのパッドに達するように長(形成し、ワ
イヤボンディングによらずに直接に半導体チップに接合
することも行なわれたが、その場合においても、例えば
、半田接合による場合、アルミニウム配線回路のベース
の上に、蒸暑によってチタン層と鉛層を夫々500〜1
.000 hの厚さに形成してパッドを盛り上げる必要
があった。 〔◆発明が解決しようとする問題点〕 そこで本発明が解決しようとする問題点は半導体チップ
のパッド部の盛り土げがなくても半導体チップとリード
フレーム間の接合が可能である支持体付きリードフレー
ムの製造方法を提供し、クエへ作製プロセスの工程数を
少なくし、歩留同上を図ることにある。 〔問題点を解決するための手段〕 本発明者は上記問題点を解決すべく研究の結果、金属箔
の片面(二半導体デバイス押入用孔を開口した支持フィ
ルムをラミネートし、次いで金属箔に支持フィルムをラ
ミネートしたものの両面にポジ型フォトレジストを聖夜
し、次いで支持フィルム側に塗布形成したポジ型フオト
レジス)M面に露光用原版をあてがい露光した後、現像
してインナーリード先端部のバンプ形成個所C二相当す
る部分が開口した第ルジストパターンを形成し、第ルジ
ストパターンの開口部より露出する金属箔面に金、銀、
鉛、または金、銀、錫、鉛、クロムなどよりなる合金を
5〜10μmの厚さ迄電着し、前記電電後、金属箔側(
=塗布形成したポジ型フォトレジスト膜面に鑓元用原版
をあてがい露光した後、現像してチップキャリアテープ
のインナーリードフレーR1或―は半導体用リードフレ
ームに相当する領域以外の領“域が開口した第2レジス
トパターンを形成し、第2レジストパターン側よりエツ
チングして不要な金属箔部分を腐蝕除去し、不要な金属
箔部分の除去後に第ルジストパターン側から全面露光し
、次いで現像したのち、露出する金属箔面な軽くエツチ
ングして前記金などを電着した部分をそれ以外のインナ
ーリード部分よりも10〜60μ嫉出させ、最後C二残
存するレジスト膜を剥離することにより、インナーリー
ド先端部にバンプ(突出部)を備えていて、半導体チッ
プのパッド部か盛り上がっていなくても接合が可能であ
る支持体付きリードフレームを少ない工程数で簡単に得
ることができることを見いだし、かかる知見にもとづい
て本発明を完成したものである。 本発明の支持体付きリードフレームの製造方法は金属箔
の片面に半導体デバイス挿入用孔を開口した支持フィル
ムをラミネートする工程と、金属箔に支持フィルムをラ
ミネートしたものの。 両面にポジ型フォトレジストを袈布する工程と、支持フ
ィルム側に塗布形成したポジ型フォトレジスト膜面に露
光用原版をあてがい露光した後、現像してインナーリー
ド先端部のバンプ形成個所;;相当する部分が開口した
第ルジストパターンを形成する工程と、第ルジストパタ
ーンの開口部より露出する金JiI4陥面に金、銀、鉛
、または金、銀、錫、鉛、クロムなどよりなる合金を5
〜10μmの厚さ迄電着する工程と、削配電着後、金属
箔側(二車布形成したポジ型フォトレジスト膜面に露光
用原版をあてがい結党した後、現像してチップキャリア
テープのインナーリードフレーム、或いは半導体用リー
ドフレームに相当する領域以外の領域が開口した男2レ
ジストパターンを形成する工程と、第2レジストパター
ン側よりエツチングして不要な金属箔部分を腐蝕除去す
る工程と、不要な金属箔部分の除去後に第ルジストパタ
ーン側から全面露光し、次いで現像したのち、露出する
金属箔面を軽くエツチングして前記金などを電着した部
分をそれ以外゛のインナーリード部分よりも10〜50
μm朶出させる工程と残存するレジスト膜を剥離する工
程とからなる。 而して本発明において、金属箔として0.015〜0.
30嘗諺の電気良導体で銅を主体とするもの、或は剃を
主体とする、銅と他の金属種(亜鉛、鉄、錫、鉛など)
の合金、或は鉄、ニッケル、錫、亜鉛、アルミニウム、
タンタルなどの金属、或は上記金属種間のクラッドタイ
プのものよりなる金属箔を適用し得る。 次に支持フィルムの材料として厚さ20〜2.000μ
mのポリイミド、ポリエステル、ガラス繊維充填ヱポキ
シ樹脂、トリアジン樹脂よりなるものを適用し得る。 次にポジ型フォトレジストとして0FPR−800(東
京応化製)、AZ−1350(ヘキストジャバン製)な
どのキノン・ジアザイド系フォトレジストを適用し得る
。 次に本発明において、不要な金属箔部分の除去後(=第
2レジストパターン側から全面露光し、次いで現像した
のち、露出する金属箔面な軽くエツチングして傘、銀な
どを電着した部分をそれ以外のインナーリード部分より
も10〜30μm突出させるのはバンプの突出高さが1
0μm以下であると半導体チップのパッド部との接合が
うまくいかないからであり、一方、30μ簿以上突出さ
せるのは経済的でないからである。また、突起部分(バ
ンプ)があまり高いと半導体チップのパッド部とバンプ
付きインナーリード部の接合の際に横方向に曲りたり、
溶融過剰になり、はみ出して他の配線に悪影響を8よば
しかねないからである。 次に本発明において金、銀などの金属を電着し、次いで
第2レジストパターンを形成したのちに行なう、不要な
金属箔部分の腐食除去工程及び不要な金tf4箔部分の
除去後に第2レジストパターン側から全面露光し、次い
で現像したのち、露出する金属箔面を怪くエツチングす
る工程は金属箔は腐蝕するが金、銀などの金属の電電部
分は腐蝕しないか、或はわずかじか腐蝕しない腐蝕液、
めっき条件により行なうことが必要である。 〔作 用〕 本発明シーおいて金属箔側に塗布形成したポジ型フォト
レジスト膜は金、銀などの金属をめっきするときのめつ
きマスクとしての機能を果すと共に、露光、現像して第
2レジストパターンを形成したのちは、エツチング用マ
スクとしての機能を果すものである。 〔実施例〕 以下、本発明の実施例につき、図面を参照しながら詳細
に説明する。 先ず、第1図示の如く、厚さ0.015〜0.60慣嘗
の電気良導体で銅を主体とするもの、銅を主体とする′
−と他の金属種(亜鉛、鉄、錫、鉛なと)との合金、或
は鉄、ニッケル、錫、亜鉛、アルミニウム、ダンタルな
どの金属、或は上記金属種間のクラッドタイプより金r
IAffi (11の片面に半導体・チップなどを挿入
する半導体デバイス挿入用孔(3)を開口した厚さ20
〜2,000μmのポリイミド、ポリエステル、ガラス
繊維充填エボ看(二よりラミネートする。 次いで第2図示゛の如く、金属箔(1)に、支持フィル
ム(2)をラミネートしたものの表裏にポジ型フォトレ
ジスト、例えばキノンφジアザイド系フォトレジスト(
AZ−1350、ヘキストジャパン製)を塗布し、乾燥
してポジ型フォトレジスト膜(41(5)を形成する。 次いで支持フィルム(2)側に塗布形成したポジ型フォ
トレジスト膜(4)面に露光用原版をあてがい露光した
後、現像して第6図示の如くインナーリード部端部のバ
ンプ形成個所に相当する部分が開口した第2レジストパ
ターン(6)を形成する。尚、第6図において(7)は
$ルジストパターンの開口部を示す。 次いで第4図示の如く、電着法により第2レジストパタ
ーン16+の開口部(7)より露出する金属w3(11
面上に金、銀、鉛、または金、銀、錫、クロムなどより
なる合金を10〜30μ罵の厚さ迄電着して金、銀など
の金属の電着部(8)を形成する。 電着は例えば銅箔上に金を電着する場合には、めっき液
として例えば金めつき液、テンベレジス)7’r(日本
高純度化学製)を用い、80゛C±1 ”C%電流密度
5A±α5*/am’ の条件下で行なう。 次いで金属箔(1)側ζ二墜布形成したポジ型フォトレ
ジスト膜(9)面に露光用原版をあてがい紫外線により
IG元した後、現像して第5図示の如くテップキャリア
ーテープのインナーリードフレーム、或参は半導体用リ
ードフレームシニ相当する領域以外、の領域が開口した
tJS2レジストパターン(9)を形成する。 次いでエツチングして金fR箔(1)の不要部を第6図
示の如く腐蝕除去する。金属箔
[Industrial Field of Application] The present invention relates to a method for manufacturing a lead frame with a support. [Prior art] The pads of semiconductor chips transmit and receive electrical signals from the outside.
Usually, a ζ nichrome layer is formed on the base of the aluminum wiring circuit by vapor deposition to a thickness of 500 to 1,000 A, and then copper is formed on top of it by vapor deposition to a thickness of 500 to 1,000 A. Overwriting = gold layer 1 by electrodeposition etc.
0 to 20) It is manufactured by forming it to a thickness of 1 m. Then, bonding with gold wire is performed to the pads produced in this way. As mentioned above, conventionally, the fine area C of a semiconductor chip:
Since multiple layers of heavy metals must be formed using a steaming method or an electric method, it takes a long time to manufacture pads for semiconductor chips, and the large number of steps can easily lead to a decrease in yield. There was a point. In addition, the tips of the inner leads of semiconductor lead frames were formed long enough to reach the pads of the semiconductor chip, and were bonded directly to the semiconductor chip without wire bonding. For example, in the case of solder bonding, a titanium layer and a lead layer each have a thickness of 50 to 1
.. It was necessary to form the pad to a thickness of 0.000 h and raise the pad. [◆Problems to be Solved by the Invention] Therefore, the problems to be solved by the present invention are to provide a lead with a support that enables bonding between a semiconductor chip and a lead frame without the need for bulges on the pads of the semiconductor chip. It is an object of the present invention to provide a method for manufacturing a frame, to reduce the number of steps in the process of manufacturing a frame, and to improve the yield. [Means for Solving the Problems] As a result of research to solve the above problems, the present inventor laminated a supporting film with holes for inserting two semiconductor devices on one side of metal foil, and then supported it on the metal foil. A positive photoresist is applied to both sides of the laminated film, and then applied to the support film side (positive photoresist). After applying an exposure master plate to the M side and exposing it, it is developed to form the bump formation area at the tip of the inner lead. Form a first Lujist pattern with an opening in the portion corresponding to C2, and apply gold, silver,
Lead or an alloy consisting of gold, silver, tin, lead, chromium, etc. is electrodeposited to a thickness of 5 to 10 μm, and after the electrodeposition, the metal foil side (
= After exposing the surface of the coated positive photoresist film to light, it is developed to open the area other than the area corresponding to the inner lead flake R1 of the chip carrier tape or the semiconductor lead frame. A second resist pattern is formed, etched from the second resist pattern side to remove unnecessary metal foil portions by corrosion, and after removing the unnecessary metal foil portions, the entire surface is exposed from the second resist pattern side, and then developed. The exposed metal foil surface is lightly etched to make the part where the gold or the like is electrodeposited protrude by 10 to 60 μm from the rest of the inner lead part, and finally the remaining resist film is peeled off to form the inner lead. We have discovered that it is possible to easily obtain a lead frame with a support, which has a bump (protrusion) at the tip and can be bonded even if the pad part of a semiconductor chip is not raised, with a small number of steps, and we have developed this knowledge. The present invention has been completed based on the above.The method for producing a lead frame with a support according to the present invention includes the steps of laminating a support film with a hole for inserting a semiconductor device on one side of a metal foil, and laminating a support film on the metal foil. A process of covering both sides with positive photoresist, applying an exposure master plate to the surface of the positive photoresist film coated on the support film side, exposing it, and developing it to remove the bumps at the tips of the inner leads. Formation location: A process of forming a first Lujist pattern with openings in the corresponding portions, and applying gold, silver, lead, or gold, silver, tin, lead, 5 alloys made of chromium etc.
After the process of electrodeposition to a thickness of ~10 μm and the electrodeposition by cutting, an original plate for exposure is applied to the metal foil side (the surface of the positive photoresist film formed on the two-wheeled cloth) to form a layer, and then developed to form the inner layer of the chip carrier tape. A step of forming a male 2 resist pattern with openings in areas other than the area corresponding to the lead frame or semiconductor lead frame, a step of etching from the second resist pattern side to remove unnecessary metal foil portions, and an unnecessary process. After removing the metal foil portion, the entire surface is exposed to light from the first resist pattern side, and then developed, the exposed metal foil surface is lightly etched, and the portion where the gold etc. has been electrodeposited is exposed more than the other inner lead portion. 10-50
The process consists of a step of oozing out micrometers and a step of peeling off the remaining resist film. In the present invention, the metal foil is 0.015 to 0.0.
30 years of good electrical conductors mainly made of copper, or mainly made of copper and other metals (zinc, iron, tin, lead, etc.)
alloys, or iron, nickel, tin, zinc, aluminum,
A metal foil made of a metal such as tantalum or a clad type between the above-mentioned metals can be used. Next, as the material for the support film, the thickness is 20 to 2.000μ.
Polyimide, polyester, glass fiber-filled epoxy resin, and triazine resin may be used. Next, as a positive photoresist, a quinone diazide photoresist such as 0FPR-800 (manufactured by Tokyo Ohka) or AZ-1350 (manufactured by Hoechst Java) can be used. Next, in the present invention, after removing the unnecessary metal foil portion (= fully exposed from the second resist pattern side, then developing, the exposed metal foil surface is lightly etched and the portion where caps, silver, etc. are electrodeposited) The protrusion height of the bump is 1 to make the bump protrude 10 to 30 μm higher than the other inner lead parts.
This is because if it is less than 0 μm, the bonding with the pad portion of the semiconductor chip will not be successful, and on the other hand, it is not economical to make it protrude more than 30 μm. In addition, if the protruding portion (bump) is too high, it may bend laterally when bonding the pad portion of the semiconductor chip and the inner lead portion with the bump.
This is because excessive melting may occur, causing it to protrude and adversely affect other wiring. Next, in the present invention, a metal such as gold or silver is electrodeposited, and then a second resist pattern is formed, followed by a corrosion removal process of unnecessary metal foil parts, and a second resist after removing unnecessary gold TF4 foil parts. The process of exposing the entire surface from the pattern side, then developing, and then etching the exposed metal foil surface will corrode the metal foil, but the electrical parts of metals such as gold and silver will not corrode, or will corrode only slightly. No corrosive liquid,
It is necessary to perform this depending on the plating conditions. [Function] The positive photoresist film coated and formed on the metal foil side in the sheet of the present invention functions as a plating mask when plating metals such as gold and silver, and also functions as a plating mask when exposed and developed. After the resist pattern is formed, it functions as an etching mask. [Example] Hereinafter, examples of the present invention will be described in detail with reference to the drawings. First, as shown in the first diagram, a good electrical conductor with a thickness of 0.015 to 0.60 mm and mainly composed of copper;
- alloys with other metals (zinc, iron, tin, lead, etc.), or metals such as iron, nickel, tin, zinc, aluminum, dantal, or cladding types between the above metals.
IAffi (thickness 20 mm with a semiconductor device insertion hole (3) for inserting a semiconductor/chip etc. on one side of 11)
~2,000 μm polyimide, polyester, glass fiber filled Evo film (laminated with two layers. Then, as shown in the second figure, the metal foil (1) is laminated with the support film (2), and a positive photoresist is applied on the front and back sides of the film. , for example, quinone φ diazide photoresist (
AZ-1350, manufactured by Hoechst Japan) is applied and dried to form a positive photoresist film (41(5)).Next, a positive photoresist film (4) coated on the support film (2) side is coated. After the exposure master is applied and exposed, it is developed to form a second resist pattern (6) in which the portion corresponding to the bump formation location at the end of the inner lead portion is open as shown in FIG. 6. (7) shows the opening of the $ resist pattern. Next, as shown in the fourth figure, metal w3 (11
Electrodeposit gold, silver, lead, or an alloy of gold, silver, tin, chromium, etc. on the surface to a thickness of 10 to 30 μm to form an electrodeposited portion (8) of metal such as gold or silver. . For electrodeposition, for example, when electrodepositing gold on copper foil, use a gold plating solution such as Tenbe Regis 7'r (manufactured by Nippon Kojundo Kagaku) as a plating solution, and apply a current of 80゛C±1''C%. The process is carried out under the condition of a density of 5A±α5*/am'. Next, an exposure master plate is applied to the surface of the positive photoresist film (9) formed on the metal foil (1) side, exposed to UV light, and then developed. Then, as shown in Figure 5, a tJS2 resist pattern (9) is formed in which areas other than the area corresponding to the inner lead frame of the TEP carrier tape or the semiconductor lead frame are open.Next, it is etched to form a gold fR foil. (1) Unnecessary parts are corroded and removed as shown in Figure 6. Metal foil

【1】として厚さ35μ
肩の銅箔を用いる場合のエツチング条件を例示すればエ
ツチング液; ysoノ5水溶液(65〜40°Brf
f1蝕温度;70〜so”c、スフレイ圧; t O〜
t 5111/C11l 、腐蝕時間;z5〜3分間で
ある。 次いで第7図示の如く、第ルジストパターン側から紫外
線にて全面露光し、次いで現像して、第ルジストパター
ン゛を除去したのち、露出する金属箔面を軽くエツチン
グして金などを電着した部分をそれ以外のインナーリー
ド部分よりも10〜30μm突出させる。 最後に第8図示の如く剥膜液によって残存レジスト膜を
溶解剥離し、水洗すること(−より第9図示のようなチ
ップキャリアーテープ或泗は第10図示のような半導体
用リードフレームを得ることが出来る。尚、N49図、
及び第10図において(IGはインナーリードlはバン
プを示す。 第11図は本発明の製造方法により得られた支持体付き
リードフレームを用いて半導体チップを実装した状態を
示す。 第11図示の如く、半導体チップ■のパッド部0の盛土
がなくてもパッド部(至)とインナーリード間の接合を
行なうことができる。 〔発明の効果〕 。 以上詳記した通り、本発明によれば金属箔面側に設けた
フオトレジス)IIQを先ず、金、銀などをめっきの際
のめつきマスクとして利用し、次いでそのフォトレジス
ト膜をパターン化してエツチング用レジストパターンと
して用いて二つの用途に用いたこと、及びパターンと共
にエツチングの際耐食性材料として用いたことにより全
体の工程数をへらしたこと、及び5〜10μmの金など
の薄膜をインナーリード先端部に形成し、次いで軽くエ
ツチングすることによりバンプを10〜30μm突出さ
せる方法を取ることにより短いめっき時間でバンプを形
成したことにより、少ない工程数で長時間を要せずして
、しかも少ない金、銀などの貴金属の使用量でインナー
リード先端部にバンプを有する支持体付きリードフレー
ムを得ることができる。
[1]Thickness 35μ
An example of etching conditions when using shoulder copper foil is etching solution;
f1 Eclipse temperature; 70~so”c, souffle pressure; t O~
t5111/C11l, corrosion time; z5 to 3 minutes. Next, as shown in Figure 7, the entire surface is exposed to ultraviolet light from the first resist pattern side, and then developed to remove the first resist pattern.The exposed metal foil surface is then lightly etched to electrodeposit gold or the like. This portion is made to protrude 10 to 30 μm from the other inner lead portions. Finally, as shown in Fig. 8, the remaining resist film is dissolved and peeled off using a film stripping solution, and washed with water. can be done.In addition, figure N49,
and in FIG. 10 (IG indicates an inner lead l indicates a bump. FIG. 11 shows a state in which a semiconductor chip is mounted using a lead frame with a support obtained by the manufacturing method of the present invention. As described in detail above, according to the present invention, the bonding between the pad part (to) and the inner lead can be performed even without the embankment of the pad part 0 of the semiconductor chip (2). The photoresist (IIQ) provided on the foil side was first used as a plating mask when plating gold, silver, etc., and then the photoresist film was patterned and used as a resist pattern for etching, for two purposes. The overall number of steps was reduced by using it together with the pattern as a corrosion-resistant material during etching, and the bumps were removed by forming a thin film of 5 to 10 μm of gold or the like on the tip of the inner lead and then lightly etching it. By forming bumps in a short plating time by protruding 10 to 30 μm, the tip of the inner lead can be formed with fewer steps and less time, and with less precious metals such as gold and silver. A lead frame with a support having bumps can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第8図は本発明の製造方法の製造過程の断
面図、第9図、及び第10図は本発明の製造方法により
製造した支持体付きり−ドフレームの平面図、第11図
はリードフレーム(二手導体チップを実装した状態の断
面図である。 1・・・・・・・・・・・・・・・・・・金属箔2・・
・・・・・・・・・・・・・・・・支持フィルム3・・
・・・・・・・・・・・・・・・・半導体デバイス挿入
用孔4.5・・・・・・・・・・・・ポジ型フォトレジ
スト膜6・・・・・・・・・・・・・・・・・・第1の
レジストパターン7・・・・・・・・・・・・・・・、
・・・開口部8・・・・・・・・・・・・・・・・・・
金、銀などの金属9・・・・・・・・・・・・・・・・
・・第2のレジストパターン特許出願人 大日本印刷株
式会社 代理人 弁理士   小 西 淳 美 第1図 第4図 第5図 第 6 図 第7図 第8図 第9図 第10図
1 to 8 are cross-sectional views of the manufacturing process of the manufacturing method of the present invention, FIGS. 9 and 10 are plan views of a supported frame manufactured by the manufacturing method of the present invention, and FIG. The figure is a cross-sectional view of a lead frame (with a two-handed conductor chip mounted on it. 1. Metal foil 2.
・・・・・・・・・・・・・・・・Support film 3・・
・・・・・・・・・・・・・・・Semiconductor device insertion hole 4.5・・・・・・・・・Positive photoresist film 6・・・・・・・・・・・・・・・・・・First resist pattern 7・・・・・・・・・・・・・・・
・・・Opening 8・・・・・・・・・・・・・・・・・・
Metals such as gold and silver 9・・・・・・・・・・・・・・・
...Second resist pattern patent applicant Dai Nippon Printing Co., Ltd. Agent Atsumi Konishi, patent attorney Figure 1 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

【特許請求の範囲】[Claims] 金属箔の片面に半導体デバイス挿入用孔を開口した支持
フィルムをラミネートする工程と、金属箔に支持フィル
ムをラミネートしたものの両面にポジ型フォトレジスト
を塗布する工程と、支持フィルム側に塗布形成したポジ
型フォトレジスト膜面に露光用原版をあてがい露光した
後、現像してインナーリード先端部のバンプ形成個所に
相当する部分が開口した第1レジストパターンを形成す
る工程と、第1レジストパターンの開口部より露出する
金属箔面に金、銀、鉛、または金、銀、錫、鉛、クロム
などよりなる合金を5〜10μmの厚さ迄電着する工程
と、前記電着後、金属箔側に塗布形成したポジ型フォト
レジスト膜面に露光用原版をあてがい露光した後、現像
してチップキャリアテープのインナーリードフレーム、
或は半導体用リードフレームに相当する領域以外の領域
が開口した第2レジストパターンを形成する工程と、第
2レジストパターン側よりエッチングして不要な金属箔
部分を腐蝕除去する工程と、不要な金属箔部分の除去後
に第1レジストパターン側から全面露光し、次いで現像
したのち、露出する金属箔面を軽くエッチングして前記
金などを電着した部分をそれ以外のインナーリード部分
よりも10〜30μm突出させる工程と残存するレジス
ト膜を剥離する工程とからなることを特徴とする支持体
付きリードフレームの製造方法。
A process of laminating a support film with a hole for semiconductor device insertion on one side of the metal foil, a process of applying a positive photoresist to both sides of the laminated support film on the metal foil, and a process of applying a positive photoresist coated on the side of the support film. A step of applying an exposure master plate to the surface of the mold photoresist film, exposing it to light, and then developing it to form a first resist pattern in which a portion corresponding to the bump formation location at the tip of the inner lead is opened; and an opening in the first resist pattern. A step of electrodepositing gold, silver, lead, or an alloy of gold, silver, tin, lead, chromium, etc. to a thickness of 5 to 10 μm on the more exposed surface of the metal foil, and after the electrodeposition, a step of electrodepositing gold, silver, lead, or an alloy consisting of gold, silver, tin, lead, chromium, etc. After applying an exposure master plate to the surface of the positive photoresist film and exposing it to light, it is developed to form the inner lead frame of the chip carrier tape.
Alternatively, a step of forming a second resist pattern in which a region other than the region corresponding to the semiconductor lead frame is open, a step of etching from the second resist pattern side to remove unnecessary metal foil portions, and a step of removing unnecessary metal foil. After removing the foil portion, the entire surface is exposed from the first resist pattern side, and then developed, and then the exposed metal foil surface is lightly etched so that the portion where the gold or the like is electrodeposited is 10 to 30 μm thicker than the other inner lead portion. A method for producing a lead frame with a support, comprising the steps of protruding the lead frame and peeling off the remaining resist film.
JP60141785A 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body Pending JPS622642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60141785A JPS622642A (en) 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60141785A JPS622642A (en) 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body

Publications (1)

Publication Number Publication Date
JPS622642A true JPS622642A (en) 1987-01-08

Family

ID=15300102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60141785A Pending JPS622642A (en) 1985-06-28 1985-06-28 Manufacture of lead frame with supporting body

Country Status (1)

Country Link
JP (1) JPS622642A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563202B1 (en) 1997-07-01 2003-05-13 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563202B1 (en) 1997-07-01 2003-05-13 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus

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