JPH04245361A - Data processor - Google Patents

Abstract

PURPOSE:To process data without being affected by access by a CPU as to the data processor including a dual-port RAM, the CPU which sets and refers to data in the dual-port RAM, and a data processing circuit which reads and updates the contents of the dual-port RAM periodically. CONSTITUTION:This data processor is equipped with an adding and subtracting circuit 4 which performs addition and subtraction for the address operation of a data processing circuit 3 and an addition and subtraction control circuit 5 which monitors the access state of the dual-port RAM 2 and outputs a control signal for the address operation to the addition and subtraction control circuit 4 so that the data processing is performed even when the CPU 1 is in access operation.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a dual port RAM
, a CPU that sets and references data for this dual port RAM, and a CPU that periodically sets and references data for this dual port RAM.
The present invention relates to a data processing device including a data processing circuit that reads and updates the contents of an AM.

For example, in circuits such as timers that periodically process data, their processing capacity tends to increase as the scale of the system increases. For this reason, CPU data setting and reference operations are frequently performed, so
An access control means is required that can periodically process data without being affected by accesses from the PU.

[0003] Furthermore, as systems become larger and more sophisticated, the address space handled by the CPU also tends to increase, and for this reason, in order to restart the system quickly, it is necessary to reset the memory part quickly. It is necessary to do it.

0004

2. Description of the Related Art FIG. 9 is a block diagram focusing on access control in a conventional data processing device. In FIG. 9, 101 is a CPU, 102 is a dual port RAM, 103 is a data processing circuit, and 104 is a Although it is an operation control circuit, the CPU 101 is a dual port RAM
The data processing circuit 103 periodically sets and references data to the dual port R.
The operation control circuit 104 reads and updates the contents of the AM 102.
It controls the operation of the data processing circuit 103 in response to a busy signal (BUSY) generated when two ports A and B are accessed simultaneously.When a busy signal is received, a stop flag is issued to the data processing circuit 103. It has become. Note that the data processing circuit 103 and the operation control circuit 10
4 operates in response to a clock. Also, in this case, CP
U101 and the data processing circuit 103 have an address generation function.

Next, the operation will be explained using FIG. 10. Now, when the CPU access address is at address n and the data processing circuit access address becomes address n, the dual port RAM 102 outputs a busy signal, so the operation control circuit 104 sets a stop flag.

[0006] When the stop flag is set in this manner, the data processing circuit 103 stops operating and data reading and writing are prohibited.

Thereafter, when the CPU 101 finishes accessing the n address, the busy signal is turned off, the stop flag is reset, and the n address is processed in the cycle (S2) following the cycle (S1).

FIG. 11 is a block diagram of a conventional data processing device focusing on reset.
1, 101 is a CPU, 102 is a dual port RAM, 103 is a data processing circuit, and 104 is an address generation circuit. In this case as well, the CPU 101 sets and references data in the dual port RAM 102, and the data processing circuit 103 periodically reads and updates the contents of the dual port RAM 102. Also,
The address generation circuit 104 is a dual port RAM 10
It is assumed that the CPU 101 also has an address generation function.

The reset operation is performed as follows. In other words, the reset signal causes the CPU to
101, data processing circuit 103, address generation circuit 10
4 is initialized, and a reset operation is performed through port A of the dual port RAM 102 by the initialization program of the CPU 101.

0010

[Problems to be Solved by the Invention] However, in the access control means in the conventional data processing device as described above, when the CPU is accessing, the data processing circuit stops operating until the CPU finishes the access. , data processing is performed in the next cycle, so if the CPU is frequently accessed, the CPU
Discrepancies in data processing cycles are accumulated for each U access.

[0011] Furthermore, in the reset means in the conventional data processing apparatus as described above, address access is sequentially performed from address 0 to the end at the time of resetting, so there is a problem that the resetting operation takes a long time.

The present invention was devised in view of the above problems, and an object of the present invention is to provide a data processing device that can perform data processing without being affected by CPU access.

Another object of the present invention is to provide a data processing device that does not require time for reset operation.

[0014]

[Means for Solving the Problem] FIG. 1 is a block diagram of the principle of the invention according to claim 1, and in this FIG.
2 is a dual port RAM, and 3 is a data processing circuit. First, the CPU 1 sets and refers to data in the dual port RAM 2, and the data processing circuit 3 periodically reads data from the dual port RAM 2. The contents are read and updated. Note that the dual port RAM 2 has a port A on the CPU side and a port B on the data processing circuit side, and can be accessed from either port.

Reference numeral 4 denotes an addition/subtraction circuit that performs addition/subtraction in order to perform address operations in the data processing circuit 3; 5 is an addition/subtraction control circuit; this addition/subtraction control circuit 5 monitors the access state of the dual port RAM 2; so that data processing can continue even if the
It outputs a control signal for performing address operations to the addition/subtraction circuit 4.

FIG. 2 is a block diagram of the principle of the invention according to claim 2. In FIG. 2, the CPU 1, dual port RAM 2, and data processing circuit 3 are the same as those according to claim 1.

Now, in FIG. 2, 6 is an address generation circuit, and this address generation circuit 6 generates an address from address 0 at the time of reset, and supplies it from port B on the data processing circuit side of the dual port RAM 2. .

7 is a reset operation display circuit that indicates that the reset operation is in progress; 8 is a CPU disconnection circuit; the CPU disconnection circuit 8 causes the reset operation display circuit 7 to disconnect the dual port RA from the CPU 1 during the reset operation;
This is to separate M2.

Reference numeral 9 denotes an address inverting circuit, and this address inverting circuit 9 inverts the address of the address generation circuit 6 during the reset operation by the reset operation display circuit 7 and supplies it from port A on the CPU side of the dual port RAM 2. It is something.

Reference numeral 10 denotes an intermediate address detection circuit, and this intermediate address detection circuit 10 detects that the address of the address generation circuit 6 becomes the intermediate address of the dual port RAM 2.

FIG. 3 is a block diagram of the principle of the invention according to claim 3, and in FIG.
The same applies to

Now, in FIG. 3, 11 is an address generating means, and this address generating means 11 generates 0 at the time of reset.
An address is generated from the address and supplied from port A on the CPU side of the dual port RAM 2.

Reference numeral 12 is a reset operation display circuit that indicates that the reset operation is in progress, and 13 is a data processing circuit disconnection circuit. This is to separate the dual port RAM 2 from the processing circuit 3.

Reference numeral 14 denotes an address inverting circuit, and this address inverting circuit 14 inverts the address of the address generating means 11 during the reset operation by the reset operation display circuit 12 and supplies it from the data processing circuit side port B of the dual port RAM 2. It is something to do.

Reference numeral 15 denotes intermediate address detection means, and this intermediate address detection means 15 detects that the address of the address generation means 11 has become an intermediate address of the dual port RAM 2.

Here, the address generating means 11 and the intermediate address detecting means 15 are provided in the CPU 1 (claim 4).

[0027]

[Operation] In the data processing device according to the invention as set forth in claim 1, the addition/subtraction control circuit 5 monitors the access state of the dual port RAM 2, and the addition/subtraction circuit 4 changes the access address of the data processing circuit 3 based on the monitoring result. By operating, the address of unprocessed data is set and CPU1
Data processing can continue even if the data is being accessed.

Further, in the data processing device according to the second aspect of the invention, when the reset signal is input, addresses starting from address 0 are sequentially generated from the address generation circuit 6, and this address is used as the data in the dual port RAM 2. At the same time, when the reset operation display circuit 7 indicates that the reset operation is in progress, the CPU disconnection circuit 8 disconnects the dual port RAM 2 from the CPU 1, and The inversion circuit 9 inverts the address of the address generation circuit 6 and supplies it from port A of the dual port RAM 2 on the CPU side. Then, when the intermediate address detection circuit 10 detects that the address of the address generation circuit 6 has become the intermediate address of the dual port RAM 2, the reset ends.

Furthermore, in the data processing apparatus according to the third and fourth aspects of the invention, when the reset signal is input, the CPU 1
Addresses starting from address 0 are sequentially generated from the address generating means 11 in the internal memory, and these addresses are supplied from port A on the CPU side of the dual port RAM 2. At the same time, the reset operation display circuit 12 indicates the reset operation. CPU disconnection circuit 1
3 separates the dual port RAM 2 from the data processing circuit 3, and the address inversion circuit 14 inverts the address of the address generation means 11 to connect the dual port RAM 2 to the data processing circuit 3.
The signal is supplied from port B on the data processing circuit side of M2.

When the intermediate address detecting means 15 in the CPU 1 detects that the address of the address generating means 11 has become the intermediate address of the dual port RAM 2, the reset ends.

[0031]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(a) Description of the first embodiment FIG. 4 is a block diagram showing the first embodiment of the present invention. The data processing device shown in FIG. The circuit 4 includes a circuit 4 and an addition/subtraction control circuit 5.

[0033] Here, the CPU 1 is a dual port RA
This is used to set and reference data for M2.
The data processing circuit 3 periodically stores the dual port RAM 2
The contents of the file are read and updated. Note that the dual port RAM 2 has a port A on the CPU side and a port B on the data processing circuit side, and can be accessed from either port.

The addition/subtraction circuit 4 performs addition/subtraction in order to operate the address of the data processing circuit 3. For this purpose, the addition/subtraction circuit 4 includes an adder 41 and a +1/-1 generation circuit 42. There is. Here, the adder 41 receives the address from the data processing circuit 3 and the +1/-1 generating circuit 42.
The +1/-1 generation circuit 42 generates +1 or -1 in response to a control signal from the addition/subtraction control circuit 5.

The addition/subtraction control circuit 5 is a dual port RA
It monitors the access state of M2 and outputs a control signal for performing address operation to the addition/subtraction circuit 4 so that data processing can be continued even when the CPU 1 is accessing. This addition/subtraction control circuit 5 is
A +1 detection circuit 51 and a -1 detection circuit 52 are provided. Here, the +1 detection circuit 51 is a dual port RAM.
When receiving the busy signal (BUSY) generated when the two ports A and B of the data processing circuit 3 are simultaneously accessed, a +1 flag is set to increment the address of the data processing circuit 3 by 1 (
+1 flag turned ON) This is converted to +1/-1 generation circuit 4.
The -1 detection circuit 52 sets the -1 flag when the +1 flag turns OFF (turns the -1 flag OFF).
(N) and outputs this to the +1/-1 generating circuit 42.

Next, the operation will be explained using FIG. 5. Now, suppose that the CPU access address is address n and the data processing circuit access address becomes address n. Since the dual port RAM 2 outputs a busy signal, the +1 detection circuit 51 of the addition/subtraction control circuit 5 detects the +1 flag. Set it up (turn on the +1 flag) and set this to +1/
-1 generation circuit 42. As a result, 1 is added to the output address of the data processing circuit 3, the access address becomes address n+1, and data processing at address n+1 is performed in the S1 cycle.

Then, in the S2 cycle, the +1 flag turns OFF and the -1 flag turns ON, so the output address of the data processing circuit 3 is subtracted by 1, and the access address becomes n.
In the S2 cycle, data processing at address n is performed.

From the S3 cycle onward, the -1 flag is turned OFF, so data processing at the address output from the data processing circuit 3 is performed.

In this way, in this embodiment, the operation of the data processing circuit 3 is continued by changing the access address from the data processing circuit 3 to another unprocessed address depending on the access state of the dual port RAM 2. Therefore, data processing can be performed periodically without being affected by access by the CPU 1.

In order to deal with the case where the CPU access address and the data processing circuit access address match consecutively, as shown in FIG. /-N
A generating circuit 42' is provided to make the numerical value generated from the +N/-N generating circuit 42' variable in accordance with the count value N of the counter 53. Then, when the continuous coincidence state between the CPU access address and the data processing circuit access address is eliminated, the counter 53 is reset in response to the +1 flag that is turned off.

Therefore, in what is shown in FIG.
While the PU access address and the data processing circuit access address continuously match, the data processing circuit 3
The access address of is n+1, n+2,..., n+N
The data processing for addresses n+1, n+2, . . . , n+N is performed sequentially.

Then, when the continuous coincidence state between the CPU access address and the data processing circuit access address is eliminated, the counter 53 is reset in response to the OFF +1 flag, so that the output address of the data processing circuit 3 becomes N is subtracted, the access address becomes address n,
Data processing at address n is performed.

Thereafter, since the -1 flag is turned off, data processing at the address output from the data processing circuit 3 is performed.

[0044] In this way, the data processing circuit 3 can continue to operate with greater versatility, and thus data processing can be performed periodically without being affected by accesses by the CPU 1. Ru.

(b) Description of Second Embodiment FIG. 7 is a block diagram showing a second embodiment of the present invention. The data processing device shown in FIG. 7 includes a CPU 1, dual port RAM 2, data processing circuit 3, and address Generation circuit 6, reset flag circuit 7, C as a reset operation display circuit
Buffer circuit 8 as a PU separation circuit, buffer circuit 9 as an address inversion circuit, intermediate address detection circuit 1
It is composed of 0.

[0046] Here, CPU1, dual port RAM
2. The data processing circuit 3 is the same as that in the first embodiment described above.

Now, in this FIG. 7, the address generation circuit 6 generates an address from address 0 at the time of reset and supplies it from port B on the data processing circuit side of the dual port RAM 2, and the reset flag circuit 7 generates an address from address 0 at the time of reset. This indicates that a reset operation is in progress upon receiving a signal.

The buffer circuit 8 is a reset flag circuit 7.
This disconnects the dual port RAM 2 from the CPU 1 during the reset operation, and the buffer circuit 9 uses the reset flag circuit 7 to invert the address of the address generation circuit 6 during the reset operation to disconnect the dual port RAM 2 from port A on the CPU side. It is supplied from

The intermediate address detection circuit 10 detects that the address of the address generation circuit 6 has become the intermediate address of the dual port RAM 2.

With the above-described configuration, when a reset signal is input, the CPU 1, data processing circuit 3, address generation circuit 6, and reset flag circuit 7 are initialized. At this time, the output of the reset flag circuit 7 indicates that the reset operation is in progress, and the buffer circuit 8 is turned OFF and the buffer circuit 9 is turned ON.
Make it.

At this time, the address generation circuit 6 sequentially generates addresses starting from address 0 (lowest address), and these addresses are supplied from port B on the data processing circuit side of the dual port RAM 2. At the same time, the buffer circuit 9 inverts the address of the address generation circuit 6, and in other words, addresses that decrease sequentially from the highest address are supplied from port A of the dual port RAM 2 on the CPU side. Further, at this time, the dual port RAM 2 is separated from the CPU 1 by the buffer circuit 8.

Then, in the intermediate address detection circuit 10, the address of the address generation circuit 6 is detected as the address of the dual port RAM 2.
When the intermediate address is detected, the reset flag circuit 7 is reset and the reset is completed. When reset in this manner, the buffer circuit 8 is turned on and the buffer circuit 9 is turned off.

As described above, according to this embodiment, by disconnecting the dual port RAM 2 from the CPU 1 during the reset operation, the dual port RAM 2 is disconnected from the CPU 1 during the reset operation.
PU1 can perform other initialization processing, and can also reset the two ports A and B of dual port RAM 2 from both the highest and lowest addresses at the same time, reducing the reset time. There are also advantages.

(c) Description of Third Embodiment FIG. 8 is a block diagram showing a third embodiment of the present invention. The data processing device shown in FIG. 8 includes a CPU 1, dual port RAM 2, data processing circuit 3, address generation circuit 6',
It is comprised of address generation means 11, a bus control register 12 as a reset operation display circuit, a buffer circuit 13 as a data processing circuit isolation circuit, a buffer circuit 14 as an address inversion circuit, and intermediate address detection means 15.

[0055] Here, CPU1, dual port RAM
2. The data processing circuit 3 is the same as that in the first and second embodiments described above.

Now, in FIG. 7, the address generating means 11 generates an address from address 0 at the time of reset and supplies it from port A on the CPU side of the dual port RAM 2, and the bus control register 12 generates an address from address 0 at the time of reset, and the bus control register 12 generates an address from address 0 at the time of reset. This indicates that the reset operation is in progress.

The buffer circuit 13 has the bus control register 1
2 separates the dual port RAM 2 from the data processing circuit 3 during the reset operation, and the buffer circuit 1
Reference numeral 4 indicates that the bus control register 12 inverts the address of the address generating means 11 during the reset operation and supplies it from port B of the dual port RAM 2 on the data processing circuit side.

The intermediate address detection means 15 detects that the address of the address generation means 11 has become the intermediate address of the dual port RAM 2.

The address generating means 11 and the intermediate address detecting means 15 are provided in the CPU 1.

Note that the address generation circuit 6' generates an address when performing data processing.

With the above-described configuration, when a reset signal is input, the CPU 1, data processing circuit 3, address generation circuit 6', and bus control register 12 are initialized. At this time, the output of the bus control register 12 indicates that the reset operation is in progress, the buffer circuit 13 is turned off, and the buffer circuit 14 is turned off.
Turn on.

At this time, the address generation means 11 of the CPU 1 sequentially generates addresses starting from address 0 (lowest address), and these addresses are supplied from port A of the dual port RAM 2 on the CPU side. At the same time, the buffer circuit 14
In other words, addresses that are sequentially smaller from the highest address are supplied from port B on the data processing circuit side of the dual port RAM 2. Furthermore, at this time, the dual port RAM 2 is separated from the data processing circuit 3 by the buffer circuit 13.

Then, the intermediate address detecting means 15 detects that the address of the address generating means 11 is detected by the dual port RAM.
When the intermediate address of 2 is detected, the bus control register 12 is reset and the reset is completed. When reset in this way, the buffer circuit 13 is turned on.
, and the buffer circuit 14 is turned off.

As described above, according to this embodiment, since the two ports A and B of the dual port RAM 2 can be reset simultaneously from both the highest address and the lowest address, there is an advantage that the reset time can be shortened. .

[0065]

As described in detail above, according to the data processing device of the present invention, data can be processed by changing the access address from the data processing circuit to another unprocessed address depending on the access state of the dual port RAM. Since the processing circuit can continue to operate, there is an advantage that data processing can be performed periodically without being affected by CPU access (Claim 1).

Furthermore, according to the data processing device of the present invention,
By disconnecting the dual-port RAM from the CPU during the reset operation, the CPU can perform other initialization processing during the dual-port RAM reset operation, and also allows two ports of the dual-port RAM to be set to the highest address at the same time. By resetting from both of the lowest addresses, there is an advantage that the reset time can be shortened (claim 2).

Further, according to the data processing device of the present invention, two ports of the dual port RAM can be reset from both the highest address and the lowest address at the same time, so there is an advantage that the reset time can be shortened ( Claim 3
, 4).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the invention according to claim 1.

FIG. 2 is a block diagram of the principle of the invention according to claim 2.

FIG. 3 is a block diagram of the principle of the invention according to claims 3 and 4.

FIG. 4 is a block diagram showing a first embodiment of the present invention.

FIG. 5 is a time chart explaining the first embodiment of the present invention.

FIG. 6 is a block diagram showing a modification of the first embodiment of the present invention.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is a block diagram showing a third embodiment of the present invention.

FIG. 9 is a block diagram showing a conventional example.

FIG. 10 is a time chart illustrating a conventional example.

FIG. 11 is a block diagram showing a conventional example.

[Explanation of symbols]

1 CPU 2 Dual port RAM 3 Data processing circuit 4 Addition/subtraction circuit 5 Addition/subtraction control circuit 6 Address generation circuit 6' Address generation circuit 7 Reset flag circuit (reset operation display circuit) 8
Buffer circuit (CPU isolation circuit) 9 Buffer circuit (address inversion circuit) 10 Intermediate address detection circuit 11 Address generation means 12 Reset flag circuit (bus control register) 13
Buffer circuit (data processing circuit isolation circuit) 14
Buffer circuit (address inversion circuit) 15 Intermediate address detection means 41 Adder 42 +1/-1 generation circuit 42'+N/-N generation circuit 51 +1 detection circuit 52 -1 detection circuit 53 Counter 101 CPU 102 Dual port RAM 103 Data processing Circuit 104 Addition/subtraction control circuit 105 Address generation circuit

Claims (4)

[Claims] 1. A dual port RAM (2), a CPU (1) that sets and references data for the dual port RAM (2), and a
an addition/subtraction circuit (4) comprising a data processing circuit (3) that reads and updates the contents of the AM (2), and that performs addition and subtraction to operate the address of the data processing circuit (3);
Then, the access state of the dual port RAM (2) is monitored, and even if the CPU (1) is accessing the dual port RAM (2),
A data processing device comprising: an addition/subtraction control circuit (5) that outputs a control signal for performing an address operation to the addition/subtraction circuit (4) so that data processing can be continued. 2. A dual port RAM (2), a CPU (1) that sets and references data for the dual port RAM (2), and a CPU (1) that periodically sets and references data for the dual port RAM (2);
It is equipped with a data processing circuit (3) that reads and updates the contents of AM (2), and upon reset, generates an address from address 0 and outputs the address from port (B) on the data processing circuit side of the dual port RAM (2). The address generation circuit (6) that supplies the address, the reset operation display circuit (7) that indicates that the reset operation is in progress, and the reset operation display circuit (7) allow the CPU (1) to output signals from the dual port during the reset operation. CPU isolation circuit (8) that isolates RAM (2)
During the reset operation, the reset operation display circuit (7) inverts the address of the address generation circuit (6) and displays the CPU side port (A) of the dual port RAM (2).
) The addresses of the address inversion circuit (9) and the address generation circuit (6) supplied from the dual port RAM (
2) is further provided with an intermediate address detection circuit (10) for detecting that the intermediate address has been reached;
Data processing equipment. 3. A dual port RAM (2), a CPU (1) that sets and references data for the dual port RAM (2), and a
It is equipped with a data processing circuit (3) that reads and updates the contents of AM (2), and upon reset, generates an address from address 0 and supplies it from the CPU side port (A) of the dual port RAM (2). Address generation means (11)
and a reset operation display circuit (12) that indicates that a reset operation is in progress, and the reset operation display circuit (12) disconnects the dual port RAM (2) from the data processing circuit (3) during the reset operation. Data processing circuit disconnection circuit (13) and reset operation display circuit (12)
During the reset operation, the address generating means (11)
An address inversion circuit (14) inverts the address of and supplies it from the data processing circuit side port (B) of the dual port RAM (2), and an address inversion circuit (14) inverts the address of the dual port RAM (2) and supplies the address of the address generating means (11) ) intermediate address detection means (15) for detecting that the intermediate address has become an intermediate address of
A data processing device characterized by being provided with. 4. The data processing device according to claim 3, wherein the address generating means (11) and the intermediate address detecting means (15) are provided in the CPU (1).