JPH04241449A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve not only the accuracy but also the degree of integration by electrically connecting the lower electrode of the first capacitance element to the upper electrode of the second capacitance element and the upper element of the first capacitance element to the lower electrode of the second capacitance element. CONSTITUTION:Respective capacitance element C1 and C2 are constituted of a lower electrode 7 formed on an element separating insulating film 4 and an upper electrode provided on the lower electrode 9 with an insulating film 9 in between. The lower electrode 7 of the first capacitance element C1 is electrically connected to the upper electrode 10 of the second capacitance element C2 with wiring 15 through a connecting hole 14. Then the upper electrode 10 of the element C1 is electrically connected to the lower electrode 7 of the element C2 with the wiring 15 through the connecting hole 14.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a capacitive element in which an upper electrode is provided on a lower electrode with an insulating film interposed therebetween. It is.

0002

2. Description of the Related Art It is desirable that a capacitive element used for analog processing such as an A/D converter has a small parasitic capacitance. Therefore, the parasitic capacitance is reduced by providing a capacitive element on the element isolation insulating film provided on the main surface of the non-active region of the semiconductor substrate. This capacitive element is constructed by providing an upper electrode on a lower electrode with an insulating film interposed therebetween.

[0003] Each of the upper electrode and lower electrode constituting the capacitive element is made of, for example, a polycrystalline silicon film or an aluminum film.

[0004] If the upper or lower electrode is formed of an aluminum film, it will be melted during heat treatment in a post-process. In other words, there is a problem with heat resistance. In addition, silicon oxide film or silicon nitride film, which is widely used as an insulating film,
Since the adhesion with the aluminum film is poor, there is a problem in that it is difficult to reduce the thickness of the insulating film. If the insulating film cannot be made thinner, the amount of accumulated charge per unit area will decrease. For this reason, the upper or lower electrode is generally made of a polycrystalline silicon film.

On the other hand, when the upper or lower electrode is formed of a polycrystalline silicon film, impurities are implanted through the polycrystalline silicon film to bring the properties of the polycrystalline silicon film closer to those of metal. There is. Regarding this type of technology, see, for example, I.E., Journal of Solid State Circuits, 16, 1981, No.
Pages 08 to 616 (IEEE Journal
Of Solid-State Circuit
s, Vol. 16 (1989) pp. 608-616)
, or I.E.E., Journal of
Solid State Circuits, 24, 1989
, pp. 165-173 (IEEE Jour
nal Of Solid-State Cir
cuits, Vol. 24 (1989) pp. 165-
173).

However, since the amount of impurities that can be introduced or diffused into the polycrystalline silicon film is limited by the solid solubility of the polycrystalline silicon film, its properties as a semiconductor still remain. Therefore, a space charge layer is formed near the interface between the insulating film and the polycrystalline silicon film. When a space charge layer is formed near the interface between the insulating film and the polycrystalline silicon film, the extent of the space charge layer changes depending on the voltage applied to the capacitive element. In other words, since there is a series parasitic resistance, the capacitor exhibits characteristics similar to those of a normal MIS capacitor, and the voltage dependence of the capacitive element remains.

Furthermore, a method has been proposed in which the voltage dependence of a capacitive element is reduced by making the same amount of impurities injected into each of the lower electrode and the upper electrode. but,
Since the upper and lower electrodes are formed in different steps, it is difficult to make them have exactly the same impurity concentration.

[0008] Therefore, the upper and lower electrodes are formed of polycrystalline silicon films, and these capacitive elements are made into a set of two, and a fixed potential is applied to one capacitive element and a fixed potential is applied to the other capacitive element. A method has been proposed in which the fixed potential is set to a fixed potential having the same absolute value and opposite polarity. Regarding this type of technology, see, for example, Symposium on VLSI Circuits, Digest of
Technical Papers, 1989, pp. 57-58 (Symposium OnVLSI
Cirsuits, Digest Of Tech
ical Papers, (1989) pp. 57-
58).

In the semi-solid integrated circuit device described in this document, two reference voltage generating circuits are provided in order to generate the fixed potentials having equal absolute values and opposite polarities. According to this configuration, for example, when the applied voltage increases, the amount of accumulated charge in one capacitive element increases, and the amount of accumulated charge in the other capacitive element also increases. Here, since the charges stored in the pair of capacitive elements have opposite polarities, they cancel each other out as a combined output, and changes in the combined output due to changes in voltage are reduced. Thereby, the precision of the semiconductor integrated circuit device can be improved.

0010

[Problems to be Solved by the Invention] However, as a result of studying the above-mentioned prior art, the present inventor found the following problems.

In the case of the method using the pair of capacitive elements, two reference voltage generation circuits are required, so the degree of integration of the semiconductor integrated circuit device is reduced by an area corresponding to the area required for arranging the reference voltage generation circuits. There is a problem that the amount decreases.

Furthermore, each of the two reference voltage generating circuits has a permissible voltage range. However, if the errors occurring within the allowable voltage ranges of the respective reference voltage generating circuits reinforce each other, the errors become large, resulting in a problem in that the accuracy of the semiconductor integrated circuit device decreases.

An object of the present invention is to provide a technique capable of improving accuracy in a semiconductor integrated circuit device having a capacitive element in which an upper electrode is provided on a lower electrode with an insulating film interposed therebetween.

Another object of the present invention is to improve the accuracy and the degree of integration in a semiconductor integrated circuit device having a capacitive element in which an upper electrode is provided on a lower electrode with an insulating film interposed therebetween. The goal is to provide technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0016]

[Means for solving the problem] (1) A lower electrode composed of a first layer of conductive film, and a second layer of conductive film provided on this lower electrode with an insulating film interposed therebetween. A semiconductor integrated circuit device comprising first and second capacitive elements each comprising an upper electrode, the lower electrode of the first capacitive element and the upper electrode of the second capacitive element being electrically connected. , the upper electrode of the first capacitive element and the lower electrode of the second capacitive element are electrically connected.

(2) The upper electrodes or lower electrodes of the first and second capacitive elements are connected to different predetermined potentials, and the lower electrodes or upper electrodes of the first and second capacitive elements are electrically connected. .

(3) A second conductive layer having a higher impurity concentration than the second conductive type semiconductor region provided on the main surface of the active region of the semiconductor substrate on the main surface of the non-active region of the first conductive type semiconductor substrate. A type semiconductor region is provided, the semiconductor region is connected to a fixed potential, an element isolation insulating film is provided on the semiconductor region, and the capacitive element is provided on the element isolation insulating film.

[0019]

[Operation] According to the above-mentioned means (1) or (2), for example, when the voltage applied to the first and second capacitive elements increases, the insulating film of the first capacitive element Since the spread of the space charge layer near the interface with the electrode becomes larger, the amount of charge accumulated in this first capacitive element increases. on the other hand,
Since a voltage in the opposite direction to that of the first capacitive element is applied to the second capacitive element connected in series or parallel to the first capacitive element, the interface between the insulating film and the electrode of the second capacitive element The spread of the nearby space charge layer becomes smaller, and the amount of accumulated charge decreases. In other words, the amount of change in the amount of accumulated charge in each of the first and second capacitive elements cancels each other out, so even if the voltage applied to the first and second capacitive elements changes, the capacitance as the combined output changes. Fluctuations can be reduced. That is, the voltage dependence of the capacitive element can be reduced. Thereby, the precision of the semiconductor integrated circuit device can be improved.

At the same time, since only two fixed potentials are required, for example, the ground potential of the circuit and a positive or negative reference potential relative to this, there is no need to provide two reference voltage generation circuits, and the reference voltage generation circuit The degree of integration of the semiconductor integrated circuit device can be improved by an area corresponding to the area required to arrange one circuit.

According to the above-mentioned means (3), even if the potential of the semiconductor substrate changes due to the operation of an active element provided in an active region of the semiconductor substrate, the second conductivity type having a high impurity concentration Since the semiconductor region is connected to a fixed potential, potential fluctuations in this semiconductor region are reduced. Therefore, it is possible to reduce the capacitance fluctuation of the parasitic capacitance in which the lower electrode of the first or second capacitive element is the upper electrode, the element isolation insulating film is the dielectric film, and the semiconductor region of the second conductivity type is the lower electrode. I can do it. Thereby, it is possible to reduce the capacitance fluctuation of the parasitic capacitance that affects the voltage dependence of the first and second capacitive elements, which further reduces the voltage dependence of the first and second capacitive elements. be able to. Thereby, the precision of the semiconductor integrated circuit device can be improved.

[0022]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

In all the drawings for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment 1] The configuration of the A/D conversion circuit included in the semiconductor integrated circuit device of Embodiment 2 of the present invention will be explained using FIG. 2 (equivalent circuit diagram).

As shown in FIG. 2, the A/D conversion circuit of the first embodiment has capacitive elements C1 to C at the input section of the amplifier AMP.
n, and the other electrodes of the capacitive elements C1 to Cn are connected to switches S11 and S1 made of MISFETs, etc.
2. Analog input voltage Vin, reference voltage Vref, and ground voltage (GN
D). Further, the output of the amplifier circuit AMP is connected to the input side by a switch Sr made of a MISFET or the like.

Next, the circuit operation of the A/D conversion circuit shown in FIG. 2 and the errors caused by the voltage dependence of the capacitive elements C1 to Cn will be explained.

The reset signal turns on the switch Sr. Further, the switches S13 to Sn3 are all connected, and the analog voltage Vin is applied to all the capacitive elements C1 to Cn. At this time, the input voltage of the amplifier AMP becomes Vr.

Next, switch Sr is turned off to cancel the reset. Then, the switches S11, S12 to Sn1, and Sn2 are controlled to maintain the voltage Vr, and the capacitive elements C1 to Cn are connected to the reference voltage Vref or the circuit ground voltage Vss. Now, for example, y capacitive elements are connected to the reference voltage Vref. Further, for example, x capacitive elements are connected to the ground voltage Vss.

If the first-order voltage term is dominant in the voltage dependence of a capacitive element, then the capacitance C is C=C0(
1+αV)...1.

(1) The charge Q stored at the time of reset is:
Q=(Vin-Vr)(x+y)C0[1+α(V
in-Vr)]...2.

(2) The charge Q accumulated after successive approximation is
Q1=-VrxC0[1-αVr] Q2=(Vref-Vr)yC0[1+α(Vref-
Vr)].

Therefore, the error potential ΔV is:

003
3]

[Math 1]

[0034] Here,

[0035]

[Math 2]

[0036] Therefore, ΔV=Vin(Vin-Vref)α becomes.

Therefore, the smaller the first-order voltage coefficient α, the smaller the error.

FIG. 3 (equivalent circuit diagram) shows a conventional capacitive element C.
s and the capacitive element Cp or Csr of the present invention. In the capacitive element Cs, a lower electrode 7 is provided on an inter-element isolation insulating film provided on the main surface of the non-active region of the semiconductor substrate, and an upper electrode 10 is provided on the lower electrode 7 via an insulating film. It is made up of.

The capacitive element Cp is a parallel capacitor formed by forming a set of two capacitive elements Cs and connecting the lower electrode of one capacitive element and the upper electrode 10 of the other capacitive element, respectively.

The capacitive element Csr is the capacitive element Cs.
This is a series capacitor configured by making a set of two capacitive elements, for example, connecting the upper electrodes 10 of the capacitive elements to different fixed voltages, and electrically connecting the lower electrodes 7 to each other. Alternatively, the lower electrodes 7 of the capacitive elements are connected to different fixed potentials, and the upper electrodes 10 are electrically connected to each other.

Next, the voltage dependence of the capacitive element will be explained using FIG. 4 (a diagram showing the voltage dependence of the capacitive element).

FIG. 4 shows an area of 1 mm2 and an insulating film thickness of 38 nm.
These are the results measured on the sample. Note that the lower electrode is made of a polycrystalline silicon film, and the upper electrode is made of polycide in which a tungsten silicide (WSi) film is formed on the polycrystalline silicon film. Further, the insulating film is made of a silicon oxide film.

The capacitive element Cs1 is a conventional capacitive element Cs in which the lower electrode is connected to the ground voltage Vss. The capacitive element Cs2 has its upper electrode connected to the ground voltage Vss.

[0044] Capacitive element Cp is obtained by connecting capacitive elements Cs in parallel. The capacitive element Csr is obtained by connecting capacitive elements Cs in series.

As shown in FIG. 4, the voltage dependence of the capacitive element Cp or Csr of the first embodiment is small. In other words, when the voltage applied to the capacitive element Cp or Csr increases, for example, the space charge layer near the interface between the insulating film and the electrode of one capacitive element Cs expands, so that this capacitive element The amount of accumulated charge of Cs increases. On the other hand, since a voltage in the opposite direction to that of the capacitive element is applied to the other capacitive element Cs connected in series or parallel with the capacitive element Cs, the interface between the insulating film and the electrode of the other capacitive element Cs The spread of the nearby space charge layer becomes smaller, and the amount of accumulated charge decreases. In other words, each capacitive element Cs
Since the amount of change in the amount of accumulated charge cancels each other out, even if the voltage applied to the capacitive element Cp or Csr connected in parallel or series changes, the fluctuation in the capacitance as the combined output can be reduced. can. That is, the voltage dependence of the capacitive element Cs or Csr can be reduced. Thereby, the precision of the semiconductor integrated circuit device can be improved.

The capacitive elements Cs1, Cs2, Cp, Cs
The respective primary voltage coefficients α of r had the following values.

Cs1: α=-125ppm/VC
s2:α=129ppm/VC
p or Csr: α=2ppm/V As described above, according to the configuration of the first embodiment, the error of the successive approximation type A/D converter can be reduced to 1/10 to 1/50 of the conventional one.

Next, using FIG. 1 (a plan view of the main part) and FIG. 5 (a sectional view of the main part taken along the line A-A in FIG. 1),
A specific configuration of the capacitive element of Example 1 will be described.

Each of the capacitive elements C1 and C2 is composed of a lower electrode 7 formed on the inter-element isolation insulating film 4, and an upper electrode 10 provided on the lower electrode 7 with an insulating film 9 interposed therebetween. has been done. The element isolation insulating film 4 is made of, for example, a silicon oxide film. This inter-element isolation insulating film 4 is provided on the main surface of the n-type well region 2 in the main surface of the non-active region of the p-type semiconductor substrate 1.

The lower electrode 7 is made of, for example, a polycrystalline silicon film. This polycrystalline silicon film is a first layer conductive film. For example, an n-type impurity is implanted into this polycrystalline silicon film.

The upper electrode 10 is composed of a polycrystalline silicon film or a laminated film in which a silicide film or a metal film is laminated on a polycrystalline silicon film. This polycrystalline silicon film or laminated film is a second layer conductive film. For example, an n-type impurity is implanted into this polycrystalline silicon film.

1 and 5 show the case of parallel capacitance. The lower electrode 7 of the first capacitive element C1 and the second capacitive element C2
The upper electrode 10 is electrically connected to the upper electrode 10 by a wiring 15 through a connection hole 14 . Further, the upper electrode 10 of the first capacitive element C1 and the lower electrode 7 of the second capacitive element C2 are connected by a wiring 15 through a connection hole 14. This wiring 15 is made of, for example, an aluminum film. This wiring 15 is provided on the upper layer of the insulating film 13. This insulating film 13 is made of, for example, PSG (Phospho
Silicate Glass) membrane or BPSG
(Boron Phospho Silicate
It is composed of a glass film.

6 (principal part plan view) and FIG. 7 (B- in FIG. 6)
The main part cross-sectional view taken along line B) shows the case of series capacitance. The lower electrode 7 of the first capacitive element C1 and the lower electrode 7 of the second capacitive element C2 are electrically connected by a wiring 15 through the connection hole 14.

8 (principal part plan view) and FIG. 9 (C- in FIG. 8)
The main part sectional view taken along line C) shows the case of another series capacitor. Upper electrode 10 of first capacitive element C1 and second capacitive element C
The upper electrodes 10 of No. 2 are connected by wiring 15 through connection holes 14 .

FIG. 10 (main part plan view) and FIG. 11 (FIG. 10
The main part sectional view taken along the line D-D) shows the case of another series capacitor. By integrally configuring the upper electrodes 10 of the first capacitive element C1 and the second capacitive element C2, the second electrodes 10 are electrically connected.

FIG. 12 (principal part plan view) and FIG. 13 (FIG. 12
The main part sectional view taken along the line E-E) shows the case of another series capacitor. By integrally configuring the lower electrodes 7 of the first capacitive element C1 and the second capacitive element C2, the lower electrodes 7 are electrically connected.

FIG. 14 (cross-sectional view of main parts) is a cross-sectional view of main parts of a semiconductor integrated circuit device equipped with the capacitive element of the first embodiment.

As shown in FIG. 14, this semiconductor integrated circuit device includes a capacitor C, a resistor R, an n-channel MISFET Qn and a p-channel MISFET that constitute a logic circuit.
Qp, a MISFET Qw used when writing information into the memory cell of the EPROM, and a field effect transistor Qe forming the memory cell of the EPROM.

The semiconductor integrated circuit device is composed of a p-type semiconductor substrate 1. This p-type semiconductor substrate 1 is
For example, it is made of single crystal silicon. An n-type well region 2 and a p-type well region 3 are provided on the main surface of the p-type semiconductor substrate 1, respectively. Furthermore, an element isolation insulating film 4 is provided on the main surface of the non-active region of the p-type semiconductor substrate 1. This inter-element isolation insulating film 4 is
For example, it is made of a silicon oxide film. In the region under this inter-element isolation insulating film 4, the p-type well region 3
A p-type channel stopper region 5 is provided on the main surface of the transistor. Each element is insulated and isolated by the element isolation insulating film 4 and channel stopper region 5.

The capacitive element C is provided on the element isolation insulating film 4. This capacitive element C includes a lower electrode 7 provided on the element isolation insulating film 4, and an upper electrode 10 provided on the lower electrode 7 with an insulating film 9 interposed therebetween. The lower electrode 7 is, for example,
It is made of polycrystalline silicon film. For example, an n-type impurity is implanted into this polycrystalline silicon film. This polycrystalline silicon film is a first layer conductive film. The insulating film 9 is
For example, it is made of a silicon oxide film. The upper electrode 1
0 is composed of, for example, a single-layer polycrystalline silicon film, or a laminated film in which a silicide film or a metal film is laminated on a polycrystalline silicon film. For example, an n-type impurity is implanted into the polycrystalline silicon film constituting the upper electrode. This polycrystalline silicon film or laminated film is a second layer conductive film. A wiring 15 is connected to each of the upper electrode 10 and the lower electrode 7 through a connection hole 14 provided in the interlayer insulating film 13.
is connected at one end. The other end of this wiring 15 is connected to an upper electrode (10) or a lower electrode (7) of a capacitive element C that forms a pair with this capacitive element C in a region not shown. The interlayer insulating film 13 is made of, for example, a PSG film or a BPSG film. The wiring 15 is
For example, it is made of an aluminum film.

n of the region where the capacitive element C is provided
− type well region 2 is electrically insulated from n − type well region 2 provided in the active region. Also, this n
− type well region 2 includes n+ type semiconductor region 11 and wiring 1
5 to a fixed voltage. This fixed voltage is either the voltage Vcc, the circuit ground voltage Vss, or the reference voltage Vref. According to this configuration, even if the substrate potential fluctuates due to noise or the like, the potential fluctuation of the n-type well region 2 is reduced, so malfunctions due to fluctuations in the substrate potential can be reduced.

The resistor R is provided on the element isolation insulating film 4. This resistor R is composed of a first layer of conductive film formed in the same process as the lower electrode 7. Further, this resistor R may be formed of a second layer conductive film formed in the same process as the upper electrode 10.

[0063] n-channel type MI constituting the logic circuit
SFETQn and p-channel MISFETQp each constitute an analog circuit or a digital circuit such as an amplifier AMP.

[0064] The n-channel type MISFETQn has p
- a gate insulating film 8 provided on the main surface of the type well region 3;
It consists of a gate electrode 10 provided on this gate insulating film 8, and a pair of n+ type semiconductor regions 11 forming a source region and a drain region, respectively. The gate insulating film 8 is made of, for example, a silicon oxide film. The gate electrode 10 is formed in the same process as the upper electrode 10 of the capacitive element C. In other words, this gate electrode 10 is composed of a second layer conductive film. One end of a wiring 15 is connected to one of the pair of n + -type semiconductor regions 11 through a connection hole 14 provided in an interlayer insulating film 13 .

The p-channel type MISFETQp is n
- a gate insulating film 8 provided on the main surface of the type well region 2;
It is composed of a gate electrode 10 provided on this gate insulating film 8, and a pair of p+ type semiconductor regions 12 forming a source region and a drain region. The gate electrode 1
0 is formed in the same process as the upper electrode 10 of the capacitive element C. In other words, this gate electrode 10 is composed of a second layer conductive film. The pair of p+ type semiconductor regions 1
2 has a connection hole 14 provided in the interlayer insulating film 13.
The other end of the wiring 15 is connected through the wiring 15. That is, one of the p+ type semiconductor regions 12 of this p channel type MISFETQp and the n channel type MISFETQn
is electrically connected to one of the n+ type semiconductor regions 11 via the wiring 15.

MISFETQ used at the time of writing
w is constructed of an n-channel type. This MISFE
The TQw is composed of a gate insulating film 6 provided on the main surface of the p-type well region 3, a gate electrode 7 provided on the gate insulating film 6, and a pair of n+-type semiconductor regions 11, respectively. The gate insulating film 6 is the same as the gate insulating film 8.
It is formed by a different process. Moreover, this gate insulating film 6
The film thickness is configured to be thicker than the film thickness of the gate insulating film 8. This is to drive a high voltage when writing information into the memory cells of the EPROM. The gate electrode 7 is formed in the same process as the lower electrode 7 of the capacitive element C. In other words, this gate electrode 7 is composed of the first layer of conductive film.

The field effect transistor Qe constituting the memory cell of the EPROM includes a gate insulating film 6 provided on the main surface of the p-type well region 3;
It is composed of a charge storage gate electrode 7 provided above, a control gate electrode 10 provided on the charge storage gate electrode 7 with an insulating film 9 interposed therebetween, and a pair of n+ type semiconductor regions 11. . The charge storage gate electrode 7 is
It is formed in the same process as the lower electrode 7 of the capacitive element C. In other words, this charge storage gate electrode 7 is composed of the first layer of conductive film. The insulating film 9 is formed in the same process as the insulating film 9 of the capacitive element C. The control gate electrode 10 is formed in the same process as the upper electrode 10 of the capacitive element C. In other words, this gate electrode 10 is
It is composed of a second layer of conductive film.

Next, the manufacturing method of this semiconductor integrated circuit device will be explained with reference to FIGS. 15 to 18 (cross-sectional views of main parts shown for each manufacturing process).
Explain using.

First, as shown in FIG. 15, an n-type well region 2, a p-type well region 3, an element isolation insulating film 4, a p-type well region 2, a p-type well region 3, an A mold channel stopper region 5 and a gate insulating film 6 are each formed.

Next, as shown in FIG. 16, on the gate insulating film 6, the lower electrode 7 of the capacitor C and the MISFETQ
A first layer of conductive film 7 is formed to constitute each of the gate electrode 7 of the field effect transistor Qe and the gate electrode 7 for charge storage of the field effect transistor Qe. This first layer conductive film 7 is made of, for example, C
It is formed by depositing a polycrystalline silicon film using the VD method. Furthermore, n-type impurities are implanted into this polycrystalline silicon film in order to reduce the resistance value. This n-type impurity implantation may be performed either during or after film deposition. In the case of analog processing, a resistor R with a relatively large resistance value may be required. In this case, after implanting the n-type impurity in the amount necessary to form the resistor R,
Impurities may be selectively implanted at a higher concentration than the above implantation amount into the formation regions of the lower electrode 7 of the capacitive element C, the gate electrode 7 of the MISFET Qw, and the charge storage gate electrode 7 of the field effect transistor Qe. . Thereafter, the gate insulating film 6 is removed using the conductive film 7 as a mask.

Next, an insulating film 9 that constitutes the dielectric film of the capacitive element C and the charge storage insulating film of the field effect transistor Qe is formed. This insulating film 9 is formed by thermally oxidizing a polycrystalline silicon film constituting the conductive film 7. At the same time, a gate insulating film 8 is formed by this thermal oxidation process.

Next, a second layer of conductive film 10 is formed. This second layer conductive film 10 is a single layer film of polycrystalline silicon film,
Alternatively, it is formed by a laminated film in which a silicide film or a metal film is formed on a polycrystalline silicon film. Impurities are implanted into the polycrystalline silicon film constituting the second conductive film 10 in the same manner as the conductive film 7 described above. At this time, by making the amount of impurity implanted into the second conductive film 10 and the amount of impurity implanted into the first conductive film 7 the same or almost the same, the voltage dependence of the capacitive element C can be improved. can be reduced.

Next, as shown in FIG. 17, the memory cell formation region is covered with, for example, a photoresist film, and the conductive film 10 is patterned. Through this process, the upper electrode 10 of the capacitive element, the gate electrode 10 of each of the n-channel type MISFETQn and the p-channel type MISFETQp
form. Note that the control gate electrode 10 of the field effect transistor Qe is defined only in its gate width direction. After that, the photoresist film is removed.

Next, the area other than the memory cell formation area is covered with, for example, a photoresist film, and each of the second layer conductive film, insulating film, and first layer conductive film is patterned, Control gate electrode 1 of field effect transistor Qe
0 and a charge storage gate electrode 7 are formed. During this patterning, the charge storage gate electrode 7
defines the gate length direction. Thereafter, an insulating film 16 is formed by a thermal oxidation method so as to cover each of the first conductive film 7 and the second conductive film 10. This insulating film 16 is thinned when patterning the first conductive film 7 and the second conductive film 10, respectively. The end portion of the conductive film 10 is reinforced, and the leakage of charges accumulated in the charge accumulation gate electrode 7 of the EPROM is reduced. Thereafter, an n+ type semiconductor region 11 and a p+ type semiconductor region 12 are formed.

Next, the insulating film 13 is formed using a BPSG film or a PSG film. After this, the connection hole 1 is formed in this insulating film 13.
form 4.

Next, wiring 15 is formed on the insulating film 13. The wiring 15 is formed by forming an aluminum film and then patterning the aluminum film. By performing up to this step, the above-mentioned figure 1
The semiconductor integrated circuit device of the first embodiment shown in FIG. 4 is completed.

As described above, according to the configuration of the first embodiment, the voltage dependence of the capacitive element C used for analog processing can be reduced, so that high-performance analog processing can be performed.

Furthermore, since the capacitive element C and the field effect transistor Qe constituting the memory cell of the EPROM can be formed in roughly the same manufacturing process,
A semiconductor integrated circuit device having EPROM memory cells and capable of analog processing can be easily manufactured.

Furthermore, since it is equipped with an EPROM memory cell, trimming of the reference voltage, etc. can be easily performed.

[Example 2] The structure and manufacturing method of a semiconductor integrated circuit device according to Example 2 of the present invention are shown in FIGS. 19 and 20 (
This will be explained using a cross-sectional view of a main part showing a part of the manufacturing process of the semiconductor integrated circuit device of Example 2.

As shown in FIG. 20, the capacitance C of the second embodiment
The dielectric films are, from the bottom, silicon oxide film, silicon nitride film,
It is composed of a laminated film in which silicon oxide films are sequentially laminated.

First, the steps up to the step shown in FIG. 15 are performed. Thereafter, a polycrystalline silicon film constituting the lower electrode 7 is deposited, and an insulating film 107 is formed on this polycrystalline silicon film. This insulating film 107 is formed of a silicon nitride film when the dielectric film is composed of a laminated film of a silicon oxide film and a silicon nitride film. In addition, when the dielectric film is composed of a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film, a laminated film in which each of the silicon oxide film and the silicon nitride film is sequentially laminated on a polycrystalline silicon film. Formed by a membrane.

Next, as shown in FIG. 19, the insulating film 1
07 and the unnecessary gate insulating film 6 is removed using the lower electrode 7 as a mask. After this, a new gate insulating film 8 is formed by thermal oxidation. At this time, a silicon oxide film is also formed on the silicon nitride film as the upper layer of the insulating film 107 at the same time. Therefore, by performing this thermal oxidation, the insulating film 17 is formed of a laminated film of a silicon oxide film and a silicon nitride film, or a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. Thereafter, by performing the steps shown in FIGS. 17 and 18, the semiconductor integrated circuit device of the second embodiment is completed.

As explained above, according to the structure and manufacturing method of the semiconductor integrated circuit device of the second embodiment, the dielectric film 9 of capacitance C is made of a silicon nitride film having a higher dielectric constant than a silicon oxide film. By configuring this, the capacity per unit area can be increased. Thereby, the area occupied by the capacitor can be reduced.

[Embodiment 3] The structure of a semiconductor integrated circuit device according to Embodiment 3 of the present invention will be explained using FIG. 21 (equivalent circuit diagram).

As shown in FIG. 21, in the semiconductor integrated circuit device of the third embodiment, a diode D is connected between the capacitors C1 to Cn and the amplifier AMP.

Next, the specific structure of the semiconductor integrated circuit device of Example 3 will be explained with reference to FIG. 22 (cross-sectional view of main parts). Note that FIG. 22 shows a cross section of the n-channel MISFETQn taken along a cutting line in the gate width direction.

As shown in FIG. 22, the diode D is composed of a p- type well region 2 and an n+ type semiconductor region 11, respectively. The junction capacitance of this diode D is configured to be sufficiently smaller than the capacitance of the capacitive element C.

The upper electrode 10 (or lower electrode 7, not shown) of the capacitive element C and the gate electrode 10 of the n-channel MISFET Qn constituting the amplifier AMP are electrically connected by a wiring 15 through the connection hole 14. There is. Further, this wiring 15 is electrically connected to the n+ type semiconductor region 11 forming the diode D through the connection hole 14.

The manufacturing process of a semiconductor integrated circuit device includes various charging processes (for example, an ion implantation process, a photoresist film removal process, a dry etching process, etc.). When the gate electrode 10 of the n-channel MISFET Qn and the upper electrode 10 (or lower electrode 7) of the capacitive element C connected thereto are in a floating state, the upper part of the gate electrode 10 and the capacitive element C is The electrode 10 (or the lower electrode 7) is charged. As a result, the electric field applied to the gate insulating film 8 becomes stronger, and the electrical characteristics of the n-channel MISFET Qn change due to deterioration of the gate insulating film 8, or the gate insulating film 8 is destroyed. According to the configuration of the third embodiment, by providing the diode D, the n-channel MISFET is
Gate electrode 10 of Qn or upper electrode 10 of capacitive element C
(or lower electrode 7) is charged, the charged charge can be released (leaked) to the substrate side via the diode D, so the n-channel MISFETQ
It is possible to prevent variations in electrical characteristics due to charging of the n gate electrode 10 or damage to the gate insulating film 8.

As explained above, according to the configuration of the third embodiment, the electrical characteristics of the n-channel MISFET Qn constituting the input gate of the amplifier AMP deteriorate due to charging during the manufacturing process of the semiconductor integrated circuit device. Since this can be prevented, it is possible to manufacture a semiconductor integrated circuit device having a highly accurate analog circuit.

[Embodiment 4] Next, the configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention will be explained using FIGS. 23 to 25 (cross-sectional views of main parts of the semiconductor integrated circuit device according to Embodiment 4). do.

As shown in FIG. 23, the semiconductor integrated circuit device of the fourth embodiment has an n-type well region 201 having a higher impurity concentration than the n-type well region 2 in the formation region (active region) of the p-channel MISFET Qp. is provided on the main surface of the p-type semiconductor substrate 1 in a region under the inter-element isolation insulating film 4 in the formation region (non-active region) of the capacitive element C, and the n-type well region 201 is connected to a fixed potential. It is something.

The parasitic capacitance in which the lower electrode 7 of the capacitive element C is the upper electrode, the inter-element isolation insulating film 4 is the dielectric film, and the n-type well region 2 is the lower electrode is also an MIS capacitor. On the other hand, the p
The impurity concentration of the n-type well region 2 in the formation region of the channel type MISFET Qp is
Since the impurity concentration is limited to satisfy the electrical characteristics of Qp, it is not possible to make the impurity concentration higher than a predetermined value. Therefore, in the fourth embodiment, the n-type well region 201 is provided in order to reduce the voltage dependence of the capacitive element C due to the parasitic capacitance. Furthermore, a wiring 15 is connected to this n-type well region 201 through a connection hole 14 . This wiring 15 has a fixed voltage, for example, a voltage Vcc, a reference voltage V
ref or the circuit ground voltage Vss. According to this configuration, for example, n channel M
Even if the substrate potential fluctuates during operation of ISFETQn, since the n-type well region 201 is connected to a fixed potential, fluctuations in the potential of the n-type well region 201 are reduced. Therefore, variations in the capacitance of the parasitic capacitance using the n-type well region 201 as the lower electrode are reduced, so that the voltage dependence of the capacitive element C can be further reduced. Thereby, the accuracy of the semiconductor integrated circuit device can be further improved.

The n-type well region 20 shown in FIG.
1 may be formed by independently implanting impurities with different concentrations into the formation regions of the n-type well region 2 and the n-type well region 201, respectively, in the step shown in FIG.

Further, as shown in FIG. 24, in the formation region of the capacitive element C, an n-type well region having a higher impurity concentration than the n-type well region 2 is formed on the main surface of the n-type well region 2. 201 may be provided. This n-type well region 201 is also formed in the step shown in FIG. 15 by selectively implanting impurities with a higher concentration into the formation region of the capacitive element C after forming the n-type well region 2. Just do it.

Further, as shown in FIG. 25, an n-type well region 201 is first formed in the formation region of the n-type well region 2, and then a p-type well region 201 is selectively formed in the formation region of the p-channel type MISFETQp. Injecting impurities to form p-channel MISF
The conductivity type of the main surface portion of the n-type well region 201 in the ETQp formation region may be reversed to form an n-type well region 2 with a low impurity concentration.

The p-type impurity implantation for forming the n-type well region 2 may be performed at the same time as the n-type well region 201 is formed and the p-type well region 3 is formed. According to this step, the step of implanting n-type impurities with high impurity concentration can be omitted. Alternatively, after the step of forming the element isolation insulating film 4, the p-channel type M
A p-type impurity may be selectively implanted into the formation region of ISFETQp.

As explained above, according to the configuration and manufacturing method of the fourth embodiment, by increasing the impurity concentration of the n-type well region 201 constituting the lower electrode of the parasitic capacitance, the voltage dependence of the capacitance C is reduced. Since the capacitance is reduced, a highly accurate capacitor C can be formed.

Furthermore, by changing the impurity concentrations of the n-type well region 2 and the n-type well region 201, a highly accurate capacitive element C can be formed without changing the electrical characteristics of the p-channel MISFET Qp. I can do it.

Furthermore, since the capacitive element C can be formed with high precision, a semiconductor integrated circuit device having a high-performance analog processing function can be manufactured.

[Example 5] Next, the structure of a semiconductor integrated circuit device according to Example 5 of the present invention is shown in FIGS. 26 (a plan view of main parts) and FIG. This will be explained using Figure).

As shown in FIGS. 26 and 27, the semiconductor integrated circuit device of the fifth embodiment has an insulating film 109 made of a silicon nitride film on a lower electrode 7 made of a polycrystalline silicon film.
An upper electrode 1 made of an aluminum film with
5 is provided with a capacitive element C.

[0104] As described above, according to the configuration of the fifth embodiment,
The structure can be the same as that of the capacitive element shown in FIGS. 1 and 5 to 13, and in the examples shown in FIGS. 1 and 5 and FIGS. 8 and 9, the connection between the lower electrode and the upper electrode, Also, the upper electrode and the lower electrode can be easily connected.

Next, a method of manufacturing a semiconductor integrated circuit device according to the fifth embodiment will be explained with reference to FIGS. 28 and 29.

First, the steps up to the steps shown in FIGS. 15 and 16 are performed. After this, an n+ type semiconductor region 11 and a p+ type semiconductor region 12 are formed.

Next, an insulating film 103 is formed by CVD. Thereafter, in the formation region of the capacitive element C, the insulating film 103 above the upper electrode 7 is removed.

Next, a silicon nitride film is formed. Thereafter, this silicon nitride film is patterned into a predetermined shape to form an insulating film 109 as shown in FIG.

Next, an insulating film 113 is formed. After this,
In order to define the substantial area of the capacitance, the insulating film 11
3 is selectively removed to form an opening 104. Further, after this, a laminated film including a silicon oxide film formed on the silicon nitride film may be formed by processing in a thermal oxidizing atmosphere.

Next, the semiconductor integrated circuit device of Example 5 is completed by forming the upper electrode 15 (wiring 15) and a surface protection film (not shown).

As explained above, according to the structure and manufacturing method of the fifth embodiment, the upper electrode 15 of the capacitor C is made of an aluminum film having a lower resistance value than a polycrystalline silicon film, so that the capacitance can be increased. Parasitic resistance of element C can be reduced.

[0112] Although the present invention has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. .

[0113]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

[0114] Accuracy can be improved in a semiconductor integrated circuit device having a capacitive element in which an upper electrode is provided on a lower electrode with an insulating film interposed therebetween.

[0115] Furthermore, in the semiconductor integrated circuit device,
Accuracy can be improved and the degree of integration can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a main part showing a capacitive element of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing the configuration of an A/D conversion circuit of the semiconductor integrated circuit device.

FIG. 3 is an equivalent circuit diagram of the conventional capacitor and the capacitor of the first embodiment.

FIG. 4 is a diagram showing the voltage dependence of the capacitive elements of the conventional and the present Example 1.

FIG. 5 is a sectional view of a main part taken along line A-A in FIG. 1;

FIG. 6 is a plan view of main parts showing another example of the capacitive element of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a main part taken along line BB in FIG. 6;

FIG. 8 is a plan view of main parts showing another example of the capacitive element of the semiconductor integrated circuit device according to the first embodiment of the present invention.

9 is a sectional view of the main part taken along line CC in FIG. 8; FIG.

FIG. 10 is a plan view of a main part showing another example of the capacitive element of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 11 is a sectional view of a main part taken along line DD in FIG. 10;

FIG. 12 is a plan view of main parts showing another example of the capacitive element of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 13 is a sectional view of a main part taken along line E-E in FIG. 12;

FIG. 14 is a plan view of a main part of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 15 is a plan view of essential parts showing a first manufacturing process of the semiconductor integrated circuit device.

FIG. 16 is a plan view of a main part showing a second manufacturing process of the semiconductor integrated circuit device.

FIG. 17 is a plan view of main parts showing a third manufacturing process of the semiconductor integrated circuit device.

FIG. 18 is a plan view of essential parts showing a fourth manufacturing process of the semiconductor integrated circuit device.

FIG. 19 is a plan view of a main part showing a first manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 20 is a plan view of essential parts showing a second manufacturing process of the semiconductor integrated circuit device.

FIG. 21 A of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram showing the configuration of a /D conversion circuit.

FIG. 22 is a sectional view of essential parts of the semiconductor integrated circuit device.

FIG. 23 is a plan view of a main part of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 24 is a sectional view of a main part showing another example of the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 25 is a cross-sectional view of main parts showing another example of the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 26 is a plan view of a main part showing a capacitive element of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

27 is a cross-sectional view of the main part taken along line FF in FIG. 26. FIG.

FIG. 28 is a sectional view of a main part showing a first manufacturing process of the semiconductor integrated circuit device.

FIG. 29 is a sectional view of a main part showing a second manufacturing process of the semiconductor integrated circuit device.

[Explanation of symbols]

7 Lower electrode 10 Upper electrode 14 Connection hole 15 Wiring

Claims (3)

[Claims] 1. A lower electrode comprising a first layer of conductive film, and an upper electrode comprising a second layer of conductive film provided on the lower electrode with an insulating film interposed therebetween. a semiconductor integrated circuit device comprising first and second capacitive elements, the lower electrode of the first capacitive element and the upper electrode of the second capacitive element being electrically connected; A semiconductor integrated circuit device characterized in that an upper electrode and a lower electrode of a second capacitive element are electrically connected. 2. Upper electrodes or lower electrodes of the first and second capacitive elements are connected to different predetermined potentials, and the lower electrodes or upper electrodes of the first and second capacitive elements are electrically connected. The semiconductor integrated circuit device according to claim 1, characterized in that: 3. A second conductivity type semiconductor region having a higher impurity concentration in a main surface portion of an inactive region of a first conductivity type semiconductor substrate than a second conductivity type semiconductor region provided in a main surface portion of an active region of the semiconductor substrate. The semiconductor device according to claim 1, further comprising a semiconductor region, the semiconductor region is connected to a fixed potential, an element isolation insulating film is provided on the semiconductor region, and the capacitive element is provided on the element isolation insulating film. 3. A semiconductor integrated circuit device according to claim 1 or claim 2.