JPH0423980B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an alarm capture circuit that captures a fault occurring or detected within a device of a digital transmission communication system.

[Conventional technology]

Traditionally, this type of alarm capture circuit has been configured to
Fault information from each alarm unit making up the device was collected using a gate signal from a microprocessor and a gate circuit.

FIG. 2 is a block diagram of a conventional example of such an alarm capture circuit.

Alarm units 101, 102,..., 10
8,201,202,...,208,...,801,
802, ..., 808 are three-state buffers 1401, 1402, ..., 1408, 15, respectively.
01,1502,...,1508,...,2101,
2102,..., 2108, and the microprocessor 1001 is connected to the gate signal line 110.
1, 1102, ..., 1108 for three-state buffers 1401-1408, 1501-1
By determining the states of the signal lines 508, . . . , 2101 to 2108, the signal lines 1301, 1302, .
308 to each alarm unit 101 to 108,
Fault information from 201-208, . . . , 801-808 is taken in.

In this circuit, 8 pieces of fault information are required to control 64 pieces of fault information.
Main control signal lines (gate signal lines 1101, 110
2,...,1108) are required.

[Problem that the invention seeks to solve]

In the conventional alarm acquisition circuit described above, when controlling failure information from each alarm unit that makes up the device, one gate circuit corresponds to one failure information, so the number of failure information increases. However, if one bus line is considered, the number of gate signal lines increases proportionally.

[Means for solving problems]

The present invention provides a selection circuit for each alarm unit group, selects one predetermined alarm unit from each selection circuit in response to a selection signal from the microprocessor, and sends fault information to the microprocessor via a three-state buffer. It was designed to be incorporated.

That is, the alarm capture circuit of the present invention
A maximum of m alarm units are connected to the input side, one or more selection circuits are provided for selecting one of these alarm units, and each selection circuit is provided correspondingly, and the input is connected to the output of the selection circuit. Select a predetermined one of the three-state buffers and alarm units connected to each selection circuit by n (however, ^2n-1 <m≦ ²ⁿ ) selection signal lines, and It has a microprocessor that controls the states of all three-state buffers through gate signal lines and inputs the outputs of all three-state buffers.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the alarm capture circuit of the present invention.

Both have 8 alarm units 101 and 10
2,...,108, alarm unit 201, 20
2,...,208,..., alarm unit 801,
802,...,808 are selection circuits 901,
902,...,908, and three selection signal lines 120 from the microprocessor 1001.
One predetermined alarm unit is selected from each selection circuit ⁹⁰¹ , 902, .
A signal line 130 between the outputs of the selection circuits 901, 902, . . . , 908 and the microprocessor 1001
Three-state buffers 2201, 2202, ..., 2208 are provided on the circuits 1, 1302, . , each selection circuit 9
The fault information of the alarm unit selected at 01, 902, ..., 908 is sent to the microprocessor 100.
1.

In order to control 64 pieces of fault information, the conventional circuit (Fig. 2) requires eight control lines (signal lines 1101,
1102,..., 1108), but in this embodiment, 3+1=4 (selection signal lines 1201,
1202, 1203 and the gate signal line 1204). The difference becomes larger as the amount of fault information to be controlled increases.

〔Effect of the invention〕

As explained above, the present invention provides a selection circuit for each alarm unit group, selects a predetermined alarm unit from each selection circuit in response to a selection signal from a microprocessor, and then selects a predetermined alarm unit from each selection circuit via a three-state buffer. By taking in failure information into the setter, there is an effect that failure information can be taken in efficiently with fewer control lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the alarm capture circuit of the present invention, and FIG. 2 is a block diagram of a conventional example. 101-108, 201-208,..., 801
~808: Alarm unit, 2201, 220
2,...,2208: Three-state buffer, 1
301-1308: Signal line, 1201, 120
2, 1203: selection signal line, 1204: gate signal line, 901 to 908: selection circuit, 1001: microprocessor.

Claims (1)

[Claims] 1. A maximum of m alarm units are connected to the input side, one or more selection circuits are provided for selecting any one of these alarm units, and each selection circuit is provided correspondingly, and the input is connected to the corresponding one. Connected to each selection circuit by a three-state buffer connected to the output of the selection circuit, and n selection signal lines (2n ^-1 <m≦ ²ⁿ ) commonly connected to the selection circuit. It has a microprocessor that selects a predetermined one of the alarm units that have been detected, controls the states of all three-state buffers by one gate signal line, and inputs the outputs of all three-state buffers. Alarm acquisition circuit.