JPS6121613A - Signal delay unit - Google Patents

Abstract

PURPOSE:To obtain a unit with simple constitution and complete compatibility by providing a conversion table to obtain control data of a multiplexer outputting selectively an output of plural series connection delay elements from required delay information. CONSTITUTION:In inputting pieces of information A, B...Z (e.g., a delay amount) informing the location of a signal delay unit 2 to an address terminal 17 of a ROM15, the ROM uses the conversion table 15 to output data of a corresponding delay to a control line 8. Thus, some of corresponding taps 6a-6f are selected by the multiplexer 7. Further, as a delay circuit 4, a memory circuit can be used in place of delay units 5 and the multiplexer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal delay unit used as a variable delay line for digital signals in digital video innovators and the like.

The configuration of the conventional example and its problems Figure 1 shows the digital video signal path P1 of a video switcher, etc.
- Signal delay unit inserted between input terminals 1a to 1m and output terminals 3a to 3m in the middle of Rn) 2 a
2 m, and the amount of delay is required to correspond to various values depending on the state of the equipment connected to the video signal paths P1 to Rn or to the video signal paths P and -Rn. FIG. 2 shows a more specific configuration example of the individual signal delay units 2a to 2m, where 1 is an input terminal, 3 is an output terminal,
4 is a delay circuit, 6 is a delay element such as a register, 6a to 6f
is a tap, 7 is a multiplexer, 8 is a multiplexer 7
9 is an individual multiplexer, 9a is a control terminal of the individual multiplexer 9, 10 is a switching circuit, 11 is a controller, and 12 is a dip switch.

With the configuration shown in Figure 2 above, the digital signal from input terminal 1 is
It is input to one end of the series-connected delay element 5, taken out from intermediate taps 6a to 6f, and changes the delay amount (x, x+J, . . . ) at the take-out position. At this time, one of the taps 6a to 6f is selected according to the data value applied to the control line 8, and the required delay amount is applied and outputted from the output terminal 3.

The data input to the control input line 8 is the data input to the dip switch 1.
The output of the switching circuit 1o is obtained by the combination of the two, and is obtained by operating one of the individual multiplexers 9 under the control of the controller 11. Now, as a concrete numerical example,
If the variation range of the delay amount is from ○ to 1,000CT based on the clock time (CT)', the control line 8 requires 10 bits, and therefore the number of dip switches 12 for one switching circuit is If we assume that 10 types of DIP switches are required and that 30 types of delay are required considering state changes and equipment versatility (compatibility), a total of 30 DIP switches will be required.
The disadvantage is that the number of units is 0, the configuration becomes complicated, the unit becomes large, and the cost increases.

Another method, as shown in FIG. 3, is to select and output data suitable for the conditions required of the unit 2 by using a table 14 in the computer 13 that gives the amount of delay for the digital data given to the control line 8. There is a way. However, this method has the disadvantage that a table must be prepared for each combination of the conditions, which increases the program capacity and makes it difficult to use.

OBJECTS OF THE INVENTION The present invention is intended to eliminate the problems of the above-mentioned conventional example, and aims to provide a simple structure and complete compatibility between units.

Structure of the Invention In order to achieve the above object, the present invention provides a signal delay unit (signal delay unit) equipped with a conversion table for obtaining control data for a multiplexer for selectively outputting the outputs of a plurality of series-connected delay elements from required delay information. k configuration.

Description of examples An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, 1 is an input terminal, 2 is a signal delay unit, 3 is an output terminal, 8 is a control line, 16 is a read only memory (ROM), 16 is a conversion table node, and 17 is an address terminal of the ROM 15. The same reference numerals as in FIG. 2 represent the same names.

With the above configuration, information A, B, which informs the address terminal 17 of the ROM 16 of the position of the signal delay unit 2.
- If Z (for example, delay amount) is input, the ROM 14 transfers the corresponding delay amount data to the control line 8 using the conversion table 15.
Output to. Therefore, multiplexer 7 selects some of the corresponding taps 6a-6f. That is, according to the above configuration, the dip switch 12 in the conventional example
Since the number of components that increase rapidly as the number of states increases can be largely omitted, the circuit configuration can be simplified.

Note that as the delay circuit 4, a memory circuit may be used instead of the delay element 5 and the multiplexer 7. Even though the input to the address terminal 14 may be done manually, the positioning of the delay signal may be input from other circuit parts such as the CPU from which information can be obtained.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention includes required delay information and a conversion table between control data and a multiplexer that determines the amount of delay in accordance with the delay information. This has the advantage that a large number of previously required dip inches can be omitted, and the overall configuration is simplified.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing how to use a signal delay unit, FIG. 2 is a block diagram showing the configuration of a conventional signal delay unit, FIG. 3 is an explanatory diagram of another conventional method of obtaining signal delay, and FIG. The figure is a block diagram showing the configuration of a signal delay unit according to an embodiment of the present invention. 6... Delay element, 7... Multiplexer, 14... ROM, 15... Conversion table,
16. Old address terminal. Name of agent: Patent attorney Toshio Nakao (1 person)
1 Figure 2

Claims (1)

[Claims] a plurality of delay elements connected in series; a multiplexer to which the output of each of the delay elements is input; and a multiplexer for selecting and outputting a delay amount of the delay element according to control data from a control line; and a delay element of the delay element. A signal delay unit comprising a conversion table between quantity information and control data of the multiplexer.