JP3453840B2 - Parallel reading M-sequence code generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M-sequence code generation circuit which has a plurality of DFFs, selects a pattern length, and reads out in parallel for multiplexing. FIG. 5 shows a configuration of an M-sequence code generating circuit according to the prior art. 5A to 3P are D-type flip-flops (hereinafter, referred to as DFF) for parallel reading, and 9 is an exclusive OR (hereinafter, referred to as EOR) gate. FIG. 5 shows an example of a circuit for reading out 16 M-sequence codes of pattern length (2 ⁷ -1) in parallel. The output 4P of the DFF 3P is input to the D terminal of the DFF 3O, and similarly connected in series up to the DFF 3A. As described above, the DFFs 3A to 3P constitute a shift register, and the outputs 4K and 4J are input to the exclusive OR gate 9, and are fed back to the input of the DFF 3P. Also, D
The clock input terminal 6 is connected to the clock terminals of the FFs 3A to 3P.
And a clock signal is supplied in parallel, and outputs 4A to 4P are output in parallel from the Q terminal of each DFF. [0004] Numbering is performed in order from the DFF 3A. When the output of the j-th DFF at a certain time t is Q _j (t) and the clock cycle is T, the time t +
The output Q _j (t + T) of the j-th DFF at T is Q ₁ (t + T) =
Q ₂ (t), Q ₂ (t + T) = Q ₃ (t),..., Q ₁₅ (t + T) = Q
There is a relationship like ₁₆ (t). The above is derived from the configuration of the shift register. Further, since the signal is fed back to the DFF 3P, it can be written as Q ₁₆ (t + T) = Q ₁₀ (t) + Q ₁₁ (t). Here, “+” indicates an exclusive OR. These connections can generally be represented by a matrix, and are as follows: Q _j (t + T) = Σ _i K _ji · Q _i (t) (1) Here, “Σ _i ” is an exclusive OR instead of a normal sum. [0005] Here, K is 16 × representing the connection of the feedback circuit.
This is a 16-square matrix, and equation (1) is represented as shown in FIG. Here, in order to make the output read in parallel from the 16 DFFs into parallel data for 16 multiplexing, the output of the DFF is output again as Q ′ _j (t) and is output in 16 data skips as in the following equation. There is a need. Q ′ _j (t + T) = Q _j (t + 16T) Here, when expanded by equation (1), Q ′ _j (t + T) = Σ _{i Kji} · Q _i (t + 15T) = Σ _i (K ¹⁶ ) _ji · Q _i (t) = Σ _i (K ¹⁶ ) _ji · Q ′ _i (t) (2) Next, FIG. 7 shows a configuration diagram of an M-sequence code generation circuit represented by Equation 2. FIG. 7 shows the pattern length (2 ^X -1)
Is an example of a circuit in which the index X of X can be selected to be X = 7 or X = 15. In FIG. 7, 1 is a 16-multiplexing feedback circuit when X = 15, 3A to 3P are DFFs, and 4A to 4P are D
The output of the FF, 6 is a clock input, and 10 is a feedback circuit for 16 multiplexing when X = 7. In FIG. 7, when the clock 6 is input, the DFFs 3A to 3P output 4A to 4P in parallel. The output terminals of the DFFs 4A to 4P are connected to interlocking switches 5A to 5P for selecting feedback circuits, respectively, and output the outputs of the DFFs to the inputs 7A to 7P of the feedback circuit 10.
Or input to the inputs 8A to 8P of the feedback circuit 1. Outputs 4A-4P are interlock switches 5A-5
After passing through the multiplexing feedback circuit 1 or the multiplexing feedback circuit 10 selected by P, the output terminals 15A to 15P output DFFs 3A to
The signal is fed back to the D terminal of 3P, and outputs the M-sequence code of the output terminal of the multiplexing feedback circuit 1 at the next clock. From equation (2), the connection matrix K ¹⁶ of the multiplexing feedback circuit 1 when X = 15 in FIG. 7 is as shown in FIG. The connection matrix K ¹⁶ means that when the component (K ¹⁶ ) _ji is 1, the output of the i-th DFF is fed back to the input of the j-th DFF. Further, when 1 to become component to the j row of the matrix K ¹⁶ there are a plurality, it is necessary to EOR gates of input. Next, FIG. 8 shows an example of the configuration of the multiplexing feedback circuit 1 when X = 15 in FIG. 13A to 13 in FIG.
P is an EOR gate whose output is 15A-15
P. The outputs 15A to 15P of the EOR gate are fed back to the inputs of the DFFs 3A to 3P in this order. According to the connection matrix in FIG. 9, the outputs of the DFFs 3A to 3P are (8B, 8C), (8C, 8D),
(8D, 8E) (8B, 8C, 8P), (8B,
8D). Next, the connection matrix K ¹⁶ of the multiplexing feedback circuit 10 when X = 7 in FIG. 7 is as shown in FIG. Next, FIG. 10 shows a circuit example of the multiplexing feedback circuit 10 when X = 7 in FIG. 11A-11P is EO
R-gates whose outputs are 15A-15P. The outputs 15A to 15P of the EOR gate are DF in this order.
The signals are fed back to the inputs of F3A to 3P. According to the connection matrix of FIG. 11, the outputs of the DFFs 3A to 3P are (7J, 7K), (7K, 7L), (7L,
7M) (7K, 7L, 7M, 7N). In a conventional circuit configuration in which M-sequence codes are read in parallel from N DFFs at a certain multiplicity N, the connection matrix of the N-multiplexing feedback circuit is expressed by the following equation (2). As shown, the result is obtained by raising the original connection matrix K to the Nth power. For this reason, the number of matrix components that become 1 increases. In a configuration in which the pattern length (2 ^x -1) of the generated M-sequence code can be selected, this problem becomes more remarkable when the difference between the multiplicity N and the index X is large. As a result, a large number of EOR gates with a plurality of inputs are required, and there is a problem that the delay time is increased and the operation speed is reduced. The present invention divides the feedback circuit multiplicity N to independent m _X number of feedback circuit multiplicity (N / m _X), to simplify the components of the connection matrix, reduce the number of inputs EOR, the total number of gates To provide a parallel readout M-sequence code generation circuit for shortening the delay time. In order to achieve this object, the present invention provides a plurality of multiplexing feedback circuits for selecting an index X and setting different pattern lengths (2 ^X -1). And an interlocking switch for selecting the plurality of multiplexing feedback circuits, and a parallel readout M-sequence code generation circuit that performs parallel readout from N DFFs at a multiplicity N.
m _X) - maximum value of the positive integer exponent X> 0 is satisfied m _X
, And the multiplexing feedback circuit having the pattern length (2 ^X -1) with the multiplicity N is divided into m _X feedback circuits having the same multiplicity (N / m _X ) and replaced. The multiplicity N is given, and the pattern length (2 ^X −
The parallel readout M configured to select the index X of 1)
In sequence code generation circuit, (multiplicity N / _{m X)} - the exponent X>
0 and a positive integer which holds determining the maximum of the m _X. Then, an N-multiplexing feedback circuit configured for each index X of the pattern length (2 ^X −1) is newly added to the multiplicity (N / m _X ).
To independent m _X number of the feedback circuit. Set the initial value into N DFF, enter the same clock by switching the m _X-number of the feedback circuit to obtain the parallel readout M-sequence code for N multiple. Next, parallel reading can be performed from 16 DFFs for 16 multiplexing, and the pattern length (2 ^X -1) is determined by X =
FIG. 1 shows an M-sequence code generation circuit according to the present invention, which can be selected to be 7 or X = 15. 1 is a feedback circuit for 16 multiplexing for X = 15, 2A and 2B are feedback circuits for 8 independent multiplexing for X = 7, and 3A to 3P are DFs for parallel reading.
F, 4A-4P are the outputs of DFFs 3A-3P, 5A-5P
Is an interlocking switch for selecting a feedback circuit, 6 is a clock input,
7A to 7P are inputs to the multiplexing feedback circuits 2A and 2B, and 8A to 7P.
8P is an input of the multiplexing feedback circuit 1. When the index X of the pattern length (2 ^X -1) is 15, the multiplicity N / m _X -the index X> 0 holds.
_{X is, (16 / m X) -15} > 0 than m _X = 1, and the
The multiplexing feedback circuit 1 is not divided, the circuit is the same as in FIG. 8, and the outputs of the DFFs 3A to 3P are connected to the inputs 8A to 8P of the multiplexing feedback circuit 1, respectively. [0018] When the exponent X = 7 pattern length (2 ^X -1), (multiplicity N / m _X) - the exponent X> 0 holds m _{X
Is, (16 / m X) -7} > 0 than m _X = 2, and the 1
As shown in the figure, a feedback circuit for 16 multiplexing for X = 7 has a multiplicity of 8
Multiplexing feedback circuits 2A and 2B. In FIG. 1, the output of the DFF 3A is connected to the multiplexing feedback circuit 2B, and the output of the DFF 3B is connected to the multiplexing feedback circuit 2B.
The outputs of the DFFs 3A to 3P are alternately connected to the inputs 7A to 7P of the multiplexing feedback circuits 2A and 2B. When the clock 6 is input, the DFFs 3A-
3P outputs outputs 4A to 4P in parallel,
The signals are fed back to the DFFs 3A to 3P through the multiplexing feedback circuit 1 or the multiplexing feedback circuits 2A and 2B selected by A to 5P, and output in parallel with the next clock. In FIG. 1, the decomposed new connection matrix is shown in FIG.
It becomes as shown in. Next, FIG. 2 shows a circuit example of the feedback circuits 2A and 2B in FIG. In FIG. 2, 14A to 14P are EOR gates, and their outputs are 12A to 12P. E
The outputs 12A to 12P of the OR gate are DFF3A in this order.
It is fed back to the input of ~ 3P. According to the connection matrix of FIG.
The outputs of the DFFs 3A to 3P are (7
C, 7E), (7E, 7G), (7G, 7I) ...
(7C, 7G) and (7D, 7F), (7F, 7H), (7H, 7J)...
-Some are connected to (7D, 7H). The former corresponds to the feedback circuit 2B, and the latter corresponds to the feedback circuit 2A. Next, the state of the outputs 4A to 4P of the DFF when X = 7 in FIG. 1 is shown in FIG. 4 is a clock input, 4A to 4P are DFF outputs, 12A, 12C,...
12M · 120 is a feedback signal from the feedback circuit 2B;
.., 12N and 12P are feedback signals from the feedback circuit 2A, and are input to the DFFs 3A to 3P, respectively. The output of the DFF changes at the rise of the clock,
It is held until the next clock input. If the connection matrix is K, the multiplicity is N, and the M-sequence code is D (0), D (1), D (2), D (3),... _i (K ^N ) _ji · D (Y × i) = D (Y × j + Y × N) (4) When the data is taken out in 16 steps with the multiplicity N being 8, Y = 2, so that Σ _i (K ⁸ ) _ji · D (2 × i) = D (2 × j + 16). It can be seen that the even and odd terms of the code are separated. If D (0), D (2), D (4)) are given as initial values, D (16), D (18), D (20) 〜 will be
FF3A, 3C,..., 3M, 3O. On the other hand, if D (1), D (3), D (5) ~ are given as initial values, D (17), D (19), D (21) ~ will be 3B / 3D ...・
Input to 3N / 3P. Therefore, the output 4A ~ of the DFF
4P includes M-sequence codes D (0), D (1), D (2), D (3), D (4),
D (5) and D (6) are obtained. In FIG. 11, in the connection matrix of the 16-multiplexing feedback circuit 10 when the pattern length is (2 ⁷ -1), the feedback circuit has two 4-input EOR gates, three 3-input EOR gates, It can be seen that 11 2-input EOR gates are required. If these are all constituted by two-input EOR gates, 23 EOR gates are required. On the other hand, as shown in the connection matrix of FIG. 3, when this is decomposed into two independent feedback circuits 2A and 2B with a multiplicity of 8, one 3-input EOR gate and 7 2-input EOR gates are formed. Thus, two feedback circuits are prepared. These are all 2 inputs E
In the case of an OR gate, 18 EOR gates are sufficient. According to the present invention, in a parallel readout M-sequence code generation circuit having a multiplicity of N and a pattern length of (2 ^X -1), the multiplexing feedback circuit is provided with a multiplicity of N / m _X ) / Exponential X> 0, it is possible to simplify the components of the connection matrix by dividing the matrix by m _X. Therefore, the maximum number of inputs of the EOR gates of the feedback circuit and the required total number of gates can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an M-sequence code generation circuit according to the present invention. FIG. 2 is an explanatory diagram of a feedback circuit 2 of FIG. FIG. 3 is a connection matrix of the feedback circuit 2; FIG. 4 is a time chart of FIG. 1; FIG. 5 is a configuration diagram of a conventional M-sequence code generation circuit. FIG. 6 is a connection matrix of the feedback circuit of FIG. 5; FIG. 7 is a configuration diagram of a conventional M-sequence code generation circuit. FIG. 8 is an explanatory diagram of the feedback circuit 1 of FIG. 1; FIG. 9 is a connection matrix of the feedback circuit 1; FIG. 10 is an explanatory diagram of the feedback circuit 10 of FIG. 7; FIG. 11 is a connection matrix of the feedback circuit 10; [Description of Signs] 1 16 multiplexing feedback circuits 2A and 2B 8 multiplexing feedback circuits 3A to 3P DFFs 4A to 4P DFF outputs 5A to 5P Interlock switch 6 Clock input 10 16 multiplexing feedback circuit

Claims (1)

(57) Claims 1. An index X is selected, and a plurality of multiplexing feedback circuits for setting different pattern lengths (2 ^X -1) and the plurality of multiplexing feedback circuits are selected. A read-out M-sequence code generation circuit that includes an interlocking switch that performs parallel reading from N DFFs with a multiplicity of N, wherein the maximum value of a positive integer satisfying (multiplicity N / m _X ) -exponent X> 0 m _X is obtained, and the multiplexing feedback circuit having a pattern length (2 ^X −1) with a multiplicity N is divided and replaced by m _X feedback circuits having the same multiplicity (N / m _X ). Parallel reading M
Series generation circuit.