JPH04229485A - Vram, memory device and display system - Google Patents

Abstract

PURPOSE: To provide a simple and efficient means capable of avoiding a midline reload by completely and efficiently utilizing serial access memory(SAM) parts. CONSTITUTION: This device is composed of VRAMs to be composed of at least one RAM consisting of plural first memory cells mutually connected so as to form plural rows and plural columns, SAM parts consisting of plural second memory cells and data transferring means between the RAM parts and the SAM parts. Selection parts consisting of different two rows are simultaneously transferred to SAM parts via addressable transfer gates under the control of an address control logic.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device capable of high-speed serial data transfer to a peripheral device such as a raster display device.

0002

[Prior Art] Video random access memory (
VRAM) is memory typically used in video display devices in computer systems. VRAM is essentially a traditional dynamic random access
This is a memory (DRAM) with a second port added through which data is serially accessed. VRAM consists of a random access memory (RAM) section, a serial access memory (SAM) section, and a transfer gate that controls data transfer between the RAM and the SAM. A SAM array typically has a memory capacity of one row of a RAM array. All rows of memory data are transferred between RAM and SAM in a single data transfer access. RAM port and S
The AM ports operate asynchronously and independently except when transferring data between RAM and SAM.

[0003] The independent and asynchronous operation of the two ports is such that the RAM port updates the contents of the display memory.
It is also used in applications in video display of computer systems where serial ports are used to provide data that is displayed rasterly on the screen. The RAM port operates at the frequency of the computer system and the SAM port operates at the frequency dictated by the raster display requirements. The SAM array normally has a capacity for one row of display data, and is continuously reloaded with new rows of display data within a display frame time. Generally, each new row display data is obtained from the row one index higher than the previous row. Reloading new row display data from the RAM array to the SAM array is performed in the RAM port data transfer cycle. RAM array and SA
The data transfer cycle between M-arrays is the only interruption to the RAM port's normal RAM access cycle. This transfer cycle is classified into two types. The first is data transfer when the SAM port is inactive, no data is being transferred to the raster display, and the serial clock is also stopped. This typically involves reloading the SAM during the blanking period of the display frame. The second is when the SAM port is active and data is transferred to the raster display. In this case the serial clock is being generated and the RAM port data transfer cycles require precise synchronization with the serial clock to maintain continuous data requests from the SAM port to the raster display. This second state is often referred to as "real-time data transfer" or "midline reload."

Control and timing of such midline reloads is a major issue in the design of display memory subsystems. Midline reload is R
Because it is a critically time-controlled real-time access that requires synchronization between the AM and SAM ports,
This wastes RAM port bandwidth, a critical component of many display memory subsystems. Furthermore, real-time access with such critical time control potentially requires complex and high speed circuitry for synchronization and control. Therefore, designers have traditionally avoided midline reloads and avoided critical timing controls or the complex circuitry associated therewith. Conventional methods for avoiding midline reloads have a number of limitations on how the contents of display memory are mapped onto the display screen. These constraints are shown below. (1) Fixing the start address for display data on the first horizontal scanning line of the display frame. (2) Generate the start address of each subsequent horizontal scanning line by incrementing the fixed address. (3) The horizontal scanning line length that requires the capacity for display data is
Do not exceed the capacity of the VRAM SAM array in the display memory subsystem. Traditionally, all these constraints needed to be satisfied to avoid midline reloads. It should be noted that these limitations do not apply to general purpose graphics adapters or display memory subsystems.

Second generation VRAMs have advanced to the ability to transfer half a row of random access memory to half a SAM. Meanwhile, the other half of the SAM is scanned out to the display device. This means of avoiding real-time data transfer is used in 1 megabit multiport DRAMs and is generally described in U.S. Pat. No. 4,825,411.
No. 4,855,959. These so-called “split registers”
In VRAM, the SAM array is separated into two, each handled independently by a method called "split register data transfer" in which one SAM is active while the other is loaded. Typically, the output status pins are scanned out while the SAM
It is configured to show.

While split-register VRAM somewhat alleviates midline reloads, it does not fully and efficiently utilize SAM array capacity and potentially doubles data transfer accesses.

[0007]

SUMMARY OF THE INVENTION The present invention fully and efficiently utilizes SAM and, under certain circumstances,
The purpose is to provide a simple and efficient means by which "midline reloads" can be avoided.

[0008] Also, if system constraints prevent the avoidance of a total "midline reload", or if for any reason it is advantageous to use a "midline reload", real-time performance may be eliminated. However, it is a second object of the present invention to eliminate such critical timing. By eliminating the need for real-time VRAM data transfers, the present invention eliminates the need for the potentially complex and high speed circuitry required to synchronize and control such data transfers, and also eliminates the need for the potentially complex and high speed circuitry required to synchronize and control such data transfers.
It also eliminates the potential waste of AM port bandwidth.

[0009]

SUMMARY OF THE INVENTION The foregoing object of the present invention is to provide at least one RAM having a plurality of first memory cells interconnected in a plurality of rows and a plurality of columns.
a VRAM section consisting of a plurality of second memory cells; a SAM section consisting of a plurality of second memory cells;
This is realized by data transfer means between M. Data from at least two row portions of the RAM are then transferred to the SAM substantially simultaneously.

According to another feature of the invention, a video RAM
comprises a random access memory portion having a plurality of memory cells arranged in rows and columns, a serial access memory portion, serial access means for allowing external access to the serial access memory portion, and a random access memory portion; It consists of control logic that controls data transfer between the memory section and the serial access memory section. The control logic serially accesses the first set of selected columns of the first row of the random access memory portion.
Simultaneously connects to memory portions, and also allows random access
A second set of selected columns of a second row of the memory portion is coupled simultaneously to the serial access memory portion.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a conventional VRAM configuration. It consists of a RAM array 1, a SAM array 2, an address control logic 3, and a transfer gate 4. The RAM array is connected to the first RAM port 5 of the VRAM and operates like a DRAM under the control of address control logic. The SAM array is connected to the second (SAM or serial) port 6 of the VRAM and is connected to the external asynchronous clock serial
It is accessed serially under the control of clock 7. S.A.
Serial access to M is controlled by a tap pointer (TAP) 8, which generates an address to the SAM from a counter that increments in serial clock cycles. The tap pointer (TAP) can be loaded with an initial address under the control of address control logic. Address control logic 3 manages address multiplexing and data processing of RAM port 5, and
provides all control and overall timing functions. Transfer gate 4 allows memory data transfer between RAM array 1 and SAM array 2 under the control of address control logic 3.

A read data transfer cycle in a conventional VRAM is shown in FIGS. 2 and 3. A read data transfer cycle is indicated by setting DT/OE low on the falling edge of the row address strobe (RAS). The row address (R
) is obtained from the address input and row R is activated. On the falling edge of the column address strobe (CAS), the column address (C) is obtained from the address input. Then, on the rising edge of DT/OE, the actual RA
Data transfer from M to SAM occurs. In a data transfer, the SAM is loaded with the contents of the RAM array row (R) and the tap pointer (TAP) is loaded with the column address (C). On the rising edge of the serial clock after the actual data transfer, the SA
New contents of M can be obtained. That is, on the first rising edge of the serial clock, start at the SAM location given by the tap pointer value. The first term of the serial data is "R;C", that is, the data in row R, column C. “R;C:C+4” is row 5 column C to C
It means 5 data items up to +4. This description will be used throughout the description. Each successive rising edge of the serial clock increments the tap pointer and outputs the contents of SAM serially to the SAM port. i.e. “R;C”, “R;C+1” and “R;C+”
2”. If the read data transfer is accomplished with the serial clock inactive, as shown in Figure 2, the timing of the transfer is critical because no data is being transferred to the display. However, as shown in Figure 3, if the read data transfer is accomplished while the serial clock is running, the DT/O
Data transfers that occur on E rising edges occur precisely in time between precise serial clock cycles;
Accurate data sequence at the SAM port must be maintained.

If the tap pointer reaches the final address of the SAM, on the next rising edge of the serial clock the address returns to zero, addressing the start of the SAM. Then, the subsequent serial clock
Incremented from zero by cycle. This is generally undesirable since the data sequence available at the SAM port is discontinuous due to jumping from the end of a row to the start of the same row.

In a memory system in accordance with an embodiment of the present invention, on the falling edge of RAS, a row address (R) is taken from the address input and two rows (R and R+1) are activated. On the falling edge of CAS, the column address (C) is obtained from the address input. Data transfer is
This is done between the two RAM arrays (R and R+1) and the SAM. Data is transferred from the RAM array row (R) column (C) to the end of the row and from the SAM location (C) to the end of the row. Additionally, the data is stored in row (R+1) column locations 0 through C-1 of the RAM array and in the SAM
This is also done between locations 0 and C-1. In other words, when the tap pointer returns to zero it will address the new row R+1. This is expressed as follows.

SAM(C:END)=R;C:ENDSAM(0:C
-1)=R+1;0:C-1 This can be shown in a single expression as follows. SAM(0:END)=R+
1;0:C-1 | R;C:END In these expressions, the parameter END indicates the last column address of the row and the last address of the SAM. dyadic operator “
‖” represents concatenation. We call this data transfer form column fold data transfer (CWDT). Column address (C)
forms the boundary of the CWDT.

In this way, after the CWDT read data transfer, the SAM will move to address R starting from SAM(C).
This includes a complete row of continuous data from ;C to R+1;C-1. This data is continuous in the RAM address space and the CWD corresponding to SAM(C)
T boundary R; starts from C, includes up to the end of SAM, and further reaches R+1; C-1 corresponding to SAM (C-1). The above is shown in FIG. 4 as a SAM map and its contents.

The CWDT functionality is used as a replacement or supplement to the conventional data transfer access available in current VRAMs. For VRAMs that provide both CWDT and conventional data transfer, it is necessary to differentiate between them by functional pins or other suitable means. In this embodiment, the CWDT functionality is used as a replacement for conventional data transfer.

The RAM array is divided into at least two segments, and at least one row address bit (including the least bit) is used to select a segment, and the remaining row address bits are used to select a row within each segment. It is advantageous to be Such memory segmentation is used in large memories to reduce loading on individual matrices. This reduces signal generation and propagation delays, and also reduces data rate variation and power consumption. According to the memory according to the invention, the segmentation of the memory allows the simultaneous activation of multiple rows to be simplified by placing the rows logically in sequential order within physically divided segments.

FIG. 5 is a block diagram of a VRAM having a RAM array divided into two physically separate segments. One segment contains all even rows and the other segment contains all odd rows. Each segment has a separate transfer gate (9, 10), and under the control of address control logic (14), the RAM array segment (
11, 12) and the SAM array (13). The RAM port (15) operation of the VRAM does not change, only the SAM port (16) operation changes due to the CWDT function.

In FIG. 5, the CWDT data transfer is performed using address control logic (14) with two rows (R of each segment).
and R+1) and select each transfer gate to open, allowing selective data transfer between the two rows and the SAM. For data transfer of row address R column address C, the address control logic is connected to the transfer gate (C
:END) is selected for the segment containing row R, and transfer gate (0:C-1) is selected for the segment containing row R+1. In this way, the CWDT boundaries are quantized in a single column subdivision, and the column address (C) must be fully decoded for transfer gate selection. However, in many cases the CWDT boundary is subdivided into coarser subdivisions (
For example, it is sufficient to quantize at 2, 4, 8, 16, 32, . . . column boundaries). This reduces column address decoding requirements and transfer gate selection in CWDT boundary organization. The invention also has useful applications where the CWDT boundary refinement is fairly coarse. If only the three most significant bits of column C are decoded, the transfer gates are divided into eight separate blocks along the length of the row. In the most extreme case, only the highest bit of column C is used to select the transfer gates in two blocks.

Although CWDT will be discussed in terms of read data transfer (RAM to SAM), such as when utilized in the display memory subsystem, the current VR
Write data transfers (SA
Application examples can also be found for M to RAM). Although write data transfer (SAM to RAM) applications are not discussed, they are within the scope of the present invention and will be apparent to those skilled in the art.

The present invention provides two CWDT configurations. The difference between the two forms is simply whether the tap pointer (17) is updated or not. The first CWDT configuration, referred to as CWDT#1, is similar to conventional read data transfer, and during data transfer, the tap pointer has a CAS
The column address (C) is loaded on the falling edge of . A second CWDT type, referred to as CWDT #2, differs from conventional read data transfers in that the tap pointer is not changed during data transfer. Both forms of CWDT are utilized when the serial clock is inactive or running. CWDT #1 is expected to be more utilized when the serial clock is inactive, while CWDT #2 is expected to be more utilized when the serial clock is running. CWDT#
1 updates the contents of both the SAM and the tap pointer. Therefore, when a serial clock is used on the fly, data transfers must occur in exact synchronization with the serial clock cycle. CWDT#2 updates only the SAM contents. CWDT#2 is serial
If performed while the clock is running, data transfers do not need to be precisely synchronized to the serial clock.

FIGS. 6 and 7 are diagrams showing two types of CWDT. FIG. 6 is CWDT #1 and shows read data transfer when the serial clock is inactive. Figure 7
is CWDT #2 and indicates a read data transfer when the serial clock is active. In embodiments of the invention, the two CWDT configurations are distinguished by the level of CAS at the rising edge of DT/OE. If CAS is low on the rising edge of DT/OE, the tap pointer is updated and the CWDT shown in FIG.
It becomes #1. On the other hand, if CAS is at a high level at the rising edge of DT/OE, the tap pointer is not updated and becomes CWDT #2 as shown in FIG.

As seen in conventional VRAMs, a read data transfer cycle is indicated by DT/OE being low on the falling edge of RAS. On the falling edge of RAS, the row address (R) is taken from the address input, and two rows (R of another segment)
and R+1) are activated. On the falling edge of CAS, the column address (C) is obtained from the address input. Column addresses (C) form the boundaries of the CWDT. Subsequently, on the rising edge of DT/OE, the actual RAM
Data transfer from to SAM occurs. The level of CAS at the rising edge of DT/OE determines whether the tap pointer (TAP) is loaded with column address C, CWDT #1 or CWDT #2. This is one particular means of controlling CWDT functionality. Other means may be devised by varying the relative timing, polarity, and operating function of the control inputs. The actual operation of a CWDT access depends on several factors, such as whether the CWDT feature is provided as a replacement or a supplement to traditional data transfer access.

In data transfer, SAM has R+1;
0:C-1‖R;C:END is loaded, the contents of RAM arrays R and R+1 are separated by the CWDT boundary, and the CWD
If the T access is CWDT#1, tap pointer (
TAP) is loaded with column address C. On the first rising edge of the serial clock after the actual data transfer, the new contents of SAM are output to the SAM port. On the first serial clock rising edge, it starts at SAM location R;C given by the tap pointer value. Continuing serial
On the rising edge of the clock, the tap pointer is incremented and the SA serially sent to the SAM port.
Output the contents of M. That is, R;C followed by R;C+
1, R; C+2, etc. When the tap pointer reaches the last location in the SAM, on the next rising edge of the serial clock, the value returns to zero, addressing the start of the SAM, and again increments from zero on each rising edge of the serial clock. continue. The serial data sequence near the tap pointer wraps is R; END-1,
R; END, R+1; 0, R+1; 1, R+1; 2. In this manner, the serial data sequence transitions seamlessly and continuously in the RAM address space across row boundaries.

CWDT#2 read data transfer (Figure 7)
In this case, the tap pointer is not updated, the serial clock is active to maintain the serial data sequence seamlessly and to avoid critical timing of data transfer, and the data transferred to the SAM is not actually updated. The previous S in the tap pointer area during data transfer.
Similar to and overlapping with AM data. To represent this, in FIG. 7, data in the SAM before data transfer is represented by R;0:C+8||R-1;C+9:END. This data was loaded into the SAM in the previous CWDT at row address R-1 column address C+9. For data transfer, SAM has R+1;0:C-1‖
R;C:END is loaded. SAM location S
The data of AM (C:C+8) is not changed by data transfer and is held as R;C:C+8. This area where the data does not change is called an overlap area.

This can be better understood by the SAM map and contents shown in FIG. 8 and the following table.

[0028]

In the timing diagram of FIG. 7, the actual data transfer is shown to occur when the tap pointer has a value of C+4. On the first rising edge of the serial clock after the actual data transfer, R;C+4
The new contents of SAM starting at is available at the SAM port. CWDT#2 data transfer does not change or affect the tap pointer increment sequence. Therefore, data transfers do not need to be critically synchronized within the serial clock stream if the tap pointer is set somewhere in the overlap region SAM(C:C+8) at the time of data transfer. That is, the critical timing is of no interest since the data within the overlap region does not change as a function of CWDT operation. The size selection of the overlap region is based on system constraints to ensure seamless serial data. In FIG. 7, the serial data sequence seamlessly progresses continuously from R-1;C+9 to R+1;C-1, with approximately two rows joined by a single CWDT#2 access. Furthermore, the sequence is extended by the next CWDT#2 access. This is accomplished without real-time data transfer.

Here, midline reload by conventional real-time read data transfer is performed using a transfer window (T
RANSFER WINDOW). In contrast, CWDT#2 read data transfer requires a transfer window corresponding to the width of the overlap area.

As an extension of the CWDT data transfer access described above, it is possible to apply different values to the CWDT boundaries and update the tap pointers. On the falling edge of CAS, the CWDT boundary is taken from the address input. If CAS is active low (eg, CWDT #1), the value that updates the tap pointer is taken from the address input on the rising edge of DT/OE. In this way, the CWDT boundary and tap pointer can take on different values.

FIG. 9 is a block diagram of a display system using a memory according to the present invention. The workstation has a central processing unit (CPU) of 20, a read-only storage device (R
The system includes an operating system (OS) 22, a random access memory 24, a data storage disk device 26, a user interface 28 such as a keyboard or mouse, and a display device 30 via a display adapter 32. These units are connected by a system bus 34. The display adapter 32 includes a display memory requiring VRAM according to the present invention, the RAM portion being updated via the RAM port and the serial access port being used to provide data to be rasterized on the display screen 30. Ru. It should be mentioned that this is only one embodiment of the display system according to the invention. A main frame computer with display devices and display adapters for each user of multiple users.
Many other implementations are possible, such as data processing systems.

The present invention simply and efficiently achieves full utilization of the SAM portion within the VRAM. Each CWDT read data transfer loads the SAM with consecutive data in a RAM address space starting at the CWDT boundary and having a length equal to the total SAM capacity. Starting at a CWDT boundary allows serial data sequences to seamlessly transition across row address boundaries. Then, sequential data within the total SAM capacity is provided until the next data transfer request occurs. Traditional read data transfers do not allow serial data sequences to transition across row address boundaries without real-time data transfer. Conventional read data transfers simply utilize the full capacity of the SAM only when the column address of the display memory subsystem, etc. is 0.

By utilizing the full capacity of the SAM, the present invention eliminates the need for "midline reloads" in the display memory subsystem. Additionally, the present invention reduces the number of VRAM data transfers required for each display frame. System limit is “midline reload”
CWD when it prevents complete avoidance or when it is advantageous to use “midline reload”.
T#2 data transfer provides a means to eliminate the real-time nature of "midline reloads." Real time V
By removing the need for RAM data transfer, CW
DT eliminates the need for potentially complex and high speed circuitry required to synchronize and control such data transfers, and the potential wasted use of RAM port bandwidth in synchronizing data transfers. I can do it.

It would also be advantageous in the present invention if CWDT were utilized as a substitute for or supplement to conventional data transfer access in current VRAMs. So far, CW
Although DT has been explained in connection with read data transfer (RAM to SAM) such as in display memory systems, it can also be used in applications related to write data transfer (SAM) found in current VRAM. It is possible.

[0036]

[Effects of the Invention] As explained above, according to the present invention,
Utilizing the full capacity of the SAM eliminates the need for "midline reloads" in the display memory subsystem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional VRAM.

FIG. 2 is a timing diagram illustrating a conventional read data transfer cycle when the serial clock is inactive.

FIG. 3 is a timing diagram illustrating a conventional read data transfer cycle when the serial clock is active, referred to as real-time data transfer.

FIG. 4 is a map diagram of a serial access memory after column-folded read data transfer according to the present invention.

FIG. 5 is a block diagram of a video random access memory of the present invention in which the RAM portion is divided into two segments.

FIG. 6 is a timing diagram illustrating a first form of column fold read data transfer when the serial clock is inactive.

FIG. 7: When the serial clock is active,
FIG. 7 is a timing diagram showing a second form of column folding read data transfer.

FIG. 8 is a map diagram of the serial access memory before and after the column-folded data transfer according to the second embodiment when the serial clock is active;

FIG. 9 is a block diagram of a display system using memory according to the present invention.

Claims (18)

[Claims] 1. A SAM comprising at least one RAM portion comprising a plurality of first memory cells interconnected in a plurality of rows and a plurality of columns, and a plurality of second memory cells.
and data transfer means between the RAM portion and the SAM portion for substantially simultaneously transferring data from the portion comprising at least two rows of the RAM to the SAM;
A VRAM characterized by comprising: 2. Both of the at least two rows are coupled to column N, and data is stored in columns 0 to C-1 (0<C-1<N ) The VRA according to claim 1, wherein the VRA is transferred from
M. 3. The VRAM according to claim 2, wherein data is transferred from columns C to N of said columns coupled to the other of said at least two rows. 4. A random access memory portion comprising a plurality of memory cells arranged in rows and columns, a serial access memory portion, and serial access means for permitting external access to the serial access memory portion.
a first set of selected columns of a first row of the random access memory portion to the serial access memory portion;
data transfer between the random access memory portion and the serial access memory portion, further simultaneously coupling a second set of selected columns of a second row of the random access memory portion to the serial access memory portion; A memory device comprising: a control logic for controlling; 5. The random access memory portion is divided into at least two segments in which logically adjacent rows are arranged in different segments. memory device. 6. The memory device according to claim 5, wherein the first row is arranged in a first segment, and the second row logically adjacent to the first row is arranged in a second segment. . 7. The memory device of claim 6, wherein each of the first and second segments is coupled to N columns, columns 0 through N, respectively. 8. The first selected column set is 0<C-1<N
8. The memory device according to claim 7, wherein the memory device is comprised of columns 0 to C-1. 9. The memory device of claim 8, wherein the second selected column set is comprised of columns C to N. 10. The second selected column set is 0<C-1<N.
8. The memory device according to claim 7, wherein the memory device is comprised of columns 0 to C-1. 11. The memory device of claim 10, wherein the first selected column set is comprised of columns C to N. 12. The memory device according to claim 9, wherein in the next data transfer, the second selected column set is comprised of columns CY to N, where Y>1. 13. The memory device of claim 12, wherein the first selected column set is comprised of columns 0 to C-X, where X=Y-1. 14. The memory device according to claim 13, wherein columns C-Y to C-1 are accessed immediately after the second data transfer. 15. The memory device of claim 4, further comprising a pointer loaded with an initial address indicating a storage location within the serial access memory portion to be accessed by the serial access means. . 16. Simultaneously with the data transfer between the random access memory portion and the serial access memory portion, the address stored by the pointer is updated with the selected column value. 16. The memory device according to item 15. 17. Simultaneously with data transfer between the random access memory portion and the serial access memory portion, the address stored by the pointer is updated with a value different from the selected column value. 16. The memory device of claim 15. 18. A central processing unit, a display device, and a video RAM receiving instructions from the central processing unit to provide data to the display device;
The AM includes at least one RAM portion consisting of a first plurality of memory cells interconnected in a plurality of rows and columns;
and a data transfer means between the RAM section and the SAM section, by which data is simultaneously transferred from at least two row sections of the RAM to the SAM. display system.