JP2744854B2 - VRAM, memory device and display system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device capable of high-speed serial data transfer to peripheral devices such as a raster display device.

[0002]

2. Description of the Related Art Video random access memory (VRAM) is the memory typically used in video display devices in computer systems. VRAM is essentially a conventional dynamic random access memory (DRAM) with the addition of a second port through which data is accessed serially. VRAM is a random access memory (RAM) part, serial
Access memory (SAM) part, RAM and SAM
And a transfer gate that controls data transfer between them. The SAM array usually has a memory capacity of one row of the RAM array.
All rows of memory data are transferred between RAM and SAM with a single data transfer access. RAM port and S
The AM port operates asynchronously and independently except during data transfer between the RAM and the SAM.

The operation of the two independent, asynchronous ports is such that the RAM port is used to update the contents of the display memory, and the serial port is used to provide the data to be rasterized on the screen. -Used for applications in system video display. The RAM port operates at the frequency of the computer system, and the SAM port operates at the frequency indicated by the raster display request. The SAM array usually has a capacity for one row of display data, and the display data of a new row is continuously reloaded within the display frame time. Generally, each new row display data is obtained from a row having one index larger than before. SAM from RAM array
The reloading of the array with new row display data is performed in the RAM port data transfer cycle. The data transfer cycle between the RAM array and the SAM array is the only interrupt to the normal RAM access cycle of the RAM port. This transfer cycle is classified into two types. The first is data transfer when the SAM port is inactive and no data is transferred to the raster display, and the serial clock is stopped. This usually involves reloading the SAM during the blanking period of the display frame.
The second is when the SAM port is active and data is transferred to the raster display. In this case, a serial clock is occurring and the data transfer cycle of the RAM port requires precise synchronization with the serial clock to maintain a continuous data request from the SAM port to the raster display. This second state is often called "real-time data transfer" or "midline reload".

In the design of the display memory subsystem, control and timing of such midline reloads is a major problem. Midline reload
Critical time-controlled real-time access that requires synchronization between the RAM port and the SAM port wastes RAM port bandwidth and other significant elements in many display memory subsystems. Further, real-time access with such critical time control potentially requires complex and fast circuits for synchronization and control. Thus, designers have traditionally avoided midline reloads and avoided critical timing control or the associated complex circuitry. Conventional methods for avoiding midline reload have a number of limitations on how the contents of the display memory are mapped on the display screen. These restrictions are shown below. (1) The start address for the display data on the first horizontal scanning line of the display frame is fixed. (2) The start address of each horizontal scanning line thereafter is generated by increasing the fixed address. (3) The horizontal scanning line length that requires the capacity for display data is
It should not be larger than the SAM array capacity of the VRAM in the display memory subsystem. In the past, all these constraints had to be satisfied to avoid midline reloads. It should be noted here that these constraints are not applicable to general purpose graphic adapters or display memory subsystems.

Second generation VRAM has advanced to the ability to transfer half a row of random access memory to half a SAM. On the other hand, the other half of the SAM is scanned out to the display device. This means of avoiding real-time data transfer is used in 1 megabit multiport DRAMs and is generally described in US Pat. No. 4,825,411.
No. 4,855,959. These so-called “Split Registers” V
In RAM, the SAM array is split into two, each handled independently by a method called "split register data transfer" in which one SAM is active while the other is loaded. Typically, the output status pin is configured to indicate which SAM is being scanned out.

While split register VRAM somewhat mitigates midline reload, it does not fully and efficiently utilize SAM array capacity, and potentially doubles data transfer access.

[0007]

SUMMARY OF THE INVENTION The present invention provides a simple and efficient means of making full and efficient use of SAM and avoiding such "midline reload" under certain circumstances. With the goal.

[0008] Also, if system constraints prevent the avoidance of total "midline reload", or for whatever reason it is advantageous to use "midline reload", remove real-time performance However, it is a second object of the present invention to eliminate such critical timing. By eliminating the need for real-time VRAM data transfer, the present invention eliminates the need for potentially complex and high speed circuits required for such data transfer synchronization and control, and the R related to such data transfer synchronization.
It also eliminates the potential waste of AM port bandwidth.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide at least one RA having a plurality of first memory cells interconnected in a plurality of rows and a plurality of columns.
A VRAM constituted by an M portion; a SAM portion constituted by a plurality of second memory cells;
This is realized by data transfer means between AMs. In so doing, data from at least two row portions of the RAM is transferred substantially simultaneously to the SAM.

According to another feature of the invention, the memory device or video RAM is a random access memory portion having a plurality of memory cells arranged in a matrix, a serial access memory portion, a serial access memory. Serial access means for permitting external access to the part, and a random access memory part and a serial access means.
It comprises control logic for controlling data transfer between the access and memory portions. The control logic simultaneously couples a first selected column set of a first row of the random access memory portion to a serial access memory portion, and reconfigures a second selected column set of a second row of the random access memory portion. Simultaneously couple to the serial access memory part. Further, the control logic includes a first selected column set of the first row and a second selected row of the first row such that at least one of the two selected column sets partially overlaps data of a previous data transfer in the serial access memory portion. Is transferred to the second selected column set.

[0011]

FIG. 1 shows a conventional VRAM configuration. It comprises a RAM array 1, a SAM array 2, address control logic 3, and a transfer gate 4. The RAM array is connected to the first RAM port 5 of the VRAM and operates like a DRAM under the control of address control logic. The SAM array is connected to the second (SAM or serial) port 6 of the VRAM and has an external asynchronous clock serial
It is accessed serially under the control of clock 7. SA
Serial access to M is controlled by a tap pointer (TAP) 8 that generates an address to the SAM from a counter that increments in a serial clock cycle. The initial address of the tap pointer (TAP) can be loaded under the control of the address control logic.
Address control logic 3 manages address multiplexing and data processing of RAM port 5,
Provides all control and overall timing functions of The transfer gate 4 permits the transfer of memory data between the RAM array 1 and the SAM array 2 under the control of the address control logic 3.

FIGS. 2 and 3 show a read data transfer cycle in a conventional VRAM. The read data transfer cycle is shown with DT / OE set to low level at the falling edge of the row address strobe (RAS). On the falling edge of RAS, the row address (R) is obtained from the address input, and row R is activated. On the falling edge of the column address strobe (CAS), the column address (C) is obtained from the address input. Thereafter, data is actually transferred from the RAM to the SAM at the rising edge of DT / OE. In the data transfer, the contents of the RAM array row (R) are loaded into the SAM, and the column address (C) is loaded into the tap pointer (TAP). At the rising edge of the serial clock after the actual data transfer, new contents of the SAM are obtained at the SAM port. That is, starting at the SAM location given by the tap pointer value on the first rising edge of the serial clock. The first term of the serial data is "R;C", that is, data of row R and column C. "R; C: C + 4" means five data items from column C to row C of row R. This description is used throughout the description. Each successive rising edge of the serial clock increments the tap pointer and outputs the contents of the SAM serially to the SAM port. That is, "R;C","R; C + 1", and "R; C + 2". If the read data transfer is accomplished with the serial clock inactive, as shown in FIG. 2, the timing of the transfer is not critical because no data has been transferred to the display device.
However, as shown in FIG. 3, when the read data transfer is accomplished while the serial clock is running, the DT / O
The data transfer that occurs on the rising edge of E occurs exactly in time during the exact serial clock cycle,
The exact data sequence at the SAM port must be maintained.

If the tap pointer reaches the last address of the SAM, on the next rising edge of the serial clock, the address returns to zero, addressing the start of the SAM. And the subsequent serial clock
Incremented from zero by cycle. This is generally undesirable, as it jumps from the end of a row to the start of the same row, resulting in a discontinuous data sequence at the SAM port.

In a memory system according to an embodiment of the present invention, a row address (R) is obtained from the address input on the falling edge of RAS, and two rows (R and R + 1) are activated. At the falling edge of CAS, the column address (C) is obtained from the address input. Data transfer is
This is performed between the two RAM arrays (R and R + 1) and the SAM. Data is transferred from the row (R) column (C) of the RAM array to the end of the row and from the SAM location (C) to the end of the row. In addition, the data is stored in row (R + 1) column locations 0 through C-1 of the RAM array and the SAM
This is also performed between locations 0 to C-1. In other words, when the tap pointer returns to zero, it will address a new row R + 1. This is expressed as:

SAM (C: END) = R; C: END SAM (0: C-1) = R + 1; 0: C-1 This can be represented by a single expression as follows. SAM (0: END) = R + 1; 0: C-1‖R; C: END In these expressions, the parameter END indicates the last column address of the row and the last address of the SAM. The dyadic operator “‖” represents concatenation. We refer to this form of data transfer as column-folded data transfer (CWDT). The column address (C) forms the boundary of the CWDT.

Thus, after a CWDT read data transfer, the SAM will contain a complete row of continuous data from address R; C to R + 1; C-1 starting at SAM (C). . This data is continuous in the RAM address space and the CW corresponding to SAM (C)
DT boundary R; starting at C, including to the end of the SAM,
Further, it reaches R + 1; C-1 corresponding to SAM (C-1). The above is shown in FIG. 4 as a SAM map and its contents.

The CWDT function is used as a substitute for, or as a supplement to, conventional data transfer access available in current VRAMs. For a VRAM that provides both CWDT and conventional data transfer, it is necessary to distinguish between them by functional pins or other suitable means. In this embodiment, the CWDT function is used as a substitute for the conventional data transfer.

The RAM array is divided into at least two segments and is used to select a segment by at least one bit (including the least significant bit) of a row address, and to use the remaining row address bits to select a row in each segment. It would be advantageous to Such memory segmentation is used in large memories to reduce the load on individual matrices. This reduces signal generation and propagation delays, as well as data rate changes and power consumption. According to the memory according to the invention, the segmentation of the memory makes it possible to simplify the simultaneous activation of a plurality of rows by arranging the rows sequentially in a logical manner in the physically divided segments.

FIG. 5 is a block diagram of a VRAM having a RAM array divided into two physically separate segments. One segment contains all the even rows and the other segment contains all the odd rows. Each segment has a separate transfer gate (9, 10) and controls memory data transfer between the RAM array segment (11, 12) and the SAM array (13) under the control of the address control logic (14). The operation of the RAM port (15) of the VRAM does not change, and only the operation of the SAM port (16) changes by the CWDT function.

In FIG. 5, the CWDT data transfer is such that the address control logic (14) uses two rows (R in each segment).
And R + 1), selecting each open transfer gate, and allowing selective data transfer between the two rows and the SAM. For data transfer of row address R, column address C, the address control logic selects the transfer gate (C: END) for the segment including row R and the transfer gate (0: C-1) for the segment including row R + 1. select. In this way, CWDT boundaries are quantized in a single column subdivision, and the column address (C) must be fully decoded for transfer gate selection. However, it is often sufficient to quantize the CWDT boundaries at coarser subdivisions (eg, 2, 4, 8, 16, 32... Column boundaries). This reduces column address decode requirements and transfer gate selection in CWDT boundary organization. The present invention also has a useful application where the CWDT boundary refinement is rather coarse. If row C
Is decoded, the transfer gate is divided into eight separate blocks along the length of the row. In the most extreme case, only the highest bit of column C is used to select a transfer gate divided into two blocks.

The CWDT will be described with respect to read data transfer (RAM to SAM) as it is used in the display memory subsystem, but the current VR
Write data transfer as seen in AM (SA
Application examples can also be found for M to RAM). An application to write data transfer (SAM to RAM) is not described but is included in the scope of the present invention and will be apparent to those skilled in the art.

The present invention provides two CWDT configurations. The two forms are simply the difference between whether or not the tap pointer (17) is updated. The first called CWDT # 1
Is similar to the conventional read data transfer, and at the time of data transfer, the tap pointer has a CA
At the falling edge of S, the column address (C) is loaded. In the second CWDT form called CWDT # 2, unlike the conventional read data transfer, the tap pointer is not changed at the time of data transfer. Both forms of CWDT are used when the serial clock is inactive or running. CWDT # 1 is more likely to be utilized when the serial clock is inactive, while CWDT # 2 is more likely to be utilized when the serial clock is running. CWDT
# 1 updates the contents of both the SAM and the tap pointer. Thus, if the serial clock is used on the fly, the data transfer must occur exactly in sync with the serial clock cycle. In CWDT # 2, only the SAM content is updated. If CWDT # 2 is performed during the serial clock run, the data transfer need not be exactly synchronized to the serial clock.

FIGS. 6 and 7 show two forms of CWDT. FIG. 6 shows CWDT # 1 and shows read data transfer when the serial clock is inactive. FIG.
CWDT # 2 indicates read data transfer when the serial clock is active. In an embodiment of the present invention, the two CWDT configurations are distinguished by the level of CAS at the rising edge of DT / OE. If CAS
Is low at the rising edge of DT / OE, the tap pointer is updated and CWD shown in FIG.
It becomes T # 1. On the other hand, if CAS is at the high level at the rising edge of DT / OE, the tap pointer is not updated and becomes CWDT # 2 shown in FIG.

As seen in a conventional VRAM, a read data transfer cycle is indicated by DT / OE being low at the falling edge of RAS.
At the falling edge of RAS, a row address (R) is obtained from the address input and two rows (R
And R + 1) are activated. At the falling edge of CAS, the column address (C) is obtained from the address input.
The column address (C) forms the boundary of the CWDT. Subsequently, at the rising edge of DT / OE, the actual RAM
Data transfer from the SAM to the SAM occurs. The level of CAS at the rising edge of DT / OE determines whether the column address C is loaded into the tap pointer (TAP), ie, CWDT # 1 or CWDT # 2. This is one specific means of controlling the CWDT function. Other means can be devised by changing the relative timing, polarity, and operating function of the control input. CWD
The actual operation of T-access depends on several factors, such as whether the features of the CWDT are provided as a substitute for, or supplement to, conventional data transfer access.

In the data transfer, the SAM has R + 1;
0: C-1‖R; C: END is loaded, the contents of RAM arrays R and R + 1 are separated by a CWDT boundary, and CWD
When the T access is CWDT # 1, the column address C is loaded into the tap pointer (TAP). At the first rising edge of the serial clock after the actual data transfer, the new contents of the SAM are output to the SAM port. At the rising edge of the first serial clock, the SAM given by the tap pointer value
Starting from location R; C. On the following rising edge of the serial clock, the tap pointer is incremented and serially sent to the SAM port.
Output AM contents. That is, R; C followed by R; C
+1, R; C + 2, etc. Tap·
When the pointer reaches the last location of the SAM, on the next rising edge of the serial clock, the value returns to zero, addressing the start of the SAM, and continues incrementing from zero again at each rising serial clock. . The serial data sequence in the vicinity of the return of the tap pointer is R; END-
1, R; END, R + 1; 0, R + 1; 1, R + 1; 2
Becomes In this way, the serial data sequence spans row boundaries and is seamless and continuous in RAM.
Migrate in address space.

CWDT # 2 read data transfer (FIG. 7)
The tap pointer is not updated, the serial clock is active to maintain the serial data sequence seamlessly and to avoid critical timing of data transfer, and the data transferred to the SAM is The previous S in the tap pointer area at the time of data transfer
As with the AM data, they overlap. To indicate this, in FIG. 7, data in the SAM before data transfer is represented by R; 0: C + 8‖R-1; C + 9: END. This data has been loaded into the SAM in the previous CWDT of row address R-1 column address C + 9. In data transfer, the SAM has R + 1; 0: C-1.
‖R; C: END is loaded. The data at the SAM location SAM (C: C + 8) does not change due to the data transfer and is held as R; C: C + 8. An area where this data does not change is called an overlap area.

The map and contents of the SAM are shown in FIG. 8 and can be understood from the following table.

[0028]

In the timing diagram of FIG. 7, it is shown that the actual data transfer occurred when the tap pointer had a value of C + 4. At the rising edge of the first serial clock after the actual data transfer, R; C + 4
The new content of the SAM starting with is obtained at the SAM port. The CWDT # 2 data transfer does not change or affect the tap pointer increment sequence. Therefore, data transfer does not need to be critically synchronized in the serial clock stream if the tap pointer is set somewhere in the overlap area SAM (C: C + 8) at the time of data transfer. That is, the critical timing is not of interest because the data in the overlap region does not change as a function of the CWDT operation.
The size selection of the overlap area is based on system constraints to guarantee seamless serial data. In FIG. 7, the serial data sequence proceeds seamlessly from R-1; C + 9 to R + 1; C-1 in a seamless state, and approximately two rows are combined by a single CWDT # 2 access. Further, the sequence is extended by the next CWDT # 2 access. This is achieved without real-time data transfer.

Here, the conventional midline reload by real-time read data transfer requires a transfer window (TR) limited to a single serial clock cycle.
ANSFER WINDOW). On the other hand, CWDT
The # 2 read data transfer requires a transfer window corresponding to the size of the overlap area.

As an extension of the CWDT data transfer access described above, it is possible to apply different values to the CWDT boundary and update the tap pointer. On the falling edge of CAS, the CWDT boundary is obtained from the address input. If CAS is active low (eg, CWDT # 1), the value to update the tap pointer is obtained from the address input on the rising edge of DT / OE. In this way, the CWDT boundary and the tap pointer can have different values.

FIG. 9 is a block diagram of a display system using a memory according to the present invention. The workstation is a central processing unit (CPU) 20 and a read-only storage device (R).
(OS) 22, a random access memory 24, a data storage disk device 26, a user interface 28 such as a keyboard or a mouse, and a display device 30 via a display adapter 32. These units are connected by a system bus 34. The display adapter 32 includes a display memory requiring a VRAM according to the present invention, the RAM portion being updated via a RAM port, and a serial access port being used to provide data to be rasterized on the display screen 30. You. It must be mentioned that this is only one embodiment of the display system according to the invention. Main frame with display device and display adapter for each of multiple users
Numerous other embodiments are possible, such as a data processing system.

The present invention simply and efficiently achieves full utilization of the SAM portion in VRAM. Each CWDT read data transfer loads the SAM with continuous data in the RAM address space, starting at the CWDT boundary and having a length equal to the total SAM capacity. Starting at the CWDT boundary, the serial data sequence can transition seamlessly across row address boundaries. Then, the sequential data within the entire SAM capacity is provided until the next data transfer request occurs. Conventional read data transfers do not permit serial data sequences to migrate across row address boundaries without real-time data transfer. The conventional read data transfer simply uses the entire capacity of the SAM only when the column address of the display memory subsystem or the like is 0.

The present invention eliminates the need for "midline reload" in the display memory subsystem by utilizing the full capacity of the SAM. Further, the present invention reduces the number of VRAM data transfers required for each display frame. System limit is “Midline reload”
CWD if it prevents complete avoidance of, or if it is advantageous to utilize "midline reload"
T # 2 data transfer provides a means to eliminate the real-time nature of "midline reload". Real-time V
By eliminating the need for RAM data transfer, CW
DT eliminates the need for potentially complex and fast circuits required to synchronize and control such data transfers, and the potential waste of RAM port bandwidth in synchronizing data transfers. Can be.

In the present invention, it is advantageous if the CWDT is used as a substitute or supplement for the conventional data transfer access in the current VRAM. Up to here, CW
It has been described in connection with read data transfer (from RAM to SAM) when the DT is a display memory system, but is also used in application examples related to write data transfer (SAM) found in current VRAM. It is possible.

[0036]

As described above, according to the present invention,
Utilizing the full capacity of the SAM can eliminate the need for "midline reload" in the display memory subsystem.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional VRAM.

FIG. 2 is a timing diagram showing a conventional read data transfer cycle when the serial clock is inactive.

FIG. 3 is a timing diagram showing a conventional read data transfer cycle when a serial clock called a real-time data transfer is active.

FIG. 4 is a map diagram of the serial access memory after column folding read data transfer according to the present invention.

FIG. 5 is a block diagram of the video random access memory of the present invention in which the RAM portion is divided into two segments.

FIG. 6 is a timing diagram showing a first form of column folding read data transfer when the serial clock is inactive.

FIG. 7 when the serial clock is active;
FIG. 9 is a timing chart showing a second form of the column folding read data transfer.

FIG. 8 is a map diagram of the serial access memory before and after column-folded data transfer according to the second embodiment when the serial clock is active.

FIG. 9 is a block diagram of a display system using a memory according to the present invention.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Todd Williams, Kingshill Road, West Ford, Vermont, United States, Box 1015, Box R1 (no address) (56) References JP, A) JP-A-2-81397 (JP, A) JP-A-60-162287 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/401 G06T 1/60

Claims (13)

(57) [Claims] 1. A random access memory comprising a plurality of memory cells arranged in a matrix and accessed by a column address signal C and a row address signal R; a serial access memory; Serial access means for permitting external access to the first row and a second selected column set of a first row and a second row determined by the column address C of the random access memory. Control logic, coupled to the access memory, for controlling data transfer between the random access memory and the serial access memory , wherein the control logic comprises at least one of the two selected column sets.
One part is part of the serial access memory
Before overlapping with the data of the previous data transfer
A first selected column set of the first row and a second selected column of the second row
A memory device for transferring a set . 2. The memory according to claim 1, wherein in the random access memory, logically adjacent rows are divided into at least two segments arranged in different segments. apparatus. 3. The memory device according to claim 2, wherein the first row is arranged in a first segment, and the second row logically adjacent to the first row is arranged in a second segment. . 4. The memory device according to claim 3, wherein each of said first and second segments are respectively combined into (N + 1) columns from column 0 to column N. 5. The method according to claim 1, wherein the first selected column set is 0 <C-1 <N
The memory device according to claim 4, wherein the memory device is configured by columns 0 to C-1. 6. The memory device according to claim 5, wherein said second selected column set is constituted by columns C to N. 7. The memory device according to claim 4, wherein said second selected column set includes columns 0 to C-1 where 0 <C-1 <N. 8. The memory device according to claim 7, wherein said first selected column set is constituted by columns C to N. 9. The memory device according to claim 6, wherein in the next data transfer, the second selected column set includes columns CY to N where Y> 1. 10. The method according to claim 1, wherein the first selected column set comprises columns 0 to C-
(Y-1).
A memory device according to claim 1. 11. Columns CY to N and 0 to C- (Y-
11. The memory device according to claim 10, wherein items up to 1) are accessed immediately after the data transfer. 12. The memory device according to claim 1, further comprising a pointer loaded with an initial address which is accessed by said serial access means and indicates a storage location in a serial access memory. 13. A central processing unit, a display device, and a video RAM for receiving instructions from said central processing unit to provide data to said display device, said video RAM comprising a plurality of rows and columns. At least one RAM consisting of a first plurality of memory cells interconnected to the SAM; a SAM consisting of a second plurality of memory cells;
And a data transfer means between the RAM and the SAM are transferred simultaneously to M, the data transfer means is less of data of the two lines
One of them is the SAM, and the other is partially
The data so as to overlap with the RAM
Transfer from at least two rows of the display system.