JPH04225461A - Recognizing system for system constitution - Google Patents

Abstract

PURPOSE:To recognize the system configuration a shorts period by attaining a configuration where each option board decides whether the bit of the data allocated previously to its own is equal to 0 or not when a write instruction is outputted to a common address of a system and then outputs the bit decided previously to a read instruction to the next common address of the system as 0 when the preceding bit of the data is equal to 0. CONSTITUTION:A personal computer main body 1 is connected to the option boards 20-22 via an extension bus 11. Each of boards 20-22 contains an address decoding circuit 5 which decodes a common address in a system and a register 6 which stores a prescribed data bit that is previously prescribed by the type of each function of the boards 20-22 when a write instruction is carried out to the common address. Then the value stored in the register 6 is outputted to the data bit decided to the read instruction given to the common address to be executed next.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system configuration recognition method, and more particularly to a system configuration recognition method for recognizing the system configuration of a personal computer system consisting of a personal computer main body and a plurality of option boards.

0002

[Prior Art] Generally, personal computer systems are required to be inexpensive, so they are configured with only the basic functions that most users use as standard functions included in the personal computer itself, such as telephones, etc. Functions such as connection to the line are provided as options in the form of boards, and users who require these boards purchase them separately and connect them to the personal computer to build a system.

Conventionally, this type of system configuration recognition method has been
In order to distinguish between additional optional functions, each board with optional functions is given a unique address (address), and the system program examines the results of data input commands to these unique addresses. The method is to determine whether or not the desired function is installed.

Furthermore, in this conventional system configuration recognition method, when allocating addresses to these options, an address area for option boards is set within the system, and as many addresses as necessary are allocated from there.

[0005]

[Problem to be Solved by the Invention] In the conventional system configuration recognition method described above, there is no regularity in address assignment for each option, so when trying to recognize the system configuration, access is performed in order according to the address assignment table. Checking whether an option board exists.

[0006] Therefore, there is a problem that it is not possible to recognize the options that have increased since the time when the program that recognizes the system configuration was designed.Furthermore, since the options are recognized one by one, it is difficult to recognize the entire system configuration. There is a problem in that it takes time to make a determination.

[0007]

[Means for Solving the Problems] The system configuration recognition method of the present invention is a system configuration recognition method for a personal computer system consisting of a personal computer main body having a general-purpose expansion bus and a plurality of option boards connected to the expansion bus. In the above, each of the plurality of option boards includes a decoding circuit that decodes a common address within the system, and a specific first decoding circuit that is predefined according to the type of function of the option board when a write command to the common address is executed. and a register for storing data bits of the option board, and when the value stored in this register is "0", the option board is unique to the read instruction to the common address that is executed next. It has an output means for outputting "0" to a predefined second data bit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a block diagram showing one embodiment of the present invention, and FIG. 1(b) is a circuit diagram showing an example of the internal circuit of each option board in FIG. 1(a).

In FIG. 1, in this embodiment, a personal computer main body 1 connects option boards 20, 21, and 22 via an expansion bus 11. Although the expansion bus 11 and option boards 20, 21, and 22 are shown separately from the personal computer main body 1 in FIG. 1, physically they are built into the personal computer main body 1.

In FIG. 1(b), the option board 2
Each internal circuit of 0, 21, and 22 receives an address decode circuit 3 that decodes a system common address, and an address match signal (S
YSAD) and a signal (IOW) indicating a write instruction from the expansion bus 11;
A flip-flop circuit (
DF) 6, an ADN circuit 5 that ANDs the SYSAD signal and a signal (IOR) indicating an instruction to output data to the expansion bus 11 when the value stored in DF6 is "0", and an AND circuit. 5 is "1", the data buffer 7 outputs data "0" to the data bus.

FIG. 2(a) is a diagram showing the data bit correspondence of the first classification for classifying the functions of the option board in this embodiment, and FIG. 2(b) is a diagram showing the data bit correspondence of the first classification classified in FIG. 3 is a diagram showing data bit correspondence in the case of line system as category 2, and FIG. 3 is a diagram showing an operation time chart of this embodiment.

In FIGS. 2A and 2B, the option boards 20, 21, and 22 of this embodiment are classified into two levels according to their functions. In other words, the first level is a rough classification of functions (line system, processor system, file system, etc.), and the second level is a detailed classification of functions broadly classified at the first level (line system, file system, etc.). If available, RS232/
RS422/ISDN, etc.).

The first classification is used for write instructions to a common address, and the second classification is used for read instructions to a common address.

In this embodiment shown in FIG. 1, the option board 20 is an RS232 1 line board and an option board 2.
1 is an ISDN board, and an option board 22 is a file system disk control board.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.
, and FIG. 3.

When the power is turned on, DF6 on all option boards 20, 21, and 22 is set to "1", and no data is output to the expansion bus 11 in response to an input command to a common address. ing.

When examining the system configuration, after a write command is executed to a common address with data bit 0 of the first classification set to "0", a read command is executed to the same address.

First, when a write command is executed, each of the option boards 20, 21, and 22 outputs an AND circuit 4 between the SYSAD signal generated by the address decoding circuit 3 and the IOW signal indicating that it is a write command. The data bus signal is stored in the DF6 by the ANDed signal. At this time, since only data bit 0 is "0", the D
"0" is stored in F6, and DF6 inside the option board 22, which is a file system, remains unchanged. If the memorized signal level is “0”, the option boards 20, 21
DF6 opens the data buffer 7 when the IOR signal indicating the next read command is issued, so the data bits 0 and 15 of the second category output from the option boards 20 and 21 are set to "0'', and the existence of the option boards 20 and 21 can be known.

Next, data bit 1 of the first classification is set to “0”.
”, when a write command and a read command are executed in the same procedure as described above, it is possible to check whether a file-based option board 22 exists or not.

[0021]

As explained above, in the system configuration recognition method of the present invention, when a write command to a system common address is output, each option board recognizes that the bit of data pre-assigned to itself is "0". ”, and outputs a predetermined data bit as “0” in response to a read command to the next system common address only when it is “0”. This has the effect of being able to recognize the presence or absence of an object in a shorter time than before by using the same procedure.

[Brief explanation of the drawing]

1(a) is a block diagram showing one embodiment of the present invention, and FIG. 1(b) is a circuit diagram showing an example of the internal circuit of each option board in FIG. 1(a).

[Fig. 2] (a) is a diagram showing the data bit correspondence of the first classification that classifies the functions of the option board in this embodiment, (b)
This is a diagram showing data bit correspondence in the case of a line system as the second classification among those classified in (a).

FIG. 3 is a diagram showing an operation time chart of this embodiment.

[Explanation of symbols]

1 Personal computer body 3 Address decoding circuit 4 AND circuit 5 AND circuit 6 Flip-flop circuit (DF) 7 Data buffer 11 Expansion bus

Claims (1)

[Claims] 1. In a system configuration recognition method for a personal computer system comprising a personal computer main body having a general-purpose expansion bus and a plurality of option boards connected to the expansion bus, each of the plurality of option boards has a comprising a decoding circuit for decoding a common address, and a register for storing a specific first data bit predefined by the type of function of the option board when a write instruction to the common address is executed; In addition, when the value stored in this register is "0", a second data bit predefined unique to the option board is set to "0" for the next read command to the common address. A system configuration recognition method characterized by having an output means for outputting.