JPH0422477Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field This invention relates to an offset voltage adjustment circuit for a sample-and-hold circuit used with an A/D converter.

(b) Prior Art Conventionally, as an offset voltage adjustment circuit for a sample and hold circuit, for example, as shown in FIG.
0, 21 and a semi-fixed resistor 22 for adjusting the offset voltage, and the slider 22c of the semi-fixed resistor 22 is connected to the inverting input terminal of the operational amplifier 23 to adjust the offset voltage. An offset voltage adjustment circuit for a sample and hold circuit has been provided.

(c) Problems that the invention attempts to solve However, in the above-mentioned conventional ones, (+)
Let Ra be the combined resistance value between the B power supply and the non-inverting input terminal of the operational amplifier 23, and let Rb be the combined resistance value between the (-) power supply and the non-inverting input terminal of the operational amplifier 23.
Then, the input impedance of the operational amplifier 23 becomes Ra・Rb/(Ra+Rb), and Ra, Rb
If the resistance is high, the input impedance of the operational amplifier 23 will be large and it will be susceptible to noise.
In addition, unless a stable power supply with little fluctuation is used for the (+)B power supply and (-)B power supply, the offset voltage will fluctuate, causing noise and other drawbacks such as the sample-and-hold circuit not operating stably. .

This invention has been made in view of the above points, and its purpose is to provide an offset voltage adjustment circuit for a sample and hold circuit that operates stably without being affected by noise.

(d) Means for solving the problem According to the offset voltage adjustment circuit of the sample-and-hold circuit according to this invention, the voltage adjustment circuit consists of a sampling analog switch, an operational amplifier, and a FET buffer amplifier used to increase the input impedance of this operational amplifier. In the offset voltage adjustment circuit of the phase inversion type sample and hold circuit, the voltage can be varied between the source of the FET of the FET buffer amplifier and the inverting input terminal of the operational amplifier, or between the inverting input terminal of the operational amplifier and the negative power supply. A resistor is provided to ensure that the sample and hold circuit operates stably without being affected by noise.

(E) Effect According to this invention, the non-inverting input of the operational amplifier of the sample-and-hold circuit can be directly grounded, so it is less susceptible to the influence of noise from the non-inverting input, and therefore, this sample-and-hold circuit operates stably. do.

(F) Embodiment An embodiment of this invention will be described based on FIGS. 1 and 2.

FIG. 1 is a circuit diagram of the main part, and FIG. 2 is a characteristic diagram showing the operating point of the FET used as a buffer amplifier in this circuit.

In the figure, "IN" is an input terminal, "OUT" is an output terminal, 1 is a resistor, 2 is an analog switch, 3 is a buffer FET used to increase the input impedance of the subsequent operational amplifier, and 4 is an offset. Semi-fixed resistor for adjusting the voltage, 5 is a resistor, 6 is an operational amplifier, 7 is a resistor for determining the voltage gain of the sample and hold circuit together with resistor 1, 8 is a capacitor for holding voltage during hold It is.

One terminal of a resistor 1 is connected to the input terminal "IN", and the other terminal of the resistor 1 is connected to the common terminal 2c of the analog switch 2.

One terminal 2h of analog switch 2 is grounded, and the other terminal 2s of analog switch 2 is grounded.
Connected to the gate of FET3.

The drain of FET3 is connected to the (+) power supply (not shown), and the source of FET3 is connected to the (-) power supply (not shown) through a series circuit of semi-fixed resistor 4 and resistor 5. are doing.

The slider 4c of the semi-fixed resistor 4 is connected to a line 6a connecting the semi-fixed resistor 4 and the resistor 5, and this line 6a is connected to the inverting input terminal of the operational amplifier 6. The non-inverting input terminal of the operational amplifier 6 is connected to ground, and the output line 6b of the operational amplifier 6 is connected to the terminal "OUT".

The output line 6b of the operational amplifier 6 and the common terminal 2c of the analog switch 2 are connected via a resistor 7, and the voltage gain of this sample and hold circuit is determined to a desired value.

Further, the output line 6b of the operational amplifier and the gate of the FET 3 are connected via a capacitor 8 to form an integrating circuit to maintain voltage during hold.

Next, the operation of the offset voltage adjustment circuit of the sample and hold circuit configured as described above will be explained.

Now, if the offset voltage of the operational amplifier 6 is completely adjusted by turning the semi-fixed resistor 4 while the common terminal 2c and the terminal 2s of the analog switch 2 are connected, then the non-inverting input of the operational amplifier 6 is grounded. Since the voltage at the non-inverting input is OV, the voltage at the inverting input is also OV. Since the voltage of the output line 6b is also OV, the gate voltage of the FET 3 is also OV.

Now, in order to operate FET3 at the operating point shown in FIG. 2, a gate bias voltage is required.

Since the voltage of the line 6a is OV, if the source current of the FET 3 is Ids, the gate voltage is Vg, and the resistance value of the semi-fixed resistor 4 is Rv, then the half current is set to satisfy the following formula Vg=Ids・Rv. By turning the fixed resistor 4, a necessary bias voltage Vg is applied to the gate of the FET 3, and a desired source current Ids flows, making it possible to accurately adjust the offset voltage of the operational amplifier 6 to OV.

In this embodiment, the source of the FET 3 and the inverting input of the operational amplifier 6 are connected through the semi-fixed resistor 4, but conversely, the source of the FET 3 and the inverting input of the operational amplifier are connected through a fixed resistor. Furthermore, the inverting input of the operational amplifier and the (-) power supply may be connected via a semi-fixed resistor.

Also, connect one terminal of the semi-fixed resistor to the source of FET3, connect the other terminal of this semi-fixed resistor to the (-) power supply, and connect the slider of this semi-fixed resistor and the operational amplifier. The purpose of this invention can also be achieved by connecting the inverting input of No. 6.

In the above embodiment, a semi-fixed resistor was used for adjusting the offset voltage, but any type of resistor may be used as long as the resistance value can be varied.

(g) Effects of the invention According to the offset voltage adjustment circuit of the sample-and-hold circuit according to this invention, the non-inverting input of the operational amplifier of the sample-and-hold circuit can be directly grounded, so that the non-inverting input is not affected by noise. Therefore, this sample and hold circuit operates stably.

Moreover, it has excellent features such as being able to be constructed at low cost and being easy to implement.

[Brief explanation of the drawing]

Figures 1 and 2 show an embodiment of this invention,
FIG. 1 is a circuit diagram of the main part, FIG. 2 is a characteristic diagram showing the operating point of the FET, and FIG. 3 is a circuit diagram showing a conventional embodiment. Explanation of symbols of main parts, 1, 5, 7...Resistor, 2...Analog switch, 3...FET, 4
...semi-fixed resistor, 6... operational amplifier, 8... capacitor.

Claims (1)

[Scope of Claim for Utility Model Registration] In an offset voltage adjustment circuit for a phase inversion type sample and hold circuit comprising a sampling analog switch, an operational amplifier, and a FET buffer amplifier used to increase the input impedance of the operational amplifier, the FET buffer amplifier comprises: An offset voltage adjustment circuit for a sample-and-hold circuit, characterized in that a variable resistor is provided between the source of the FET and the inverting input terminal of the operational amplifier, or between the inverting input terminal of the operational amplifier and the negative power supply. .