JPH04223331A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH04223331A
JPH04223331A JP40655190A JP40655190A JPH04223331A JP H04223331 A JPH04223331 A JP H04223331A JP 40655190 A JP40655190 A JP 40655190A JP 40655190 A JP40655190 A JP 40655190A JP H04223331 A JPH04223331 A JP H04223331A
Authority
JP
Japan
Prior art keywords
hole
side electrode
electrode
etching
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40655190A
Other languages
Japanese (ja)
Inventor
Masaki Kobayashi
正樹 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP40655190A priority Critical patent/JPH04223331A/en
Publication of JPH04223331A publication Critical patent/JPH04223331A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To enable a through hole for electrically connecting the surface side electrode with the rear side electrode of a semiconductor substrate such as monolithic microwave IC, etc., to be easily made by etching step. CONSTITUTION:The through hole measuring patterns 3 are provided on the electrodes 1, 2 in the terminal side opening part 6 to make the through hole 5. Through these procedures, the timing of the through hole etching termination of a semiconductor substrate can be assured thereby enabling the defective timing due to the insufficient or excessive etching step to be avoided.

Description

【発明の詳細な説明】[Detailed description of the invention]

[発明の目的] [Purpose of the invention]

【0001】0001

【産業上の利用分野】本発明は化合物半導体を用いた半
導体装置に関し、特に化合物半導体基板の両面間を貫通
して設けられる貫通孔を再現性よく形成できる構造の半
導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a compound semiconductor, and more particularly to a semiconductor device having a structure in which through holes extending between both surfaces of a compound semiconductor substrate can be formed with good reproducibility.

【0002】0002

【従来の技術】従来、GaAsFET等を能動素子とす
るモノリシック型マイクロ波集積回路(以下MMICと
略称)では、接地用電極のパッケージ等の接地面への接
続方法の一つにワイヤボンディングによる接地を行うも
のがある。しかし、この方法には、ボンディングワイヤ
のインダクタンス成分がRF特性を低下させるという欠
点がある。
[Prior Art] Conventionally, in monolithic microwave integrated circuits (hereinafter abbreviated as MMIC) using GaAsFETs and the like as active elements, one of the methods for connecting a grounding electrode to the ground plane of a package, etc. is to use wire bonding for grounding. There is something to do. However, this method has the drawback that the inductance component of the bonding wire degrades the RF characteristics.

【0003】そこで、インダクタンス成分を低減させる
目的で図10に示す構造が用いられる。これは、GaA
s基板4の表面側に形成された表面側電極1に面し、か
つ、この基板4の表裏両面間を貫通する貫通孔5を形成
し、この貫通孔5及びGaAs基板4裏面のメタライズ
によって前記表面側電極1とGaAs基板裏面の裏面側
電極10を電気的に導通させた構造となっている。この
構造によると、パッケージ等の接地面へのマウントの際
に直接接地することができ、インダクタンス成分を低減
させることができる。上記貫通孔を形成する工程を各工
程毎の断面図で示す。
[0003] Therefore, the structure shown in FIG. 10 is used for the purpose of reducing the inductance component. This is GaA
A through hole 5 is formed which faces the front side electrode 1 formed on the front side of the S substrate 4 and penetrates between the front and back surfaces of this substrate 4, and by metallizing the through hole 5 and the back side of the GaAs substrate 4. The structure is such that the front side electrode 1 and the back side electrode 10 on the back side of the GaAs substrate are electrically connected to each other. According to this structure, it is possible to directly ground the package or the like when mounting it on the ground plane, and it is possible to reduce the inductance component. The steps of forming the above-mentioned through holes are shown in cross-sectional views for each step.

【0004】まず、図11に示すように、GaAs基板
の表面側に蒸着等により表面側電極1を形成する。次に
図12に示すようにGaAs基板4を裏面側からラッピ
ングにより薄くし、所定の厚さのGaAs基板4とした
後、裏面よりGaAs基板4に選択的なドライエッチン
グ又はウエットエッチングを施し、表面側電極1に達す
る基板貫通孔5を設ける。そして、裏面側から金属の蒸
着及びメッキを施して裏面側電極10を形成して図10
に示すように基板貫通孔5によって表面側電極1に裏面
側電極10を接続させた構造を完成する。
First, as shown in FIG. 11, a front side electrode 1 is formed on the front side of a GaAs substrate by vapor deposition or the like. Next, as shown in FIG. 12, the GaAs substrate 4 is thinned from the back side by lapping to obtain a GaAs substrate 4 of a predetermined thickness, and then selective dry etching or wet etching is performed on the GaAs substrate 4 from the back side, and the surface A substrate through hole 5 reaching the side electrode 1 is provided. Then, metal is vapor-deposited and plated from the back side to form the back side electrode 10, as shown in FIG.
As shown in FIG. 3, a structure is completed in which the front side electrode 1 and the back side electrode 10 are connected to the front side electrode 1 through the substrate through hole 5.

【0005】[0005]

【発明が解決しようとする課題】上記の工程におけるエ
ッチングの終点の確認には、次のような問題がある。上
記エッチング工程の終点の確認は貫通孔5を裏面側から
顕微鏡を用いて視認を行う。この視認によるエッチング
工程の終点の判定が難しく、エッチング不足であるにも
拘らずエッチング終了と誤認してチップ歩留を低下させ
たり、接地のインピーダンスが過大となって高周波特性
を低下させたりする場合があった。接地のインピーダン
スが過大となるのは貫通孔と表面側電極が接する部分の
開口径が大きくなり過ぎた場合である。エッチング過剰
により開孔部が表面側電極よりはみ出して外観歩留を低
下させたり、極端な場合にはバイアホール電極の周辺部
分をエッチングしてしまい、機械的強度が著しく劣化す
る場合があった。 [発明の構成]
Problems to be Solved by the Invention There are the following problems in confirming the end point of etching in the above process. The end point of the etching process is confirmed by visually checking the through hole 5 from the back side using a microscope. It is difficult to determine the end point of the etching process by visual inspection, and it may be mistaken as etching completion even though there is insufficient etching, resulting in a decrease in chip yield, or in cases where the grounding impedance becomes excessive and degrades high frequency characteristics. was there. The grounding impedance becomes excessive when the opening diameter of the portion where the through hole and the surface electrode contact becomes too large. Excessive etching may cause the opening to protrude beyond the surface electrode, reducing the appearance yield, or in extreme cases, the peripheral portion of the via hole electrode may be etched, resulting in a significant deterioration of mechanical strength. [Structure of the invention]

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
一方の主面から他方の面に達する貫通孔を有する半導体
基板と、この半導体基板の一方の主面に前記貫通孔にそ
の一部が面して層状に形成され、かつ前記貫通孔側から
縁部が視認できる表面側電極と、前記半導体基板の他方
の面に層状に形成された裏面側電極と、この裏面側電極
と前記表面側電極とを前記貫通孔を利用して導電接続す
る電極間接続手段とより成る半導体装置とする。変形例
として、前記貫通孔側から縁部が視認できる表面側電極
の代りに前記貫通孔側から視認できる凹凸を有する表面
側電極とした半導体装置とする。
[Means for Solving the Problems] A semiconductor device of the present invention includes:
A semiconductor substrate having a through hole reaching from one main surface to the other surface, a layer formed on one main surface of the semiconductor substrate with a part thereof facing the through hole, and an edge extending from the through hole side. a front-side electrode whose portion is visible; a back-side electrode formed in a layer on the other surface of the semiconductor substrate; and an electrode between which the back-side electrode and the front-side electrode are conductively connected using the through hole. A semiconductor device comprising a connecting means. As a modified example, a semiconductor device is provided in which a front-side electrode having an unevenness that is visible from the through-hole side is used instead of a front-side electrode whose edge is visible from the through-hole side.

【0007】[0007]

【作用】本発明は、貫通孔を形成する際の終端部にある
電極に貫通孔径測定用のパターンを設けることにより、
エッチング工程における確認の際、上記パターンを視認
してエッチング終了時点の判断ができる。
[Operation] The present invention provides a pattern for measuring the diameter of the through hole on the electrode at the terminal end when forming the through hole.
When checking in the etching process, it is possible to visually check the pattern and determine when the etching has finished.

【0008】[0008]

【実施例】以下、本発明の実施例について図1〜図9に
説明する。従来例と同じ構成部分には同一符号を付けて
ある。図1は本発明による半導体装置の断面図であり、
表面側電極1又は2の縁部で貫通孔径測定用パターン3
が形成されている。
Embodiments Examples of the present invention will be described below with reference to FIGS. 1 to 9. Components that are the same as those of the conventional example are given the same reference numerals. FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention,
Pattern 3 for measuring through hole diameter at the edge of surface side electrode 1 or 2
is formed.

【0009】図2は図1のA−A´断面図である。表面
側電極1は寸法測定パターン形成のため、一例として図
の密な斜線部の形状にAuGeを2000A,続けてP
tを300A,選択的に蒸着してある。表面側電極2は
1の欠如部と1の上面にTi/Pt/Auが蒸着されて
いる。表面側電極1と2の縁部が測定用パターン3を形
成し、図2の例では表面側電極1と2の境界の直線部分
の長さが10μmである。  図3は、図2のB−B´
線で図1を切断した断面図である。ただし、裏面側電極
10は除いてある。6は貫通孔の開口部である。
FIG. 2 is a sectional view taken along line AA' in FIG. For the surface side electrode 1, in order to form a dimension measurement pattern, as an example, AuGe was applied to the shape of the densely shaded area in the figure at 2000A, followed by P.
t was selectively deposited at 300A. The front side electrode 2 has Ti/Pt/Au deposited on the missing portion of 1 and the upper surface of 1. The edges of the front-side electrodes 1 and 2 form a measurement pattern 3, and in the example of FIG. 2, the length of the straight line portion at the boundary between the front-side electrodes 1 and 2 is 10 μm. FIG. 3 shows the line BB' in FIG.
FIG. 2 is a cross-sectional view of FIG. 1 taken along a line. However, the back side electrode 10 is excluded. 6 is the opening of the through hole.

【0010】図4は本発明の変形例である。GaAs基
板4に接して絶縁膜7のパターンがあり、その欠如部及
び7の上面に表面側電極1が形成されている。絶縁膜7
と表面側電極1の境界すなわち表面側電極の縁部が測定
用パターン3を形成する。
FIG. 4 shows a modification of the present invention. There is a pattern of an insulating film 7 in contact with the GaAs substrate 4, and a front side electrode 1 is formed on the cutout portion and the upper surface of the insulating film 7. Insulating film 7
The boundary between the surface-side electrode 1 and the surface-side electrode 1, that is, the edge of the surface-side electrode forms a measurement pattern 3.

【0011】次に、上記構造を作成する方法を図5〜図
8に各工程の断面図で示す。図5に示すように厚さ約4
00μmのGaAs基板4の上面にフォトレジスト膜8
を塗布し、このフォレジスト膜に貫通孔径測定用パター
ン形状のパターニングを施す。次いでAuGe/Ptを
それぞれ2000A/300A蒸着し、リフトオフによ
り測定用パターンの形状をした表面側電極1を形成する
Next, a method for creating the above structure is shown in cross-sectional views of each step in FIGS. 5 to 8. Thickness about 4 as shown in Figure 5
A photoresist film 8 is formed on the upper surface of the GaAs substrate 4 with a thickness of 00 μm.
is applied, and this foresist film is patterned in the shape of a pattern for through-hole diameter measurement. Next, AuGe/Pt is vapor-deposited at 2000 A/300 A, respectively, and a front-side electrode 1 in the shape of a measurement pattern is formed by lift-off.

【0012】次に、この上にTi/Pt/Auをそれぞ
れ1000A/500A/8000A蒸着する(図6)
。次にGaAs基板4を裏面側からラッピングし、約1
50μm厚にする。次いで図7に示すように裏面側の貫
通孔形成予定域に開孔を有するフォトレジストパターン
9を設ける。次に図8に示すようにリアクティブ・イオ
ン・エッチング(以下、RIEと略記する)を施して貫
通孔5を形成し、上記フォトレジストパターン9を除去
する。この状態を基板の裏面側から見た図を図9に示す
[0012] Next, Ti/Pt/Au are vapor-deposited on top of this at 1000A/500A/8000A (FIG. 6).
. Next, the GaAs substrate 4 is lapped from the back side, and approximately 1
Make it 50 μm thick. Next, as shown in FIG. 7, a photoresist pattern 9 having openings is provided in the area where the through holes are to be formed on the back side. Next, as shown in FIG. 8, reactive ion etching (hereinafter abbreviated as RIE) is performed to form a through hole 5, and the photoresist pattern 9 is removed. FIG. 9 shows this state as viewed from the back side of the substrate.

【0013】上記の構造における貫通孔形成過程で、エ
ッチングが表面側電極1,2に達していないときは、貫
通孔径測定用パターン3が認められない。エッチングが
表面側電極に到達すると貫通孔径測定用パターン3を視
認でき、このパターンにより表面電極側貫通孔径が所定
値と比較して小さいか、適正か、大きいかを判断するこ
とができる。この貫通孔径測定用パターン3により、工
程途中の貫通孔径を知り、適切な時点でエッチングを打
切り、適正な孔径の貫通孔を得ることができる。次に、
裏面側電極10を形成すれば上記表面側電極1,2と電
気的接続が得られ、図1に示す状態になる。
In the process of forming the through holes in the above structure, if the etching does not reach the front side electrodes 1 and 2, the through hole diameter measurement pattern 3 will not be recognized. When the etching reaches the surface-side electrode, the through-hole diameter measurement pattern 3 can be visually recognized, and it can be determined from this pattern whether the surface-electrode side through-hole diameter is small, appropriate, or large compared to a predetermined value. By using this through-hole diameter measurement pattern 3, it is possible to know the through-hole diameter during the process, stop etching at an appropriate point, and obtain through-holes with an appropriate diameter. next,
Once the back side electrode 10 is formed, electrical connection with the front side electrodes 1 and 2 can be obtained, resulting in the state shown in FIG. 1.

【0014】この実施例の工程により、貫通孔形成時に
おけるエッチング不足による表面側電極1と裏面側電極
10との間の導通不良やインピーダンス過大、エッチン
グ過剰による表面側電極1周辺の外観不良等が防止され
、半導体装置の製造歩留が向上する。  上記実施例で
は電極材料の違いにより、貫通孔径測定用電極の縁部を
形成した。  別の実施例として、GaAs基板4の表
面側に貫通孔径測定用パターン形状の凹部を形成する。 この凹部の形成には通常用いられるフォトレジストとウ
ェットエッチング又はドライエッチング等の手法を用い
る。この凹部パターンが形成されたGaAs基板4の表
面側にAuGe/Pt,Ti/Pt/Auを蒸着する。 この結果、GaAs基板4に接した表面側電極AuGe
/Ptは貫通孔径測定用パターンの凹凸形状となる。従
って、第一の実施例と同様にこのGaAs基板4を裏面
側からエッチングして貫通孔を形成すれば貫通孔が表面
電極に到達するとこの表面電極の凹凸パターンを視認す
ることができる。この凹凸パターンにより貫通孔形成エ
ッチングの終点を容易に判断することができる。
The process of this embodiment prevents poor conductivity between the front side electrode 1 and back side electrode 10 due to insufficient etching when forming the through hole, excessive impedance, and poor appearance around the front side electrode 1 due to excessive etching. This can be prevented and the manufacturing yield of semiconductor devices can be improved. In the above embodiments, the edges of the through-hole diameter measuring electrodes were formed using different electrode materials. As another example, a concave portion in the shape of a pattern for measuring the diameter of a through hole is formed on the surface side of the GaAs substrate 4. To form this recessed portion, a commonly used photoresist and a technique such as wet etching or dry etching are used. AuGe/Pt and Ti/Pt/Au are deposited on the surface side of the GaAs substrate 4 on which the concave pattern is formed. As a result, the surface side electrode AuGe in contact with the GaAs substrate 4
/Pt becomes the uneven shape of the pattern for measuring the diameter of the through hole. Therefore, if the GaAs substrate 4 is etched from the back side to form a through hole as in the first embodiment, the uneven pattern of the surface electrode can be visually recognized when the through hole reaches the surface electrode. The end point of the through-hole forming etching can be easily determined based on this uneven pattern.

【0015】なお、図2,図3,図4に示した貫通孔径
測定用電極の縁部パターン3は一例であり、これに限ら
れるものではない。孔径を測定でき、表面電極と裏面電
極とを電気的に接続できるパターンならば、他の形状で
もよいことは勿論である。
The edge pattern 3 of the through-hole diameter measuring electrode shown in FIGS. 2, 3, and 4 is merely an example, and the pattern is not limited to this. Of course, other shapes may be used as long as the pattern allows the pore diameter to be measured and allows electrical connection between the front and back electrodes.

【0016】[0016]

【発明の効果】以上述べたように本発明によれば半導体
基板の貫通孔エッチング終了時の判断が確実になり、エ
ッチング不足やエッチング過剰による不良の発生を防ぎ
、MMIC等を歩留よく製作することができる。
[Effects of the Invention] As described above, according to the present invention, it is possible to reliably determine when through-hole etching of a semiconductor substrate is completed, prevent defects due to insufficient etching or excessive etching, and manufacture MMICs and the like with high yield. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の半導体装置を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

【図2】[Figure 2]

【図1】のA−A´切断図である。FIG. 1 is a cutaway view taken along the line AA′ of FIG.

【図3】[Figure 3]

【図2】のB−B´切断図である。It is a BB' cutaway view of FIG. 2.

【図4】[Figure 4]

【図3】の一変形例である。FIG. 3 is a modified example.

【図5】本発明の半導体装置の製造工程を説明する断面
図である。
FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the present invention.

【図6】本発明の半導体装置の製造工程を説明する断面
図である。
FIG. 6 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the present invention.

【図7】本発明の半導体装置の製造工程を説明する断面
図である。
FIG. 7 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the present invention.

【図8】本発明の半導体装置の製造工程を説明する断面
図である。
FIG. 8 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the present invention.

【図9】本発明の半導体装置の製造工程を説明する平面
図である。
FIG. 9 is a plan view illustrating the manufacturing process of the semiconductor device of the present invention.

【図10】従来例の半導体装置を説明する断面図である
FIG. 10 is a cross-sectional view illustrating a conventional semiconductor device.

【図11】従来例の半導体装置の製造工程を説明する断
面図である。
FIG. 11 is a cross-sectional view illustrating the manufacturing process of a conventional semiconductor device.

【図12】従来例の半導体装置の製造工程を説明する断
面図である。
FIG. 12 is a cross-sectional view illustrating the manufacturing process of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1,2  ……  表面側電極 3  ……  測定用パターン 4  …………  GaAs基板 5  ……  貫通孔 6  …………  開口部 7  ……  絶縁膜 8  …………  フォトレジスト 9  ……  フォトレジストパターン10  ………
…  裏面側電極
1, 2... Surface side electrode 3... Measurement pattern 4...... GaAs substrate 5...... Through hole 6...... Opening 7... Insulating film 8...... Photoresist 9...... Photoresist Pattern 10……
… Back side electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  一方の主面から他方の面に達する貫通
孔を有する半導体基板と、この半導体基板の一方の主面
に前記貫通孔にその一部が面して層状に形成され、かつ
前記貫通孔側から、縁部が視認できる表面側電極と、前
記半導体基板の他方の面に層状に形成された裏面側電極
と、この裏面側電極と前記表面側電極とを前記貫通孔を
利用して導電接続する電極間接続手段とより成る半導体
装置。
1. A semiconductor substrate having a through hole reaching from one main surface to the other surface, a layer formed on one main surface of the semiconductor substrate with a part thereof facing the through hole, and A front side electrode whose edge is visible from the through hole side, a back side electrode formed in a layered manner on the other side of the semiconductor substrate, and this back side electrode and the front side electrode are connected using the through hole. A semiconductor device comprising inter-electrode connection means for conducting conductive connection.
【請求項2】  一方の主面から他方の面に達する貫通
孔を有する半導体基板と、この半導体基板の一方の主面
に前記貫通孔にその一部が面して層状に形成され、かつ
前記貫通孔側から、視認できる凹凸を有する表面側電極
と、前記半導体基板の他方の面に層状に形成された裏面
側電極と、この裏面側電極と前記表面側電極とを前記貫
通孔を利用して導電接続する電極間接続手段とより成る
半導体装置。
2. A semiconductor substrate having a through hole reaching from one main surface to the other surface, a layer formed on one main surface of the semiconductor substrate with a part thereof facing the through hole, and From the through-hole side, a front-side electrode having visible irregularities, a back-side electrode formed in a layered manner on the other surface of the semiconductor substrate, and the back-side electrode and the front-side electrode are connected using the through-hole. A semiconductor device comprising inter-electrode connection means for conducting conductive connection.
JP40655190A 1990-12-26 1990-12-26 Semiconductor device Pending JPH04223331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40655190A JPH04223331A (en) 1990-12-26 1990-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40655190A JPH04223331A (en) 1990-12-26 1990-12-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04223331A true JPH04223331A (en) 1992-08-13

Family

ID=18516174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40655190A Pending JPH04223331A (en) 1990-12-26 1990-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04223331A (en)

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