JP2707483B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2707483B2 JP2707483B2 JP5120603A JP12060393A JP2707483B2 JP 2707483 B2 JP2707483 B2 JP 2707483B2 JP 5120603 A JP5120603 A JP 5120603A JP 12060393 A JP12060393 A JP 12060393A JP 2707483 B2 JP2707483 B2 JP 2707483B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- junction
- film
- semiconductor substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、可変容量ダイオード等
の半導体基板表面に平行なＰＮ接合面を有する半導体装
置の、ボンディングパッドとなる導体膜の構造およびそ
の製造方法に関するものである。とくに、半導体基板表
面に平行に浅いＰＮ接合面が形成される高周波用の可変
容量ダイオード装置等に適したものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a conductor film serving as a bonding pad in a semiconductor device having a PN junction parallel to the surface of a semiconductor substrate such as a variable capacitance diode, and a method of manufacturing the same. In particular, it is suitable for a high-frequency variable capacitance diode device or the like in which a shallow PN junction surface is formed parallel to the semiconductor substrate surface.
【０００２】[0002]
【従来の技術】従来、可変容量ダイオード装置等の半導
体装置と外部回路の接続はワイヤボンディングによって
行われる。半導体素子表面の導体膜と素子を搭載する基
板あるいはリードフレームとの間でワイヤボンディング
が行われる。2. Description of the Related Art Conventionally, a semiconductor device such as a variable capacitance diode device is connected to an external circuit by wire bonding. Wire bonding is performed between a conductor film on the surface of a semiconductor element and a substrate or a lead frame on which the element is mounted.
【０００３】可変容量ダイオードでのワイヤボンディン
グは、図４に示したように、ＰＮ接合が形成された半導
体基板40の表面に形成されたアルミニウムの導体膜42に
直接行っていた。また、この部分は製造途中のウエハー
から切断、分離される前の可変容量ダイオードが、特性
の検査のために自動機械による検査針（プローブ）を接
触される部分でもある。ところが、可変容量ダイオード
の大容量化と、１００ＭＨｚ以上の高周波における使用
を目的としてＰＮ接合面の深さを浅くすると、図４に示
したように導体膜12の同じ部分にワイヤボンディングし
たり、検査針を接触させることによってＰＮ接合面を破
壊することが多く、これによって耐圧が低下し、リーク
電流が増加するといった問題が生じる。特に、検査針は
通常先端が鋭く尖ったタングステンの針であり、接触面
に強い衝撃力が加わるので破壊の原因を発生しやすく、
その後のワイヤボンディングによる破壊を助長すると考
えられる。As shown in FIG. 4, wire bonding with a variable capacitance diode is directly performed on an aluminum conductor film 42 formed on a surface of a semiconductor substrate 40 on which a PN junction is formed. This portion is also a portion where the variable capacitance diode before being cut and separated from the wafer being manufactured is brought into contact with an inspection needle (probe) by an automatic machine for inspection of characteristics. However, if the depth of the PN junction surface is reduced for the purpose of increasing the capacity of the variable capacitance diode and using it at a high frequency of 100 MHz or more, wire bonding or inspection for the same portion of the conductive film 12 as shown in FIG. The PN junction surface is often broken by contacting the needle, which causes a problem that the breakdown voltage is reduced and the leak current is increased. In particular, the inspection needle is usually a tungsten needle with a sharp pointed tip, and a strong impact force is applied to the contact surface, so it is easy to cause the cause of destruction,
It is considered that the destruction by subsequent wire bonding is promoted.
【０００４】そこで、図３に示したように、半導体基板
30のＰＮ接合が形成された部分の表面からその周囲の酸
化膜31上に跨がるアルミニウムの導体膜32を形成し、ボ
ンディングパッドや検査針専用の領域を設ける構造も考
えられる。しかし、そのための素子面積の増加に伴う収
量低下によるコストアップ、アルミニウムの電極幅に制
約される抵抗の増加の問題が生じる。また、導体膜32と
酸化膜31下面の半導体領域とは同電位でなく、それらの
間に浮遊容量が発生する問題も生じる。Therefore, as shown in FIG.
A structure is also conceivable in which an aluminum conductor film 32 is formed so as to extend from the surface of the portion where the 30 PN junction is formed on the oxide film 31 around the PN junction, and a region dedicated to the bonding pad and the inspection needle is provided. However, there arises a problem that the cost is increased due to a decrease in yield due to an increase in the element area, and a resistance is increased due to the limitation of the electrode width of aluminum. Further, the conductor film 32 and the semiconductor region on the lower surface of the oxide film 31 are not at the same potential, and there is a problem that a stray capacitance occurs between them.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、ボンデイン
グパッドとは別に検査針の接触可能な領域をＰＮ接合が
形成された部分に設けることにより、ＰＮ接合を破壊す
ることなく検査針の接触とワイヤボンディングが可能な
半導体装置およびその製造方法を提供するものである。SUMMARY OF THE INVENTION According to the present invention, a contact area of a test needle is provided separately from a bonding pad in a portion where a PN junction is formed, so that the contact of the test needle with the PN junction is not broken. An object of the present invention is to provide a semiconductor device capable of performing wire bonding and a method of manufacturing the same.
【０００６】検査針の接触可能な領域は、ＰＮ接合の周
囲に存在する必要はないから小型化が可能であり、導体
抵抗も小さく、また、導体膜と半導体領域との間に浮遊
容量が発生することのない半導体装置およびその製造方
法を提供するものである。The contact area of the test needle does not need to exist around the PN junction, so that it can be miniaturized, the conductor resistance is small, and a stray capacitance is generated between the conductor film and the semiconductor region. And a method of manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】本発明は、ＰＮ接合面が
形成された半導体基板の表面の一部に酸化膜等の絶縁膜
を介して導体膜を形成し、この導体膜を検査針の接触可
能な領域とし、絶縁膜のない半導体基板の表面に形成し
た導体膜をボンディングパッドとすることによって、上
記の課題を解決するものである。According to the present invention, a conductor film is formed on a part of the surface of a semiconductor substrate on which a PN junction surface is formed via an insulating film such as an oxide film, and the conductor film is formed on an inspection needle. The above object is achieved by using a conductive film formed on a surface of a semiconductor substrate without an insulating film as a bonding pad as a contactable region.
【０００８】すなわち、半導体基板の表面に平行なＰＮ
接合面が形成された半導体装置において、該ＰＮ接合面
が形成された部分の半導体基板表面の一部に絶縁膜を具
え、その絶縁膜上と該ＰＮ接合面の表面側の層の絶縁膜
を設けてない表面に跨がる導体膜を具え、該ＰＮ接合面
の表面側の層の絶縁膜を設けてない表面の導体膜をボン
ディングパッドとしたことに特徴を有するものである。That is, PN parallel to the surface of the semiconductor substrate
In a semiconductor device having a junction surface formed thereon, an insulating film is provided on a part of the surface of the semiconductor substrate where the PN junction surface is formed, and the insulating film on the insulating film and a layer on the surface side of the PN junction surface are formed. The present invention is characterized in that a conductive film is provided over a surface on which the insulating film is not provided, and a conductive film on the surface on the surface side of the PN junction surface where the insulating film is not provided is used as a bonding pad.
【０００９】また、半導体基板の表面に平行なＰＮ接合
面が形成された半導体装置の製造方法において、該ＰＮ
接合面が形成された部分の半導体基板表面の一部に絶縁
膜を形成し、その絶縁膜表面と該ＰＮ接合面の表面側の
層の絶縁膜を設けてない表面に跨がる導体膜を形成し、
該ＰＮ接合面の表面側の層の絶縁膜のない表面の導体膜
にワイヤボンディングすることに特徴を有するものであ
る。In a method of manufacturing a semiconductor device in which a PN junction plane parallel to a surface of a semiconductor substrate is formed,
An insulating film is formed on a part of the surface of the semiconductor substrate where the bonding surface is formed, and a conductive film extending over the surface of the insulating film and the surface on the surface side of the PN bonding surface where the insulating film is not provided is formed. Forming
The present invention is characterized in that wire bonding is performed on a conductor film on the surface without the insulating film of the layer on the surface side of the PN junction surface.
【００１０】[0010]
【作用】SiO 2 等の酸化膜によって絶縁層を形成し、これ
を介して導体膜を設けその部分に検査針を当てることに
よって浅いＰＮ接合が検査針の接触時の衝撃力から保護
される。また、半導体基板表面と導体膜は同電位とな
り、浮遊容量の発生を防止することができる。The insulating layer is formed by an oxide film such as SiO 2, a conductive film is provided through the insulating layer, and the inspection needle is applied to the insulating film, whereby the shallow PN junction is protected from the impact force at the time of the contact of the inspection needle. In addition, the surface of the semiconductor substrate and the conductive film have the same potential, so that generation of stray capacitance can be prevented.
【００１１】[0011]
【実施例】以下、図面を参照して、本発明の実施例につ
いて説明する。図１は、本発明の実施例を示す、（ａ）
は平面図、（ｂ）は正面断面図である。半導体基板10内
に可変容量ダイオードを形成する例を示したもので、基
板表面側のＰ型領域とその下側のＮ+ 領域とによって浅
いＰＮ接合が形成されている。このＰＮ接合が形成され
る部分の周囲の領域は表面がSiO 2 の絶縁膜11で覆われる
が、この絶縁膜11をＰＮ接合の形成された部分の表面、
すなわちＰ型領域の表面の一部にも形成する。この場合
は、周囲の絶縁膜とは分離されて島状に形成されたSiO 2
の絶縁膜11がＰ型領域表面にも形成されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.
Is a plan view, and (b) is a front sectional view. This shows an example in which a variable capacitance diode is formed in the semiconductor substrate 10, and a shallow PN junction is formed by a P-type region on the substrate surface side and an N + region below the P-type region. The surface around the part where the PN junction is formed is covered with an insulating film 11 of SiO 2 .
That is, it is also formed on a part of the surface of the P-type region. In this case, SiO 2 formed in an island shape separated from the surrounding insulating film
Is also formed on the surface of the P-type region.
【００１２】ＰＮ接合のＰ型領域となっている半導体基
板表面と絶縁膜11の表面に跨がる導体膜12がアルミニウ
ムの蒸着、エッチング等によって形成される。この導体
膜12は絶縁膜11上の部分と半導体基板10の表面の部分と
が導通されるのに充分な厚さに形成する。そして、半導
体基板10の表面の導体膜12に金線13等がワイヤボンディ
ングされて接続が行われる。島状の絶縁膜11の上の導体
膜12は、検査針が接触される領域である。A conductive film 12 extending over the surface of the semiconductor substrate serving as a P-type region of the PN junction and the surface of the insulating film 11 is formed by vapor deposition, etching, or the like of aluminum. The conductive film 12 is formed to have a sufficient thickness to allow conduction between the portion on the insulating film 11 and the portion on the surface of the semiconductor substrate 10. Then, the gold wire 13 and the like are wire-bonded to the conductor film 12 on the surface of the semiconductor substrate 10 to perform connection. The conductor film 12 on the island-shaped insulating film 11 is a region where the inspection needle contacts.
【００１３】検査針が接触される領域は、導体膜12の下
に絶縁膜11が形成されている。これによって、検査針の
接触時の衝撃等からＰＮ接合は保護され、ワイヤボンデ
イングによるＰＮ接合の破損の発生をほとんど防止する
ことができる。そして、素子の歩留り、信頼性が著しく
向上する。しかも、ボンディングパッドとこの下の半導
体領域とは同じ電位となるので、浮遊容量を発生するこ
ともなくなる。An insulating film 11 is formed below a conductor film 12 in a region where the test needle contacts. As a result, the PN junction is protected from an impact at the time of contact with the inspection needle, and the occurrence of breakage of the PN junction due to wire bonding can be substantially prevented. Then, the yield and reliability of the device are significantly improved. In addition, since the bonding pad and the semiconductor region thereunder have the same potential, no floating capacitance is generated.
【００１４】図２は、本発明の他の実施例を示す、
（ａ）は平面図、（ｂ）は正面断面図である。半導体基
板20内に可変容量ダイオードを形成する例を示したもの
で、基板表面側のＰ型領域とその下側のＮ+ 領域とによ
って浅いＰＮ接合が形成されている。このＰＮ接合が形
成される部分の周囲の領域はSiO 2 の絶縁膜21で覆われる
が、この絶縁膜21をＰＮ接合の形成された部分の表面、
すなわちＰ型領域の表面まで伸ばして形成した例を示し
ている。FIG. 2 shows another embodiment of the present invention.
(A) is a plan view, (b) is a front sectional view. This shows an example in which a variable capacitance diode is formed in the semiconductor substrate 20. A shallow PN junction is formed by a P-type region on the substrate surface side and an N + region below the P-type region. A region around the portion where the PN junction is formed is covered with an insulating film 21 of SiO 2 .
That is, an example is shown in which it is formed to extend to the surface of the P-type region.
【００１５】本発明による半導体装置の製造にあたって
は、拡散等の半導体基板の処理後に半導体基板表面に形
成したSiO 2 等の酸化膜の窓開けの際のマスクを変えるの
みでよい。ＰＮ接合上面に形成する絶縁膜を残すように
酸化膜のエッチングを行い、導体膜を所定のパターンで
形成するのみでよい。In the manufacture of the semiconductor device according to the present invention, it is only necessary to change the mask for opening the window of the oxide film such as SiO 2 formed on the surface of the semiconductor substrate after the processing of the semiconductor substrate such as diffusion. It is only necessary to etch the oxide film so as to leave the insulating film formed on the upper surface of the PN junction and form the conductor film in a predetermined pattern.
【００１６】[0016]
【発明の効果】本発明によれば、ＰＮ接合がきわめて浅
い部分に形成されている半導体装置でも、検査時の検査
針の接触とこれに続くワイヤボンディングによるＰＮ接
合の破壊を防止することが可能となり、素子の歩留り、
信頼性が大幅に向上する。また、素子の面積を増加させ
る必要もなく、コスト面でも有利となる。更に、浮遊容
量の発生を防止できるので、素子の特性を維持すること
も容易となる。According to the present invention, even in a semiconductor device in which a PN junction is formed at an extremely shallow portion, it is possible to prevent contact of an inspection needle during inspection and breakage of the PN junction due to subsequent wire bonding. And yield of the element,
The reliability is greatly improved. Also, there is no need to increase the area of the element, which is advantageous in terms of cost. Furthermore, since the occurrence of stray capacitance can be prevented, it becomes easy to maintain the characteristics of the element.
【図１】 本発明の実施例を示す（ａ）平面図、（ｂ）
正面断面図FIG. 1A is a plan view showing an embodiment of the present invention, and FIG.
Front sectional view
【図２】 本発明の他の実施例を示す（ａ）平面図、
（ｂ）正面断面図2A is a plan view showing another embodiment of the present invention, FIG.
(B) Front sectional view
【図３】 従来例を示す（ａ）平面図、（ｂ）正面断面
図3A is a plan view showing a conventional example, and FIG.
【図４】 他の従来例を示す（ａ）平面図、（ｂ）正面
断面図FIG. 4A is a plan view showing another conventional example, and FIG.
10、20：半導体基板 11、21：絶縁膜 12、22：導体膜 10, 20: Semiconductor substrate 11, 21: Insulating film 12, 22: Conductive film
Claims (2)
形成された半導体装置の製造方法において、該ＰＮ接合
面が形成された部分の半導体基板表面の一部に絶縁膜を
形成し、その絶縁膜表面と該ＰＮ接合面の表面側の層の
絶縁膜のない表面に跨がる導体膜を形成し、該ＰＮ接合
面の表面側の層の絶縁膜のない表面の導体膜にワイヤボ
ンディングし、前記絶縁膜表面に設けた導体膜に検査針
を当てて検査することを特徴とする半導体装置の製造方
法。In a method of manufacturing a semiconductor device in which a PN junction surface parallel to a surface of a semiconductor substrate is formed, an insulating film is formed on a part of the semiconductor substrate surface where the PN junction surface is formed.
Formed, the conductor of the insulating film surface and the free surface insulating film on the surface side of the layer of the PN junction surface formed extending over the conductive film, no insulating film on the surface side of the layer of the PN junction surface surface Wire boss on membrane
To the conductor film provided on the surface of the insulating film.
A method for manufacturing a semiconductor device, comprising:
形成された可変容量ダイオード装置の製造方法におい
て、該ＰＮ接合面が形成された部分の半導体基板表面の
一部に絶縁膜を形成し、その絶縁膜表面と該ＰＮ接合面
の表面側の層の絶縁膜のない表面に跨がる導体膜を形成
し、該ＰＮ接合面の表面側の層の絶縁膜のない表面の導
体膜にワイヤボンディングし、前記絶縁膜表面に設けた
導体膜に検査針を当てて検査することを特徴とする可変
容量ダイオード装置の製造方法。2. A method for manufacturing a variable capacitance diode device in which a PN junction surface parallel to a surface of a semiconductor substrate is formed, wherein a portion of the semiconductor substrate surface where the PN junction surface is formed is formed. An insulating film is formed , and a conductor film is formed over the surface of the insulating film and the surface of the layer on the surface side of the PN junction surface without the insulating film.
Then , wire bonding was performed on the conductive film on the surface without the insulating film of the layer on the surface side of the PN junction surface, and provided on the surface of the insulating film.
A method for manufacturing a variable capacitance diode device, wherein inspection is performed by applying an inspection needle to a conductive film .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5120603A JP2707483B2 (en) | 1993-04-23 | 1993-04-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5120603A JP2707483B2 (en) | 1993-04-23 | 1993-04-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06310560A JPH06310560A (en) | 1994-11-04 |
| JP2707483B2 true JP2707483B2 (en) | 1998-01-28 |
Family
ID=14790346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5120603A Expired - Fee Related JP2707483B2 (en) | 1993-04-23 | 1993-04-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2707483B2 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5517487B2 (en) * | 1972-08-30 | 1980-05-12 | ||
| JPS54128272A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Structure of bonding pad |
| JPS62165344A (en) * | 1986-01-17 | 1987-07-21 | Nec Corp | Semiconductor device |
| JPH01130534U (en) * | 1988-03-02 | 1989-09-05 | ||
| JPH0473939A (en) * | 1990-07-16 | 1992-03-09 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
| JPH04152576A (en) * | 1990-10-16 | 1992-05-26 | Toko Inc | Variable capacitance diode device |
-
1993
- 1993-04-23 JP JP5120603A patent/JP2707483B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06310560A (en) | 1994-11-04 |
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