JPH0422030B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix circuit for a semiconductor nonvolatile memory device.

Semiconductor nonvolatile memory devices having an insulated gate field effect transistor structure include the generally known MNOS type and MAOS type structures, both of which use writing (erasing) through the first layer insulating film. It has been common practice to set "1" and "0" logic levels by inducing direct tunneling, Fowler-Nordheim tunneling, and the like.

Therefore, it is necessary to apply a high write voltage of 20 V or more in order to obtain an appropriate "1" and "0" width due to tunnel efficiency and memory retention capacity, which are limited by tunnel width and barrier height. It had been. Therefore, when implementing the above-mentioned semiconductor non-volatile memory device on-chip inside a watch IC, since the peripheral IC is composed of a CMOS structure with a thin-film insulated gate structure, the conventional write (erase) voltage of 20V or higher is required. The non-volatile storage device used (hereinafter
E ² PROM) has the disadvantage that peripheral ICs can cause malfunction or destruction.

Furthermore, in order to avoid the effects of high voltage application on peripheral ICs, high-voltage designs (e.g. PN junction isolation,
This necessitates special measures for substrate separation, etc., resulting in disadvantages in terms of area, and has many disadvantages in increasing capacity.

Also, when writing (erasing) E ² PROM using the IC's internal high voltage source, the clock power supply voltage (for example -
Even in the means of generating a high voltage from 1.55V), there are also drawbacks such as the step-up circuit occupying a significantly large area due to problems such as step-up efficiency.

In addition, in ICs with built-in E ² PROM in electronic watches, etc., the watch board (base plate) is at the highest potential, so
For example, use an N-type substrate to obtain the write voltage from the internal power supply.
In the design provided for the E ² PROM, we have taken measures such as separating special substrates (for example, sapphire) to
It is necessary to select a means for generating a negative write voltage.

The present invention eliminates the above-mentioned drawbacks by incorporating an E ² PROM with a MONOS structure capable of low-voltage writing (erasing) on-chip in a watch IC, and further by forming a matrix using the memory cell of the present invention. , for peripheral low voltage watches using negative low voltage unipolar voltage
Not only does it enable write (erase) operations without adversely affecting the CMOS, but it also significantly improves capacity, and its effects are significant. This will be explained below with reference to the drawings.

FIG. 1a is a sectional view of the MONOS structure used in the present invention, and FIG. 1b shows a V+h (threshold voltage)-V _G (gate voltage) hysteresis curve. MONOS
The structure consists of a three-layer insulating film (oxide film 1, nitride film 2, top film 3) for the gate part.
Since the total thickness of the MNOS has been reduced to around 100 Å, it is essentially possible to
Structures with similar tunneling probabilities at low voltages (e.g.
10V), and by forming an oxide film 3 with a large barrier height on the electrode 4 side, the conventional
Compared to the MNOS structure E ² PROM, the memory retention ability is significantly improved, and it is found to be particularly effective when formed on the same substrate as an IC consisting of a thin-film low-voltage MOS transistor such as an electronic watch. .

FIG. 2a shows an example of a 9-bit configuration of a memory matrix circuit according to the present invention.

Address transistors 11 of the same channel, for example, N-channel configuration, provided in the same substrate
It consists of a memory cell of a non-volatile memory element 12 having a MONOS structure, and the drain terminal of the N-channel address transistor 11 is used as a data output terminal.
D ₁ , and the drain terminal D ₁ is connected through the load 13.
Connect to V _DD (ground) terminal.

Next, the source terminal 21 of the N-channel address transistor 11 and the N-channel
MONOSE ² PROM12 drain (also source)
Connect the 22 terminals.

The gate terminals of the address transistors 11 and MONOSE ² PROM ¹² in each row arranged in a matrix are short-circuited to form A ₁ to A ₃ terminals and M ₁ to _{M 3} terminals, respectively. The terminal P ^- is connected to B, and the source (or drain) terminals of each MONOSE ² PROM 12 in each column are connected to S ₁ to _{S 3} .

FIG. 2b shows the pulse waveform of each terminal in each mode. In the present invention, the board terminal B is
1.55VMONOSE ² PROM12 source terminal (S ₁ ~
S ₃ ) to −1.55V, address transistor gate terminals (A ₁ to A ₃ ) to a negative voltage (e.g. −9V),
By setting the gate terminals (M ₁ to M ₃ ) of the MONOSE ² PROM to a negative voltage (-9V), all bits of the N-channel MONOSE ² PROM can be set to the depletion state.

For example, when setting memory cells M ₁₁ , M ₁₂ , M ₁₃ to write (enhancement), erase, or write state, terminals A ₁ to A ₃ , substrate terminals B, M ₂ , and M ₃ are set to negative voltage, Terminal M ₁ to −1.55V, S ₁ to negative voltage, S ₂ to −
1.55V, put S ₃ at negative voltage.

Figure 3 shows the change in V+h (threshold voltage) when the gate voltage is -1.55V, the substrate voltage is -9V, the drain is open, and the source potential is changed from 0 to -9V in the depletion state of MONOSTr. shows.

As is clear from Figure 3, there is no change in V+h of MONOSTr when the source potential is erased at -1.55V,
It can be seen that the threshold of the _M12 memory cell described above also does not change at all. Also, other cells _M21 to _M23 , _M31
~ _M33 MONOSTr has a drain (or source) with an open gate at -V, a substrate B at -V, and a source (or drain) at -V or -1.55V, so there is no state change at all.

In this way, the memory matrix circuit of the present invention has a negative voltage (e.g. -9V) and a watch power supply voltage -
Not only is it possible to write (erase) and inhibit operations with a binary value of 1.55V, but it is also possible to erase bits (bytes).

Further, although the present invention deals with the case of N channel, the same applies to the case of P channel. Furthermore, when considering on-chip integration with CMOS for watches,
By using MONOSE ² PROM, the conventional 20V
The write (erase) voltage is significantly lower than when using the above write (erase) voltage, and can be performed at around 9 V, for example, so it is easy to integrate it with watch CMOS made of low voltage CMOS, and it is also possible to use low voltage Since writing and erasing is possible with two values, internal writing (erasing) is possible using an internal high voltage generation source, and it does not easily take up a large area from the watch power supply, making it possible to design booster circuits, etc. This is possible and is extremely effective for applications such as electronic watches.

[Brief explanation of drawings]

FIG. 1a is a cross-sectional view showing the structure of a MONOS transistor. Figure 1b shows the hysteresis curve of threshold voltage and gate voltage. FIG. 2a is a circuit diagram of a memory matrix of the present invention. FIG. 2b is a diagram of voltage waveforms at each terminal. Figure 3 is a graph showing the change in Vth of the erased MONOS transistor. 11... Address transistor, 12...
MONOS transistor.

Claims (1)

[Claims] 1 Same channel address transistor and
Memory consisting of MONOS type non-volatile memory elements
A memory matrix circuit characterized in that cells are arranged in a matrix. 2. In the memory cell, the drain terminal of the address transistor is grounded via a load, the drain terminal is used as a data output terminal, and the source terminal of the address transistor and the drain (or source) terminal of the nonvolatile memory element are shorted. The memory according to claim 1, wherein the memory is configured to provide a write (or erase) and inhibit voltage to the source (or drain), gate, and substrate terminal of the nonvolatile memory element. Memory-matrix circuit with cell structure. 3 Memory cells must be protected from write (erase) and inhibit operations.
2. The memory matrix circuit according to claim 1, wherein the memory matrix circuit is set from a negative voltage (-V) from a 1.5V watch power supply and an internal voltage generation source that boosts the watch power supply voltage.