JPH0422030B2 - - Google Patents
Info
- Publication number
- JPH0422030B2 JPH0422030B2 JP8637783A JP8637783A JPH0422030B2 JP H0422030 B2 JPH0422030 B2 JP H0422030B2 JP 8637783 A JP8637783 A JP 8637783A JP 8637783 A JP8637783 A JP 8637783A JP H0422030 B2 JPH0422030 B2 JP H0422030B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- voltage
- terminal
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 claims description 14
- 239000011159 matrix material Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 239000010408 film Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 241001191009 Gymnomyza Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HLXGRHNZZSMNRX-UHFFFAOYSA-M sodium;3-(n-ethyl-3,5-dimethylanilino)-2-hydroxypropane-1-sulfonate Chemical compound [Na+].[O-]S(=O)(=O)CC(O)CN(CC)C1=CC(C)=CC(C)=C1 HLXGRHNZZSMNRX-UHFFFAOYSA-M 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、半導体不揮発性記憶装置のマトリツ
クス回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix circuit for a semiconductor nonvolatile memory device.
絶縁ゲート形電界効果トランジスタ構造を有す
る半導体不揮発性記憶装置は、一般に知られてい
る様にMNOS型、MAOS型構造があるが、これ
らは共に書込(消去)手段として第1層絶縁膜を
通しての直接トンネルやFowler−Nordheimト
ンネル現象等を誘起することで、“1”、“0”論
理レベルを設定することが常であつた。 Semiconductor nonvolatile memory devices having an insulated gate field effect transistor structure include the generally known MNOS type and MAOS type structures, both of which use writing (erasing) through the first layer insulating film. It has been common practice to set "1" and "0" logic levels by inducing direct tunneling, Fowler-Nordheim tunneling, and the like.
そのため、トンネルきよりやバリヤー高さなど
で制約されるトンネル効率や記憶保持能力による
適正な“1”、“0”幅を得る事などを考えて、書
込み電圧は20V以上の高電圧印加が余儀なくされ
ていた。そのため、時計用IC内部に上述の半導
体不揮発性記憶装置をオンチツプ化する場合、周
辺ICが薄膜絶縁ゲート構造を有するCMOS構造
で構成されているため、従来の20V以上の書込
(消去)電圧を用いる不揮発性記憶装置(以後
E2PROMとする)に対しては、周辺ICが誤動作
や破壊の原因になりうるという欠点を有する。 Therefore, it is necessary to apply a high write voltage of 20 V or more in order to obtain an appropriate "1" and "0" width due to tunnel efficiency and memory retention capacity, which are limited by tunnel width and barrier height. It had been. Therefore, when implementing the above-mentioned semiconductor non-volatile memory device on-chip inside a watch IC, since the peripheral IC is composed of a CMOS structure with a thin-film insulated gate structure, the conventional write (erase) voltage of 20V or higher is required. The non-volatile storage device used (hereinafter
E 2 PROM) has the disadvantage that peripheral ICs can cause malfunction or destruction.
更にそのため高電圧印加の周辺ICへの影響を
避けるため、高耐圧設計(例えばPN接合分離、
基板分離etc)の特殊な工夫が余儀なくされるた
め、面積的に不都合を生じ、容量アツプに対して
は、非常に不利な点が多かつた。 Furthermore, in order to avoid the effects of high voltage application on peripheral ICs, high-voltage designs (e.g. PN junction isolation,
This necessitates special measures for substrate separation, etc., resulting in disadvantages in terms of area, and has many disadvantages in increasing capacity.
又IC内部高電圧発生源を用いて、E2PROMを
書込(消去)む場合、時計用電源電圧(例えば−
1.55V)から高電圧を発生する手段に於いても昇
圧効率等の問題から昇圧回路が著しい大面積を占
める等の欠点も有する。 Also, when writing (erasing) E 2 PROM using the IC's internal high voltage source, the clock power supply voltage (for example -
Even in the means of generating a high voltage from 1.55V), there are also drawbacks such as the step-up circuit occupying a significantly large area due to problems such as step-up efficiency.
又電子時計等にE2PROMを内蔵するICに於い
ては、時計基板(地板)が最高電位に有るため、
例えばN型基板を用いて内部電源から書込電圧を
E2PROMに提供する設計では、特殊な基板(例
えばサフアイヤ)分離等の工夫を行なつて、正、
負の書込電圧を発生する手段の選択が余儀なくさ
れる。 In addition, in ICs with built-in E 2 PROM in electronic watches, etc., the watch board (base plate) is at the highest potential, so
For example, use an N-type substrate to obtain the write voltage from the internal power supply.
In the design provided for the E 2 PROM, we have taken measures such as separating special substrates (for example, sapphire) to
It is necessary to select a means for generating a negative write voltage.
本発明はかかる上述の欠点を除去し、低電圧書
込(消去)可能なMONOS構造のE2PROMを時
計用IC内にオンチツプ化し、更に本発明のメモ
リ−セルを用いてマトリツクス化することで、負
の低電圧の単極性電圧を用いて周辺低耐圧時計用
CMOSに悪影響を与えず、書込(消去)動作を
可能にするばかりか、容量アツプにも著しく改善
するもので、その効果は著しく大きい。以下図面
に従つて説明する。 The present invention eliminates the above-mentioned drawbacks by incorporating an E 2 PROM with a MONOS structure capable of low-voltage writing (erasing) on-chip in a watch IC, and further by forming a matrix using the memory cell of the present invention. , for peripheral low voltage watches using negative low voltage unipolar voltage
Not only does it enable write (erase) operations without adversely affecting the CMOS, but it also significantly improves capacity, and its effects are significant. This will be explained below with reference to the drawings.
第1図aは本発明に用いるMONOS構造断面
図で、第1図bはV+h(しきい値電圧)−VG(ゲ
ート電圧)ヒステリシス曲線を示す。MONOS
構造は3層絶縁膜(酸化膜1、窒化膜2、トツプ
膜3)でゲート部分が構成され、ゲート絶縁膜1
の総厚も100Å前後迄薄膜化されるために、実質
的には、従来の20V以上の書込み電圧のMNOS
構造と同様のトンネル確率を低電圧(例えば
10V)で得られること、更には電極4側にバリア
高さの大きい酸化膜3を形成することで、従来の
MNOS構造E2PROMに比較し、記憶保持能力も
著しく改善できるなど、特に電子時計等の薄膜低
耐圧MOSトランジスタからなるICと同一基板上
に形成する場合に於いては著しく有効であること
がわかる。 FIG. 1a is a sectional view of the MONOS structure used in the present invention, and FIG. 1b shows a V+h (threshold voltage)-V G (gate voltage) hysteresis curve. MONOS
The structure consists of a three-layer insulating film (oxide film 1, nitride film 2, top film 3) for the gate part.
Since the total thickness of the MNOS has been reduced to around 100 Å, it is essentially possible to
Structures with similar tunneling probabilities at low voltages (e.g.
10V), and by forming an oxide film 3 with a large barrier height on the electrode 4 side, the conventional
Compared to the MNOS structure E 2 PROM, the memory retention ability is significantly improved, and it is found to be particularly effective when formed on the same substrate as an IC consisting of a thin-film low-voltage MOS transistor such as an electronic watch. .
第2図aは本発明のメモリ−マトリツクス回路
の実施例で9ビツト構成の例を示す。 FIG. 2a shows an example of a 9-bit configuration of a memory matrix circuit according to the present invention.
同一基板内に設けた同一チヤネル例えばNチヤ
ネル構成のアドレストランジスタ11と
MONOS構造を有する不揮発性記憶素子12の
メモリ−セルからなり、該Nチヤネルアドレスト
ランジスタ11のドレイン端子をデータ出力端子
D1とし、該ドレイン端子D1を負荷13を介して
VDD(接地)端子に接続する。 Address transistors 11 of the same channel, for example, N-channel configuration, provided in the same substrate
It consists of a memory cell of a non-volatile memory element 12 having a MONOS structure, and the drain terminal of the N-channel address transistor 11 is used as a data output terminal.
D 1 , and the drain terminal D 1 is connected through the load 13.
Connect to V DD (ground) terminal.
次に該Nチヤネルアドレストランジスタ11の
ソース端子21と該Nチヤネル
MONOSE2PROM12のドレイン(又ソース)
22端子を接続する。 Next, the source terminal 21 of the N-channel address transistor 11 and the N-channel
MONOSE 2 PROM12 drain (also source)
Connect the 22 terminals.
マトリツクス状に配列した各行のアドレストラ
ンジスタ及MONOSE2PROM各該アドレストラ
ンジスタ11及MONOSE2PROM12のゲート
端子短絡し、それぞれA1〜A3端子、M1〜M3端
子とし、各セルに共通な基板端子P-をB、各列
の各該MONOSE2PROM12のソース(又はド
レイン)端子を接続し、S1〜S3とする。 The gate terminals of the address transistors 11 and MONOSE 2 PROM 12 in each row arranged in a matrix are short-circuited to form A 1 to A 3 terminals and M 1 to M 3 terminals, respectively. The terminal P - is connected to B, and the source (or drain) terminals of each MONOSE 2 PROM 12 in each column are connected to S 1 to S 3 .
第2図bは各モードに於ける各端子のパルス波
形を示す。本発明は、基板端子Bを−
1.55VMONOSE2PROM12のソース端子(S1〜
S3)を−1.55V、アドレストランジスタのゲート
端子(A1〜A3)を負電圧(例えば−9V)、
MONOSE2PROMのゲート端子(M1〜M3)を
負電圧(−9V)におくことで、全ビツトのNチ
ヤネルMONOSE2PROMはDepletion状態に設定
できる。 FIG. 2b shows the pulse waveform of each terminal in each mode. In the present invention, the board terminal B is
1.55VMONOSE 2 PROM12 source terminal (S 1 ~
S 3 ) to −1.55V, address transistor gate terminals (A 1 to A 3 ) to a negative voltage (e.g. −9V),
By setting the gate terminals (M 1 to M 3 ) of the MONOSE 2 PROM to a negative voltage (-9V), all bits of the N-channel MONOSE 2 PROM can be set to the depletion state.
例えばメモリ−セルM11、M12、M13を、書込
(Enhancement)、消去、書込状態に設定する場
合、端子A1〜A3、基板端子B、M2,M3を負電
圧、端子M1を−1.55V、S1を負電圧、S2を−
1.55V、S3を負電圧に置く。 For example, when setting memory cells M 11 , M 12 , M 13 to write (enhancement), erase, or write state, terminals A 1 to A 3 , substrate terminals B, M 2 , and M 3 are set to negative voltage, Terminal M 1 to −1.55V, S 1 to negative voltage, S 2 to −
1.55V, put S 3 at negative voltage.
第3図は、Depletion状態のMONOSTrをゲー
ト電圧を−1.55V、基板電圧を−9V、ドレインを
オープン状態にし、ソース電位を0〜−9Vに変
えた場合のV+h(しきい値電圧)の変化を示す。 Figure 3 shows the change in V+h (threshold voltage) when the gate voltage is -1.55V, the substrate voltage is -9V, the drain is open, and the source potential is changed from 0 to -9V in the depletion state of MONOSTr. shows.
第3図で明らかの様にソース電位を−1.55Vで
消去されたMONOSTrのV+h変化は全くなく、
上述のM12メモリ−セルのしきい値も全く変化し
ないことがわかる。又他のセルM21〜M23、M31
〜M33のMONOSTrはドレイン(又ソース)が
オープンゲートが−V、基板Bが−V、ソース
(又ドレイン)が−V又は−1.55Vで構成されて
いるため状態変化は全くない。 As is clear from Figure 3, there is no change in V+h of MONOSTr when the source potential is erased at -1.55V,
It can be seen that the threshold of the M12 memory cell described above also does not change at all. Also, other cells M21 to M23 , M31
~ M33 MONOSTr has a drain (or source) with an open gate at -V, a substrate B at -V, and a source (or drain) at -V or -1.55V, so there is no state change at all.
この様に本発明のメモリ−マトリツクス回路
は、負電圧(例えば−9V)と時計用電源電圧−
1.55Vの2値で書込(消去)、禁止動作が可能な
ばかりか、ビツト消去(バイト)も可能である。 In this way, the memory matrix circuit of the present invention has a negative voltage (e.g. -9V) and a watch power supply voltage -
Not only is it possible to write (erase) and inhibit operations with a binary value of 1.55V, but it is also possible to erase bits (bytes).
又本発明はNチヤネルの場合であるがPチヤネ
ルの場合も同様である。更に時計用CMOSとの
オンチツプ化を考えた場合に於いても
MONOSE2PROMを用いることで、従来の20V
以上の書込(消去)電圧を用いる場合に比較し著
しく低下し、例えば9V前後で行なえるため、低
耐圧CMOSから構成されている時計用CMOSと
のオンチツプ化も容易で、又負の低電圧の2値で
書込消去が可能のため内部高電圧発生源を用い
て、内部書込(消去)が可能なばかりか時計用電
源から容易に大面積を占めることがなく昇圧回路
等の設計が可能で電子時計等の応用には著しく効
果が大きい。 Further, although the present invention deals with the case of N channel, the same applies to the case of P channel. Furthermore, when considering on-chip integration with CMOS for watches,
By using MONOSE 2 PROM, the conventional 20V
The write (erase) voltage is significantly lower than when using the above write (erase) voltage, and can be performed at around 9 V, for example, so it is easy to integrate it with watch CMOS made of low voltage CMOS, and it is also possible to use low voltage Since writing and erasing is possible with two values, internal writing (erasing) is possible using an internal high voltage generation source, and it does not easily take up a large area from the watch power supply, making it possible to design booster circuits, etc. This is possible and is extremely effective for applications such as electronic watches.
第1図aはMONOSトランジスタの構造を示
す断面図。第1図bはスレシヨルド電圧とゲート
電圧のヒステリシス曲線。第2図aは本発明のメ
モリ−マトリツクスの回路図。第2図bは各端子
の電圧波型図。第3図は消去されたMONOSト
ランジスタのVthの変化を示すグラフ。
11……アドレストランジスタ、12……
MONOSトランジスタ。
FIG. 1a is a cross-sectional view showing the structure of a MONOS transistor. Figure 1b shows the hysteresis curve of threshold voltage and gate voltage. FIG. 2a is a circuit diagram of a memory matrix of the present invention. FIG. 2b is a diagram of voltage waveforms at each terminal. Figure 3 is a graph showing the change in Vth of the erased MONOS transistor. 11... Address transistor, 12...
MONOS transistor.
Claims (1)
MONOS型不揮発性記憶素子からなるメモリ−
セルをマトリツクス状に配列したことを特徴とす
るメモリ−マトリツクス回路。 2 メモリ−セルは、アドレストランジスタのド
レイン端子を負荷を介して接地し、該ドレイン端
子をデータ出力端子とし、該アドレストランジス
タのソース端子及び該不揮発性記憶素子のドレイ
ン(又はソース)端子を短絡し、該不揮発性記憶
素子のソース(又はドレイン)、ゲート、基板端
子に書込(又は消去)、禁止電圧を提供する様に
構成したことを特徴とする特許請求の範囲第1項
記載のメモリ−セル構造を有するメモリ−マトリ
ツクス回路。 3 メモリ−セルは書込(消去)、禁止動作を約
1.5Vの時計用電源及び該時計用電源電圧を昇圧
した内部電圧発生源による負電圧(−V)から設
定することを特徴とする特許請求の範囲第1項記
載のメモリ−マトリツクス回路。[Claims] 1 Same channel address transistor and
Memory consisting of MONOS type non-volatile memory elements
A memory matrix circuit characterized in that cells are arranged in a matrix. 2. In the memory cell, the drain terminal of the address transistor is grounded via a load, the drain terminal is used as a data output terminal, and the source terminal of the address transistor and the drain (or source) terminal of the nonvolatile memory element are shorted. The memory according to claim 1, wherein the memory is configured to provide a write (or erase) and inhibit voltage to the source (or drain), gate, and substrate terminal of the nonvolatile memory element. Memory-matrix circuit with cell structure. 3 Memory cells must be protected from write (erase) and inhibit operations.
2. The memory matrix circuit according to claim 1, wherein the memory matrix circuit is set from a negative voltage (-V) from a 1.5V watch power supply and an internal voltage generation source that boosts the watch power supply voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58086377A JPS59211281A (en) | 1983-05-17 | 1983-05-17 | Memory matrix circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58086377A JPS59211281A (en) | 1983-05-17 | 1983-05-17 | Memory matrix circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59211281A JPS59211281A (en) | 1984-11-30 |
JPH0422030B2 true JPH0422030B2 (en) | 1992-04-15 |
Family
ID=13885184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58086377A Granted JPS59211281A (en) | 1983-05-17 | 1983-05-17 | Memory matrix circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59211281A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2655765B2 (en) * | 1991-05-29 | 1997-09-24 | ローム株式会社 | Semiconductor device |
JP4726033B2 (en) | 2000-08-30 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Nonvolatile memory, control method of nonvolatile memory, and IC card |
-
1983
- 1983-05-17 JP JP58086377A patent/JPS59211281A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59211281A (en) | 1984-11-30 |
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