JP2635619B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an electrically rewritable programmable ROM (E
^{The present} invention relates to a nonvolatile semiconductor recording device having an internal booster circuit such as a 2PROM.

(Prior Art) An E ² PROM includes a booster circuit inside a chip, generates a high voltage Vpp for programming, and supplies this high voltage to a memory cell to perform writing / erasing. In general, as shown in the sectional view of FIG. 4, a memory cell has n-type source and drain layers 2 and 3 formed on a p-type silicon substrate 1 and a floating gate formed on the substrate 1 with a gate insulating film 4 interposed therebetween. 5 and a control gate 6 are laminated. A tunnel insulating film 7 of about 100 ° is formed on a portion between the floating gate 5 and the silicon substrate 1.
There is a rewrite area in which is formed. Rewriting of information is performed on the silicon substrate 1 via the tunnel insulating film 7 in the rewriting area.
This is done by transferring charges between the gate and the floating gate 5.

In such an E ² PROM, when programming, a high electric field is applied to the tunnel insulating film in the rewriting area. is there. To solve this problem, it is desirable to raise the programming voltage Vpp slowly to increase the voltage so that a high electric field is not applied to the tunnel insulating film. Therefore, it is conceivable to simply lower the current supply capability of the internal booster circuit to blunt the output waveform of the program voltage Vpp. However, in this method, when the temperature rises, the leakage current of the diffusion layer to which the boosted voltage is applied increases, and the current supply capability of the booster circuit is extremely reduced. Operating margin is reduced.

(Problems to be Solved by the Invention) As described above, in the conventional E ² PROM, a high electric field is applied to the tunnel insulating film, so that the tunnel insulating film deteriorates with time. If the current supply capability of the booster circuit that obtains the above voltage is reduced, there is a problem that the rewriting operation margin is reduced.

An object of the present invention is to solve the above problems and to provide a highly reliable nonvolatile semiconductor memory device.

[Configuration of the invention]

(Means for Solving the Problems) According to the present invention, in a nonvolatile semiconductor memory device having a booster circuit for generating a boosted potential and outputting the boosted potential to a memory cell, a potential connected to the booster circuit and boosted in a stepwise manner is generated. And a limiter circuit.

(Operation) In the configuration of the present invention, the booster potential for programming is boosted in a stepwise manner by the limiter circuit, so that the output waveform of the booster circuit can be smoothed and slowly risen. Therefore, since the injection and emission of electrons are performed at the same time as the voltage is increased in the floating gate, a high electric field is not applied to the thin tunnel insulating film.

(Example) An example of the present invention will be described.

FIG. 1 shows a schematic configuration diagram of the E ² PROM of this embodiment.
Is the high voltage Vpp for programming generated by the booster circuit 11.
To the nonvolatile memory cell array 13 via the decoder circuit 12.
To supply. This cell array 13 is composed of nonvolatile memory cells as shown in FIG. As shown in the figure, a limiter circuit 14 for boosting the programming potential in a stepwise manner is connected in parallel to the booster circuit 11 and the decoder circuit 12, and the limiter circuit 14 and the booster circuit 11 are connected in parallel.
Are not connected in series. The booster circuit 11, the decoder circuit 12, the memory array 13, the limiter circuit 14, and the timing control circuit 15 are integrated on one chip.

Next, the details of the limiter circuit 14 will be described. As shown in FIG. 2, the limiter circuit 14 includes a plurality of MOS transistors 21 to 30 having respective gates and drains connected in series, and the gates of some of the MOS transistors 24 to 30 are each connected to a switch. Are connected to the timing control circuit 15 through the MOS transistors 31 to 37 for use. Limiter circuit
The boost potential Vpp determined by 14 is equal to M
Since the sum of the threshold values of the OS transistors is obtained, the boosted potential Vpp is controlled by the number of serially conducting MOS transistors of the limiter circuit 14. In FIG. 2, for example,
N-channel enhancement type MO with threshold 2 [V]
Ten S transistors are connected in series to form a 10-stage configuration.

Next, the operation of the embodiment of the E ² PROM shown in FIG. ² will be described with reference to the output waveforms shown in FIG. The switching MOS transistor 31 is controlled by the timing control circuit 15.
When all of .about.37 are in the ON state, the outputs of the switching MOS transistors 31 to 37 become "H". In this case, the booster circuit 11
Limiter circuit conducted between the output potential and ground potential
There are only 14 serially connected MOS transistors in three stages 21, 22, and 23, and the threshold value of each MOS transistor is 2
[V], the boosted potential is 6 [V]. Next, the switching MOS transistor 31 is controlled by the timing control circuit 15.
Is turned off and the switching MOS transistors 32 to 37 are turned on, the output of the switching MOS transistor 31 becomes “L”, and the MOS transistor 24 connected to the switching MOS transistor 31 becomes conductive. Therefore, the serially connected MOS transistors that are conducted in the limiter circuit 14 have four stages of 21, 22, 23, and 24, and the boosted potential at this time is 8 stages.
[V]. Similarly, by sequentially switching the switching transistors from the on state to the off state by the timing control circuit 15, as shown in FIG.
The voltage rises stepwise to a high voltage Vpp for programming of 20 V. The time for boosting the voltage to about 20 [V] is later than the conventional one, but the programming time is the same as the conventional one.

As described above, in the present embodiment, the switches connected to the gates of the serially connected MOS transistors that constitute the limiter circuit are sequentially changed from the on-state to the off-state by using the timing control circuit, thereby forming a multi-stage series. The connected MOS transistors are sequentially turned on. As a result, the boosted potential rises in a stepwise manner without lowering the current supply capability, so that a high electric field is not applied to the tunnel insulating film, so that deterioration of the tunnel insulating film can be suppressed.

The present invention is not limited to the embodiments described above, but can be variously modified. For example, a PN junction diode may be used as the limiter circuit instead of the MOS transistors connected in multiple stages. Further, the present invention provides
For example, the present invention can be applied to a nonvolatile RAM in which an E ² PROM and an SRAM are combined.

〔The invention's effect〕

As described above, according to the present invention, the high voltage for programming smoothly rises in a stepwise manner without lowering the operation margin, so that the deterioration of the tunnel insulating film over time can be suppressed, A highly reliable nonvolatile semiconductor memory device can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing a booster waveform of the embodiment of the present invention, and FIG. 4 is a sectional view of a memory cell of an E ² PROM. 1 ... semiconductor substrate, 2 ... drain, 3 ... source, 5
... floating gate, 6 ... control gate, 7 ... tunnel insulating film, 11 ... booster circuit, 12 ... decoder circuit, 13 ... memory cell array, 14 ... limiter circuit, 15 ... timing control circuit, 21 ~ 30 ... MOS transistor, 31 ~ 37 ... Switch transistor.

Claims (4)

(57) [Claims] 1. A booster circuit for generating a boosted potential as an output, a plurality of circuit elements connected in series between an output of the booster circuit and a ground potential, and adjacent circuit elements connected in series A limiter circuit including a switch connected between the first and second switches; a timing control circuit for transmitting a signal for controlling the opening and closing of the switch; and a boosted potential (V PP) determined by the limiter circuit.
Is applied, and the output potential of the booster circuit is controlled by the limiter circuit and the timing circuit during one write or erase operation, so that the first potential is changed from the first potential to the first potential. A non-volatile semiconductor storage device, wherein the potential is changed in a stepwise manner to a second potential higher than the second potential. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said stepped-up potential is applied to said memory cell via a decoder circuit. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said circuit element is an insulated gate field effect transistor. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile memory cell is a read-only memory cell which can be electrically written and erased.