JP2754887B2 - Nonvolatile semiconductor memory device and write / erase method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory device, in particular, an electrically writable and erasable nonvolatile semiconductor memory device (ELECTRICALLY ERASA).
BLE PROM; EEPROM).

[Conventional technology]

FIG. 6 shows a conventional semiconductor memory device (EEPROM) in which avalanche injection is performed for writing and FN tunneling is performed for erasing, and one semiconductor memory element (hereinafter referred to as a memory cell) for electrically writing and erasing data. FIG.

 A normal EPROM has a similar structure.

In the figure, (1) is a P-type silicon semiconductor substrate having a concentration of about 1.5 × 10 ¹⁵ / cm ³ and a specific resistance of about 10 Ω-cm, and (2) is a concentration of about 1 × 10 5 formed on the silicon substrate (1). A well region of ¹⁶ / cm ³ , (3) a tunnel oxide film (gate oxide film) having a thickness of about 100 ° formed on the main surface of the silicon substrate (1), and (4) a gate oxide film (3) A floating gate made of a polycrystalline silicon layer formed thereon,
(5) is an interlayer insulating film formed on the floating gate (4), (6) is a control gate made of a polycrystalline silicon layer formed on the interlayer insulating film, (7)
Is an N ⁺ type source region formed by introducing arsenic at 1 × 10 ²⁰ / cm ^3, which is connected to a source line (not shown). (8) is a drain region similar to the source region,
(9) is a bit line directly connected to the drain region and made of an aluminum alloy, as is apparent from the drawing.

Next, the operation of this EEPROM will be described. Writing data to a memory cell is performed by applying a high-voltage applied externally.
12.5V is applied to the control gate (6), and the N ⁺ type drain region (8) is applied with a voltage stepped down from the externally applied high voltage to 8V via a load resistor. On the other hand, the N ⁺ source region (7) has a ground potential (GND) grounded via the source line. At this time, the N ⁺ source region (7)
Electrons move toward the N ⁺ drain region (8), and a current of about 0.5 mA flows through this memory cell. At this time, the moving electrons are accelerated by a high electric field near the drain region (8) and obtain high energy exceeding an energy barrier of 3.2 eV from the surface of the silicon substrate (1) to the gate oxide film (3). The electrons that have obtained this high energy are called hot electrons, and a part of them is pulled over by the high voltage of the control gate (6) over the barrier of the gate oxide film (3) and injected into the floating gate (4). You. Thus, the floating gate (4) is in a negatively charged state. This state corresponds to "0" of the data. Erase of memory cell is performed by externally applied high voltage 12.5V
Is applied to the source region (7) via the source line. On the other hand, the control gate (6) is grounded and the ground potential (GN
D), and the drain region (8) is in a floating state.

At this time, a high electric field is generated in the gate oxide film () between the floating gate (4) and the source region (7), and F-
N tunneling occurs, and a tunnel current flows between the floating gate (4) and the source region (7). Thus, the floating gate (4) is in an electrically neutral state or a positively charged state. This state corresponds to data “1”.

[Problems to be solved by the invention]

As described above, the conventional EEPROM in which avalanche injection is performed for writing and FN tunneling is performed for erasing is as follows. (A) When the voltage is applied to the drain region (8) at the time of writing, the current flowing at this time is 0.5 to 1 mA Since the power required for writing is large, a booster circuit formed on a semiconductor substrate on which a memory cell is formed based on a power supply potential of 5 V applied from the outside and driving various peripheral circuits,
The potential boosted by the so-called on-chip booster circuit (8
It is impossible to apply V) to the drain region (8), and it is necessary to apply a potential (8 V) obtained by stepping down a high voltage given from outside via a load resistor to the drain region (8). It was difficult to use a single 5V power supply.

(B) The memory cell of this structure does not have a select transistor, that is, the drain region (8) is directly connected to the bit line (9), and the source region (7) is connected to the source line. Therefore, the erasure is usually performed in a lump of all data or in a unit of several kilobytes even in a small unit. Therefore, even if the current flowing per memory cell at the time of erasing is on the order of nA (especially junction leakage current), if erasing is performed in units of kilobytes or megabytes, a current on the order of μA to mA will flow.
For this reason, a high voltage applied to the source region (7) at the time of erasing cannot be generated in the on-chip booster circuit for the same reason as described above.

Regarding the voltage applied to the drain region (8) at the time of writing (a), as the impurity concentration in the well region (2) increases due to scaling accompanying high integration, the generation rate of hot electrons increases. However, the applied voltage 8V may decrease. FIG. 2 shows an example. This is an example in which writing can be performed with a drain voltage of 5 V and a gate voltage of 12 V by optimizing the well concentration and the drain structure. As shown, sufficient writing has been performed with a pulse width of 10 μSec, and practical operating characteristics have been obtained. The high voltage 12V applied to the control gate (6) at the time of writing requires little writing power because almost no current flows, and the potential boosted by the on-chip boosting circuit based on the power supply potential of 5V applied from the outside ( Even if 12V) is applied to the control gate (6), driving can be performed without any problem, and data can be written to the memory cell by a power supply potential of 5V applied from the outside.

On the other hand, since the FN tunneling is used in the erasing operation (b), a high electric field of 10 MV / cm or more is required in the gate oxide film between the source region (7) and the floating gate (4). Further, the thickness of the gate oxide film (3) cannot be extremely reduced due to problems in device characteristics and reliability. For this reason, it is difficult to lower the voltage applied to the source region (7).

Further, as described above, when the well concentration is increased for lowering the writing voltage and for operating the fine transistor, the junction breakdown voltage is reduced, and the device is greatly deteriorated by the erasing operation. That is, when the control gate (6) is set to the ground potential and a high voltage is applied to the source (7), an inter-band tunneling phenomenon occurs at the overlapping portion of the floating gate (4) and the source region (7). The electrons generated by this inter-band tunneling
Holes of the hole pairs are repelled by the positive potential of the source region (7) and flow toward the channel region or the substrate (1). At this time, the well concentration is high and the junction breakdown voltage of the source region (7) is low as described above.

In other words, if the avalanche phenomenon is likely to occur, the generated holes cause avalanche breakdown, and a large number of generated holes are attracted to the vertical electric field and injected into the floating gate (4).

In other words, when the well concentration becomes higher, the vertical electric field between the floating gate (4) and the source region (7) is more effective than the extraction of electrons from the floating gate (4) to the source region (7) by FN tunneling. Band-to-band tunneling occurs, and electron-hole pairs are generated. These holes are accelerated by a lateral electric field between the source region (7) and the drain region (8), causing avalanche breakdown, and generating a large amount of hot holes. Erasing is caused by the implantation.

It is known that hole injection causes a greater damage to the gate oxide film (3) than electron injection. ) Deteriorates rapidly and the number of rewrites cannot be secured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in consideration of a non-volatile semiconductor memory device (EEPRO) operable with a single power supply and having an increased number of data rewrites.
M) is intended to gain.

[Means for solving the problem]

A nonvolatile semiconductor memory device according to a first aspect of the present invention includes a second conductive type source region formed on one main surface of a first conductive type semiconductor substrate and connected to a source line, and one main surface of the semiconductor substrate. A drain region of the second conductivity type formed from the source region via the channel region and directly connected to the bit line; a floating gate formed on the channel region via an insulating film; A memory cell consisting solely of a transistor element having a control gate and a control gate formed facing each other with an insulating film interposed therebetween, and formed on one main surface of the semiconductor substrate;
When erasing data in the memory cell, a first pulse having a first width and a negative potential is applied to the control gate, and the first pulse is supplied to the control gate via the source line.
And a write / erase means for applying a second pulse of a positive potential having a second width smaller than the width of the first pulse to the source region within an application period of the first pulse.

Further, in the nonvolatile semiconductor memory device according to the second invention, the write / erase means applies a third pulse having a third width and having a positive potential to the control gate when writing data to the memory cell. , Via the bit line,
A fourth pulse having a fourth width smaller than the third width and having a positive potential lower than the positive potential of the third pulse is supplied to the drain region within the application period of the third pulse. In addition to the applying means, an applying means for applying the ground potential to the source region is further provided.

Further, the nonvolatile semiconductor memory device according to the third invention is characterized in that:
The semiconductor substrate further includes a semiconductor well region of a first conductivity type having a higher concentration than that of the semiconductor substrate formed on one main surface of the semiconductor substrate, and a source region and a drain region are formed on one main surface of the semiconductor well region. It is formed in.

Further, the nonvolatile semiconductor memory device according to the fourth invention is formed on one main surface of the first conductivity type semiconductor substrate in the nonvolatile semiconductor memory device driven by the first power supply potential applied from the outside. The second connected to the source line
A conductive type source region, a second conductive type drain region formed on one main surface of the semiconductor substrate from the source region via a channel region and directly connected to a bit line, and an insulating film on the channel region A memory cell consisting solely of a transistor element having a floating gate formed through the substrate and a control gate formed on the surface of the floating gate so as to oppose the insulating gate via an insulating film, and one main surface of the semiconductor substrate An internal negative potential generating means driven by the single power supply potential and outputting a negative potential; and a first width output from the internal negative potential generating means when data is erased from the memory cell. A first pulse having a negative potential is applied to the control gate, and based on the single power supply potential via the source line. And a potential applying means for applying a second pulse composed of a positive potential having a second width smaller than the first width to the source region within an application period of the first pulse. It is provided with writing / erasing means.

Further, the nonvolatile semiconductor memory device according to the fifth invention is characterized in that:
An internal high-potential generating means driven by a single power supply potential and outputting a positive potential higher than the single power-supply potential; and And a third pulse having a third potential and having a third potential and output from the third gate based on the single power supply potential is applied to the control gate via the bit line. A fourth pulse having a narrow fourth width and having a positive potential lower than the positive potential of the third pulse is applied to the drain region within an application period of the third pulse, and a ground potential is applied. Is further provided to apply a potential to the source region.

Further, a writing / erasing method for a nonvolatile semiconductor memory device according to a sixth aspect of the present invention includes a second conductivity type source region formed on one main surface of the first conductivity type semiconductor substrate and connected to a source line; A second conductivity type drain region formed on the one main surface of the semiconductor substrate from the source region via a channel region and directly connected to a bit line; and a floating region formed on the channel region via an insulating film. In a method for writing and erasing a nonvolatile semiconductor memory device comprising a memory cell comprising only a transistor element having a gate and a control gate formed on a surface of the floating gate so as to face through an insulating film, the memory At the time of erasing data from the cell, after applying a first pulse of a negative potential having a first width to the control gate, Applying, via a line, a second pulse of a positive potential having a second width smaller than the first width to the source region within an application period of the first pulse; This is to extract the electrons accumulated in the gate.

In the method for writing / erasing data in a nonvolatile semiconductor device according to a seventh aspect of the present invention, at the time of writing data to a memory cell, a third pulse of a positive potential having a third width is applied to the control gate, A fourth pulse having a fourth width smaller than the third width and having a positive potential lower than the positive potential of the third pulse is applied through a line to an application period of the third pulse. And applying a ground potential to the source region to accumulate electrons in the floating gate.

[Action]

In the first and second inventions, the writing / erasing means applies a first pulse having a negative potential to the control gate at the time of data erasing, thereby lowering the potential of the floating gate by capacitive coupling to reduce the source. The positive potential of the second pulse applied to the region can be reduced, the lateral electric field between the source region and the drain can be reduced to reduce the generation of hot holes, and the negative potential for applying to the control gate and the source can be reduced. A positive potential for application to the region can be generated at the same power supply potential applied from the outside, and the source region has a second width smaller than the first and the width within the application period of the first pulse. By giving the second pulse having a positive potential, the charge current flowing from the source region to the drain region can be suppressed, and the Hophole due to the charge current can be reduced. Formed can be suppressed.

Further, in the third invention, since the source region and the drain region of the transistor element of the memory cell are formed in the semiconductor well region having a higher concentration than the substrate concentration, the potential applied to the drain region at the time of data writing is reduced. The potential for application to the control gate and the potential for application to the drain region can be generated at the same power supply potential applied from the outside,
The erasing means applies a first pulse having a negative potential to the control gate at the time of data erasure, whereby the potential of the floating gate is lowered by capacitive coupling and the positive potential of the second pulse applied to the source region is reduced. , The generation of hot holes can be reduced by reducing the lateral electric field between the source region and the drain, and the negative potential applied to the control gate and the positive potential applied to the source Can be generated at the same power supply potential applied from the power supply.

Further, in the fourth and fifth inventions, a negative potential is applied to the control gate at the time of data erasing, so that the internal negative potential generation of the writing / erasing means for applying a negative potential to the control gate is performed. The means can be driven by a single power supply potential, and the positive potential applied to the source region of the transistor element of the memory cell can be made a positive potential based on the single power supply potential, thereby enabling a single power supply. The generation of hot holes can be reduced by reducing the lateral electric field between the region and the drain region.

Further, in the sixth and seventh inventions, the potential of the floating gate is lowered by the capacitive coupling by applying the first pulse having a negative potential to the control gate at the time of data erasure, and the potential of the source region is reduced. The positive potential of the second pulse to be applied can be lowered, the generation of hot holes can be reduced by reducing the lateral electric field between the source region and the drain, and the negative potential for application to the control gate and the source region can be reduced. A positive potential for application can be generated at the same power supply potential applied from the outside, and a positive potential having a second width smaller than the first width within the application period of the first pulse is applied to the source region. By applying the second pulse having the potential of the charge current, the charge current flowing from the source region to the drain region can be suppressed, and Generation of can be suppressed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an operation mode according to the present invention. At the time of writing (A), first, the source potential (Vs) is set to 0V, and the control gate voltage (Vg) is increased to 12V. Thereafter, the drain voltage (Vd) is increased to 5V. At this time, the voltage pulse width applied to the drain (7) is about 10 μSec. After that, the drain voltage is set to 0V, and then the control gate voltage is set to 0V. FIG. 2 shows the characteristics of the memory cell operated under such a write condition. Well concentration 5
By setting the processing temperature during wafer processing to 900 ° C. or less at × 10 ¹⁶ / cm ³ and a drain concentration of 1 × 10 ²⁰ / cm ³ , a drain voltage of 5
With V, the control gate voltage is 12 V, and the threshold voltage Vth is 7 V at 10 μSec, a sufficient write state is obtained. At the time of writing, although the voltage applied to the control gate (6) is 12V, as described in the item of the problem to be solved by the invention, the voltage applied from the outside is 5V.
Even if a potential (12 V) boosted by the on-chip boosting circuit based on the power supply potential of the semiconductor well is applied to the control gate (6) without any problem, the semiconductor well region (2) in which the drain region (8) is formed Concentration of 5 × 10 ¹⁶ / c
Since the concentration is as high as m ³ , the voltage applied to the drain region (8) may be 5V, and can be applied based on a power supply potential of 5V applied from outside without providing a special booster circuit. In short, for writing data, a positive high voltage is generated in the control gate (6) (generated by the internal high potential generating means) to apply a positive high voltage, and a positive potential is applied to the drain region (8). Write / erase means
It can be formed on the same semiconductor substrate on which a memory cell is formed, and can be driven by a single power supply potential (5 V).

At the time of erasing, as shown in FIG. 1B, first, the drain voltage (Vd) is set to a floating state, and the control gate voltage (Vg) is set to -12V. After that, the source voltage (Vs) is increased to 5V. At this time, the voltage pulse width applied to the source region (7) is about 100 mSec.

At the time of this erasing, although the voltage applied to the control gate (6) is -12 V, almost no current flows through the control gate (6). Even if the potential (-12V) stepped down by the step-down circuit is applied to the control gate (6), the drive can be performed without any problem. In addition, the voltage applied to the source region (7) may be 5V, and no special step-up circuit is required. It can be applied based on a power supply potential of 5 V applied from the outside. In short, in order to erase data, a negative voltage is generated at the control gate (6) (generated by the internal negative potential generating means) to apply a negative voltage, and a positive voltage is applied to the source region (7). The erasing means can be formed on the same semiconductor substrate on which the memory cells are formed, and can be driven by a single power supply potential (5 V).

Next, the erase characteristics of the memory cell operated under such erase conditions are shown in FIG.

FIG. 3 also shows, for comparison, the erase characteristics when a conventional control gate is applied with 10 V to a 0 V source. Thus, -12V is applied to the control gate (6).
It can be seen that the erasing operation is sufficiently performed even when the source voltage is 5 V by applying. In order to confirm the current components generated in these two types of erase modes, a measurement as shown in FIG. 4 was performed.

FIG. 4 shows a floating gate (6) of a memory cell.
Are connected to the electrodes, and the source voltage dependence of the source current and the gate current is measured. At this time, the substrate (1) is grounded, and the drain region is floating. The solid line corresponds to the conventional control gate 0 V erase, and the broken line is the power supply-voltage graph corresponding to the control gate according to the present invention, which is applied with -12 V applied. Since the capacitive coupling ratio between the control gate (6) and the floating gate (4) is about 0.5, -5 V is applied to the gate voltage Vg in FIG.

In any of the modes, as can be seen from the source current, avalanche breakdown occurs at a source voltage (Vs) of about 8V.

At this time, it can be seen that when Vg = ground (GND), almost no gate current flows, and no erase operation is performed. Furthermore, at the source voltage (Vs) of 10 V, complete avalanche breakdown occurs, and although the gate current flows, it is considered that most of the current is due to hot hole injection. On the other hand, under a gate (Vg) -5 V application condition, a gate current starts to flow from a source voltage (Vs) of about 4 V. Since avalanche breakdown occurs around 8V, there is sufficient margin at a source voltage (Vs) of 5V, and this gate current is F-
It is considered that the electron current due to N tunneling is dominant. By applying a negative potential to the gate in this manner, it was confirmed that the source potential could be kept low, and the generation of hot holes was suppressed by the relaxation of the lateral electric field.

FIG. 5 shows the measured rewriting characteristics of a single memory cell. The white circle is the conventional control gate 0V,
The characteristics at the time of erasing the source 10 V are shown, and the black circles show the characteristics at the time of erasing the control gate -12 V and the source 5 V of the present invention. All pulse widths are 100mSec, writing is drain
The test was performed at 5 V, control gate 12 V, and 10 μSec. As is clear from FIG. 5, the erasing mode proposed in the present invention has a significantly improved rewriting characteristic as compared with the conventional method.

Moreover, after applying -12 V to the control gate (6), 5V is applied to the source region (7), the applied potential of the source region (7) is set to 0V, and then the applied potential of the control gate (6) is set to 0V. Therefore, when −5 V is applied to the control gate (6) whenever 5 V is applied to the source region (7), the charge current flowing from the source region to the drain region can be suppressed. The generation of hot holes due to the charge current can be suppressed, the injection of hot holes into the gate insulating film (3) decreases, and the number of times of data rewriting can be increased.

[Effects of the Invention] The first and second inventions of the present invention store data depending on whether electrons are accumulated in the floating gate or whether the accumulated electrons are withdrawn, and the electrically writable / erasable floating gate is provided. In those having a memory cell consisting only of a gate type transistor element,
A first pulse formed on one main surface of the semiconductor substrate and having a negative potential having a first width and applied to a control gate of a transistor element of the memory cell when data is erased from the memory cell, Writing / erasing means for applying a second pulse having a second potential smaller than the first width and having a positive potential to the source region of the transistor element through the source line during the application period of the first pulse; Since the first pulse having a negative potential is applied to the control gate during data erasing, the potential of the floating gate is lowered by capacitive coupling, and the positive potential of the second pulse applied to the source region is erased. And the generation of hot holes can be reduced by reducing the lateral electric field between the source region and the drain. And the number of data rewrites can be increased, and a negative potential to be applied to the control gate and a positive potential to be applied to the source region can be generated at the same external power supply potential. And a second pulse having a positive potential having a second width smaller than the first width is applied to the source region within the application period of the first pulse. As a result, the charge current flowing from the source region to the drain region is suppressed, and the generation of hot holes due to the charge current is suppressed. It is what you have.

A third aspect of the present invention comprises only a floating gate type transistor element which stores data depending on whether electrons are accumulated in the floating gate or whether the accumulated electrons are extracted and which can be electrically written and erased. In a device having a memory cell, the source region and the drain region of the transistor element of the memory cell are formed in a semiconductor well region having a higher concentration than the substrate concentration, and are formed on one main surface of the semiconductor substrate. Applying a first pulse of a negative potential having a first width to the control gate of the transistor element of the memory cell, and applying a second width to the source region of the transistor element of the memory cell via a source line. Since the writing / erasing means for applying the second pulse having the positive potential is provided. The potential applied to the drain region during data writing can be lowered, and the potential for applying to the control gate and the potential for applying to the source region can be generated at the same power supply potential applied from the outside. By applying the first pulse having a negative potential to the control gate, the potential of the floating gate is reduced by capacitive coupling, and the positive potential of the second pulse applied to the source region can be reduced. Since the generation of hot holes can be reduced by reducing the horizontal electric field between the drains, the injection of hot holes into the gate insulating film decreases, the number of times of data rewriting can be increased, and the negative potential for applying to the control gate can be reduced. And the same power supply voltage applied externally to apply a positive potential for application to the source region. Those having the effect that occupies not allow a single power reduction and can generate at.

According to the fourth and fifth aspects of the present invention, a floating gate transistor capable of electrically writing and erasing data by storing data depending on whether electrons are accumulated in the floating gate or the accumulated electrons are extracted. An internal negative potential generating means which is formed on one main surface of a semiconductor substrate, is driven by a single power supply potential, and outputs a negative potential, A negative potential output from the internal negative potential generating means is applied to the control gate of the transistor element of the memory cell, and a positive potential based on a single power supply potential is applied to the source region of the transistor element of the memory cell via the source line. Since the writing / erasing means having the potential applying means for applying the The internal negative potential generating means of the writing / erasing means for applying the voltage can be driven by a single power supply potential, and the positive potential applied to the source region of the transistor element of the memory cell is changed to a positive potential based on the single power supply potential. In addition to the effect that a single power supply can be achieved, the generation of hot holes can be reduced by reducing the lateral electric field between the source region and the drain, so that the injection of hot holes into the gate insulating film is reduced. This has the effect that the number of times of data rewriting can be increased.

Further, according to the sixth and seventh inventions, a floating gate type transistor capable of electrically writing and erasing data by storing data depending on whether electrons are accumulated in the floating gate or the accumulated electrons are extracted. In a device having a memory cell consisting of only elements, a negative potential is applied to the control gate of the transistor element of the memory cell, and then a positive potential is applied to the source region of the transistor element of the memory cell via a source line. Since the electrons accumulated in the floating gate of the transistor element of the memory cell are extracted, by applying a negative potential to the control gate, the potential of the floating gate is lowered by capacitive coupling and the positive potential applied to the source region is reduced. Potential between the source region and the drain Since the generation of hot holes can be reduced by reducing the lateral electric field, the injection of hot holes into the gate insulating film decreases, the number of times of data rewriting can be increased, and a negative potential and a source region to be applied to the control gate can be achieved. A positive potential to be applied to the source region can be generated at the same power supply potential applied from the outside, thereby making it possible to use a single power supply. Further, a positive potential applied to the source region is applied to the control gate by a negative potential. After applying the potential, the charge current flowing from the source region to the drain region is suppressed, and the generation of hot holes due to the charge current is suppressed. Therefore, the injection of further hot holes into the gate insulating film is reduced and data is rewritten. This has the effect of increasing the number of times.

[Brief description of the drawings]

FIG. 1 is an operation mode diagram of a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 shows write characteristics. The vertical axis shows Vth of a memory cell after writing, and the horizontal axis shows high voltage pulse width. ing. FIG. 3 shows the erasing characteristics. The black circles indicate the erasing characteristics in the gate negative application erasing mode according to the present invention, and the white circles indicate the erasing characteristics in the conventional gate 0 V erasing mode. FIG. 4 is a graph showing a source voltage dependency of a gate current and a source current in an element having an electrode connected to a floating gate of a memory cell. The solid line corresponds to the gate 0V erase in the conventional example, and the broken line corresponds to the gate negative applied erase of the present invention. FIG. 5 shows the number of times of rewriting due to the difference between the erasing method of the present invention and the conventional example.
White circles indicate the results of the conventional example, and black circles the results of the erasing method according to the present invention. FIG. 6 shows sectional structures of a memory cell according to the conventional example and the present invention, wherein (1) is a semiconductor substrate, (2) is a well region, (3) is a gate oxide film, and (4) is a floating gate. , (5) indicates an interlayer insulating film, (6) indicates a control gate, (7) indicates a source region, (8) indicates a drain region, and (9) indicates a bit line. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (7)

(57) [Claims] A source region of a second conductivity type formed on one main surface of a semiconductor substrate of a first conductivity type and connected to a source line;
A second surface formed on one main surface of the semiconductor substrate from the source region via a channel region and directly connected to a bit line;
Only a transistor element having a drain region of a conductivity type, a floating gate formed on the channel region via an insulating film, and a control gate formed on the surface of the floating gate and facing the insulating film via an insulating film And a first pulse formed on one main surface of the semiconductor substrate and having a negative potential having a first width and applied to the control gate when data is erased from the memory cell. , A second line narrower than the first width via the source line.
A non-volatile semiconductor memory device, comprising: a writing / erasing means for applying a second pulse having a width of a positive potential to the source region within an application period of the first pulse. 2. A writing / erasing means for applying a third pulse of a positive potential having a third width to a control gate at the time of writing data to a memory cell, and applying the third pulse via a bit line. A fourth pulse having a fourth width smaller than the width of the third pulse and having a positive potential lower than the positive potential of the third pulse.
2. The non-volatile semiconductor memory device according to claim 1, further comprising an application unit that applies the pulse to the drain region during the application period of the third pulse and applies a ground potential to the source region. 3. A semiconductor substrate formed on one main surface thereof.
The semiconductor well region of a first conductivity type having a higher concentration than the semiconductor substrate, and the source region and the drain region are formed on one main surface of the semiconductor well region. 3. The nonvolatile semiconductor memory device according to item 2. 4. A nonvolatile semiconductor memory device driven by a first power supply potential applied from the outside, wherein said nonvolatile semiconductor memory device is formed on one main surface of a semiconductor substrate of a first conductivity type and connected to a source line. A source region, a second conductivity type drain region formed on one main surface of the semiconductor substrate from the source region via a channel region, and directly connected to a bit line, and an insulating film on the channel region. A memory cell consisting of only a transistor element having a floating gate formed by the above, and a control gate formed on the surface of the floating gate so as to face through an insulating film, and formed on one main surface of the semiconductor substrate. Internal negative potential generating means driven by the single power supply potential and outputting a negative potential; and the internal negative potential generating means for erasing data in the memory cell. Applying a first pulse of a negative potential having a first width and output from the potential generating means to the control gate, and via the source line, based on the single power supply potential, Writing / erasing having potential applying means for applying a second pulse composed of a positive potential having a second width smaller than the first width to the source region within an application period of the first pulse; A nonvolatile semiconductor memory device comprising: 5. An internal high potential generating means driven by a single power supply potential and outputting a positive potential higher than the single power supply potential, wherein the writing / erasing means is configured to write the data to a memory cell when writing the data. A third pulse consisting of a positive potential having a third width and output from the internal high potential generating means is applied to a control gate, and the third pulse is applied to the control gate via the bit line based on the single power supply potential. A fourth pulse having a fourth width smaller than the third width and having a positive potential lower than the positive potential of the third pulse is applied to the drain region within the application period of the third pulse. 5. The nonvolatile semiconductor memory device according to claim 4, further comprising a potential applying means for applying a ground potential to the source region. 6. A source region of a second conductivity type formed on one main surface of a semiconductor substrate of a first conductivity type and connected to a source line;
A second surface formed on one main surface of the semiconductor substrate from the source region via a channel region and directly connected to a bit line;
Only a transistor element having a drain region of a conductivity type, a floating gate formed on the channel region via an insulating film, and a control gate formed on the surface of the floating gate and facing the insulating film via an insulating film In the method for writing and erasing a nonvolatile semiconductor memory device including a memory cell comprising: a first pulse having a first width and a negative potential having a first width is applied to the control gate when erasing data from the memory cell. Later, a second pulse having a second width smaller than the first width and having a positive potential is applied to the source region via the source line within an application period of the first pulse. Extracting electrons stored in the floating gate, and writing / erasing the nonvolatile semiconductor memory device. 7. When writing data into a memory cell, a third pulse having a third width and a positive potential is applied to a control gate, and a fourth pulse narrower than the third width is applied via a bit line. A fourth pulse having a width of a lower positive potential than the positive potential of the third pulse is applied to the drain region within the application period of the third pulse, and the ground potential is applied to the source region. 7. The method according to claim 6, further comprising accumulating electrons in the floating gate by applying a voltage to the floating gate.