JPH04220012A - Selection circuit - Google Patents

Abstract

PURPOSE:To realize the selection circuit to select one selected signal among plural selected signals divided into two groups or the like. CONSTITUTION:Plural selected signals selected by the selection circuit are divided into plural numbers represented by a high-order binary selection signal in a binary selection signal group from a selection setting circuit 2 and each selected signal belonging to the selected signal group is fed to an input to a 1st selection circuit 4. A selected signal in the selected signals fed to each 1st selection circuit 4 is selected by a low-order binary selection signal in the said binary selection signal group from the said selection setting circuit 2. The one selected signal in the said selected signal group inputted to the 2nd selection circuit 6 and selected by the 1st selection circuits 4 is selected and outputted by the said 2nd selection circuit 6. Thus, the hardware required to form the signal selection circuit is saved and this method is advantages in the mount of a printed circuit board.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selection circuit that selects one of two groups of bit data to be selected. In printed board circuits, a selection circuit may select one of the binary bit data for use. There is a demand for mounting many elements on the printed board circuit, and in order to meet this demand, it is necessary to configure one element or one functional circuit as small as possible. The same applies to the selection circuit.

0002

2. Description of the Related Art An example of a conventional selection circuit is shown in FIG. This selection circuit consists of a hexadecimal switch 30, a ROM 32, and tri-state output buffers 340-3415. The address signal output from the hexadecimal switch 30 is
It is supplied to address inputs A0 to A3 of the ROM 32, and a selection signal is output from its output. Binary bit data D0 to D15 are input to the inputs of the tristate output buffers 340 to 3415, respectively, and selection signals O0 to O15 of the ROM 32 are supplied to selection control inputs of the tristate output buffers 340 to 3415. 1 of the binary bit data D0 to D15
are selected by selection signals O0 to O15 from the ROM 32. For example, as shown in FIG.
If the binary signals inputted from the decimal switch 30 to the address inputs A0 to A3 of the ROM 32 are all low level signals (switch positions 0 and (1) in FIG.
(see (4)), and the binary bit data D0 is selected by the tri-state output buffer 340 (see ((4) in FIG. 5).
5) to (21)), if only the binary signal input to the address input A0 is at a high level signal and all other address inputs A1 to A3 are at a low level signal (see Figure 5). In switch position 1 (see (1) to (4)), the binary bit data D1 is selected in the tri-state output buffer 340 ((6) in FIG.
(See (20)). Furthermore, if the binary signals input from the hexadecimal switch 30 to the address inputs A0 to A3 of the ROM 32 are all at high level (see (1) to (3) in FIG. 5), the binary signals are input to the address inputs A0 to A3 of the ROM 32. Bit data D15 is selected in tri-state output buffer 3415 (switch positions 15 and (19) to (
20)).

The binary bit data selected as described above is used for controlling a controlled circuit (not shown).

0004

[Problem to be solved by the invention] One ROM used in the conventional selection circuit requires a 16-pin IC, and four buffers require one 16-pin IC. Since six 16-pin ICs are required, the circuit scale is large, and if you try to mount this selection circuit on a printed board, it will consume a lot of mounting area on the printed board, and it will be difficult to install it on the printed board. A problem arises in the implementation.

The present invention was created in view of the above technical problem, and is characterized by providing a selection circuit which has a small circuit scale and is advantageous in mounting on a printed board or the like.

[0006]

SUMMARY OF THE INVENTION FIG. 1 shows a block diagram of the principle of the present invention. As shown in FIG. 1, the present invention includes a selection setting circuit 2 that outputs a binary selection signal group, and a plurality of selected signals represented by upper binary selection signals in the binary selection signal group. It has an input to which each selected signal belonging to the selected signal group divided into selected signal groups is separately supplied, and one selected signal among the inputted selected signals is used as the binary selection signal. A first selection circuit 4 for each selected signal group is selected by the lower binary selection signal in the group, and the output signal of each first selection circuit 4 is supplied to the input, and the output signal of each first selection circuit 4 is supplied to the input, and a second selection circuit 6 that selects the output signal of one of the first selection circuits 4.

[0007]

[Operation] A plurality of selected signals selected by the selection circuit of the present invention are divided into a plurality of signals represented by upper binary selection signals in the binary selection signal group from the selection setting circuit 2,
Each selected signal belonging to the selected signal group is supplied to the input of the first selection circuit 4 corresponding to the selected signal group.

In each of the first selection circuits 4, one of the selected signals supplied thereto is one of the lower two selected signals in the group of binary selection signals from the selection setting circuit 2.
Selected by the forward selection signal. One selected signal in the selected signal group selected by each of the first selection circuits 4 and inputted to the second selection circuit 6 is selected and outputted by the second selection circuit 6. be done.

As described above, according to the present invention, in order to select one selected signal from a plurality of selected signals, the selection setting circuit 2, the first selection circuit 4, and the first 2
Since it is only necessary to provide the selection circuit 6, the amount of hardware required to configure the signal selection circuit can be reduced. This is advantageous when mounting on a printed board.

0010

Embodiment FIG. 2 shows an embodiment of the present invention. As shown in this figure, hexadecimal switch 20, 8→1 selector 22
1, 8→1 selector 222, and 2→1 selector 2
Consists of 4. The bit output signals of the 8th to 2nd bits in binary representation of the hexadecimal switch 20 are supplied to selection inputs A1 to A3 of the 8→1 selector 221 and the 8→1 selector 222. Binary bit input D0 to D of 8→1 selector 221
7 contains even binary bit data D0, D2, D4
, D6, D8, D10, D12, and D14 are input separately. Binary bit inputs D0 to D of 8→1 selector 222
7, odd binary bit data D1, D3, D5
, D7, D9, D11, D13, and D15 are input separately. The output Y0 of the 8→1 selector 221 and the binary bit data output Y1 of the 8→1 selector 222 are 2→1
It is input to the binary bit data inputs D0 and D1 of the selector 24. The selection input A0 of the 2→1 selector 24 is supplied with the first bit output signal A0 in the binary representation of the hexadecimal switch 20.

In FIG. 2, the 8→1 selector 221 corresponds to the selection setting circuit 2 in FIG.
2 corresponds to the first selection circuit 4 in FIG. 1, and the 2→1 selector 24 corresponds to the second selection circuit 6 in FIG. The operation of the present invention configured as described above will be explained below. Even binary bit data D0, D2, D4, D6,
D8, D10, D12, and D14, and odd binary bit data D1, D3, D5, D7, D9
, D11, D13, and D15 are the 8→1 selector 22
1 and 8→1 selector 222,
Any one of them can be selected and output by outputting a bit output signal corresponding to the binary bit data desired to be output from the hexadecimal switch 20. For example, when you want to output even binary bit data D0, by setting the setting position of the hexadecimal switch 20 to "0" (see switch position 0 in FIG. 3), the hexadecimal switch 20 outputs the 8th position in binary representation. All of the first to first bit output signals are set to low level signals (see (() in Figure 3).
1) to (4)). As a result, the even number 2 is set by the 8→1 selector 221 and the 8→1 selector 222.
hex bit data D0, and odd binary bit data D1
is selected. Selected binary bit data D0
, D1 is selected by the 2→1 selector 24 by the low level bit output signal A0 (see (1) in FIG. 3). When you want to output odd binary bit data D1, set the hexadecimal switch 20 to "1" (see switch position 1 in FIG. 3), and the hexadecimal switch 20 will output the 1st bit in binary representation. Only the output signal is set to a high level signal, and all of the 8th to 2nd bit output signals in binary representation are set to low level signals (see (1) to (4) in Figure 3). . As a result, the 8→1 selector 221
The even binary bit data D0 and the odd binary bit data D1 are selected by the 8→1 selector 222, but in this case, the binary bit data D1 is
1 selector 24 selects a high level bit output signal A.
0 (see (1) in Figure 3).

The relationship between the even binary bit data D0 and the odd binary bit data D1 is determined by the hexadecimal switch 20.
From 8→1 selector 221 and 8→1 selector 222
Except that the combinations of high level signals and low level signals of the bit output signals A1 to A3 of the 8th to 2nd positions in binary representation supplied to the selection inputs of the switch positions 2 to 2 in FIG. (See switch position 15)
, even binary bit data D2 and odd binary bit data D3, even binary bit data D4 and odd binary bit data D5, ..., even binary bit data D1
The same applies to the 4 and odd binary bit data D15.

[0013] The hardware required to perform such an operation is that the 8→1 selector 221, 8→1 selector 222, and 2→1 selector 24 each have 16
Since the pin IC can be configured with one pin IC, in the above embodiment, the selection circuit is constructed using a smaller number of 16-pin ICs, that is, three 16-pin ICs, compared to the selection circuit explained in the [Prior Art] section. Can be configured.

[0014] The above embodiment is only one specific example, and other numbers may be used. Furthermore, it is not necessarily necessary that the numbers be even or odd. What is necessary is, for example, if the signals input to the inputs of the 8→1 selector 221 and 8→1 selector 222 correspond to the binary representation bit output signals supplied to the selection inputs. That's enough.

[0015]

As explained above, according to the present invention, a plurality of selected input signals are divided into groups as many as the number represented by the upper binary selection signal of the binary selection signal group, and the divided Since one selected input signal among the selected input signal group is selected by the lower binary selection signal of the binary selection signal group, one selected input signal among the plurality of selected input signals The amount of hardware required to select signals can be reduced. Therefore, the mounting area required for mounting on the device can also be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a principle block diagram of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing a time chart of an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional selection circuit.

FIG. 5 is a diagram showing a time chart of a conventional selection circuit.

[Explanation of symbols]

2 Selection setting circuit 4 First selection circuit 6 Second selection circuit

Claims (1)

[Claims] 1. A selection setting circuit (2) that outputs a binary selection signal group; and a plurality of selected signal groups, the plurality of selected signals being represented by upper binary selection signals in the binary selection signal group. It has an input that separately supplies each selected signal belonging to the selected signal group divided into two groups, and one of the inputted selected signals
a first selection circuit for each selected signal group that selects one selected signal using a lower binary selection signal in the binary selection signal group
4) and the output signal of each said first selection circuit (4) is supplied to an input, said upper binary selection signal selects a first selection circuit of one of said respective first selection circuits (4). (4) A selection circuit comprising a second selection circuit (6) for selecting the output signal.