JPH04217357A - Semiconductor apparatus and its manufacture - Google Patents

Abstract

PURPOSE:To make a semiconductor apparatus smaller without decreasing its Early voltage by forming a groove so as to surround the first diffusion layer formed in an epitaxial layer on a substrate of a semiconductor and also forming the second diffusion layer so as to surround said groove. CONSTITUTION:A groove 21 is formed by surrounding an emitter diffusion layer 8 in an epitaxial layer 3 on a semiconductor substrate 1. Then, the inside of the groove 21 is filled up with the first heat oxide film 22 and a polysilicon layer 23, and a collector diffusion layer 7 is formed by surrounding the groove 21. By doing this, the effective base width WB is determined by the depth (d) and width (w)of the groove 21 and the base width WB becomes equal to (2Xd+w), so that the width (w) of the groove 21 can be reduced by increasing the depth (d) of the groove 21 without making the depth too close to the substrate 1. Therefore, the semiconductor apparatus can be made smaller while securing a sufficient base width WB and, moreover, any trouble due to a drop in Early voltage can be prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a lateral bipolar transistor and a method for manufacturing the same.

0002

[Prior Art] FIG. 10 shows a conventional semiconductor device, lateral type p
1 is a cross-sectional view of an np transistor, in which 1 is a p-type semiconductor substrate and 2 is an n+ semiconductor formed on the surface of the substrate 1.
3 is an n- type epitaxial layer formed on the substrate 1 and the buried diffusion layer 2, 4 is a field oxide film formed on the surface of the epitaxial layer 3 by the LOCOS method, and 5 is a p+ type buried diffusion layer. 6 is an oxide film formed on the element isolation 5; 7, 8, and 9 are p+ type collector diffusion layers and p+ type emitters formed in the collector region, emitter region, and base region of the surface of the epitaxial layer 3, respectively. A diffusion layer, an n+ type base diffusion layer, 10, 11, and 12 are electrodes formed in contact with the collector diffusion layer 7, emitter diffusion layer 8, and base diffusion layer 9, respectively, and 13 is a PSG film for surface protection.

[0003] Normally, in bipolar integrated circuits, horizontal pn
The fabrication of a p-transistor is carried out, and the p+ diffusion of the base of the npn transistor is connected to the collector of the pnp transistor,
The n+ diffusion of the emitter of an npn transistor corresponds to the diffusion of the base of a pnp transistor, and the lateral pnp transistor is manufactured by substantially the same process as that of the npn transistor.

Next, FIGS. 11 to 18 show the horizontal type p
FIG. 3 is a cross-sectional view showing the manufacturing process of the nn transistor, and each process will be described below.

First, as shown in FIG. 11, an n+ type buried diffusion layer 2 called a floating collector is formed on the surface of a substrate 1, and then an n- type epitaxial layer is formed on the substrate 1 and the buried diffusion layer 2. 3 is formed. At this time,
The purpose of the buried diffusion layer 2 is to maintain a breakdown voltage between the collector and emitter and the substrate 1.

Next, as shown in FIG. 12, a thin underlying oxide film 14 is formed on the surface of the epitaxial layer 3, and a nitride film 15 is formed thereon by LPCVD or the like, and then a diffusion layer is formed in a later step. The patterning is performed so that the nitride film 15 remains in the region where the nitride film 15 is formed.

[0007] Then, as shown in FIG.
By this method, a thick field oxide film 4 is formed on the surface of the epitaxial layer 3 except for the remaining region of the nitride film 15, that is, the region other than the region where a diffusion layer will be formed in a later step.
Furthermore, as shown in FIG. 14, after the nitride film 15 and underlying oxide film 14 on the region where the element isolation 5 is formed are removed, as shown in FIG. The p+ type element isolation 5 is formed by diffusion to a high concentration.

At this time, the nitride film 15 and underlying oxide film 14 remain on the collector region, emitter region, and base region of the substrate 1, respectively, and are masked, so that p-type impurities are not diffused into these regions. On the other hand, this p
+ An oxide film 6 is formed on the element isolation 5 by oxidation added during diffusion.

Next, as shown in FIG.
After all of the photoresist 16 is removed, a photoresist 16 is applied to the regions other than the collector region and the emitter region, boron (B) ions are implanted using this as a mask, and heat treatment is performed to form the substrate 1 as shown in FIG. The strain on the surface is recovered by ion implantation and the implanted B ions are diffused, thereby forming a p+ type collector diffusion layer 7 and a p+ type emitter diffusion layer 8. At this time, field oxide film 4
is so thick that B ions cannot reach the area below it.

Further, as shown in FIG. 17, after the photoresist 16 is removed, a photoresist 17 is applied to areas other than the base area, the underlying oxide film 14 of the base area is removed, and the photoresist 17 is masked. As shown in FIG. 18, arsenic (As) is ion-implanted, and then, as shown in FIG. 18, heat treatment is performed to diffuse the implanted As ions, forming an n+ type base diffusion layer 9, and removing the photoresist 17. Ru.

At this time, the base diffusion layer 9 is
The top is oxidized to form a thin oxide film 18.

After the PSG film 13 is formed on the entire surface by the CVD method, collector, emitter, and base electrode outlets are formed in the PSG film 13, thin oxide film 18, and underlying oxide film 14, and these electrodes are Each electrode 10 at the outlet
, 11, 12 are formed, and a horizontal pn as shown in FIG.
A p-transistor is formed.

By the way, as shown in FIGS. 16 and 17, the p+ diffusion and then the n+ diffusion are performed in accordance with the manufacturing process of the vertical npn transistor, as described above. This is because consideration was given to manufacturing.

[0014]

[Problems to be Solved by the Invention] Since the lateral pnp transistor, which is a conventional semiconductor device, is constructed as described above, in order to reduce the size of the transistor, the distance between the emitter diffusion layer 8 and the collector diffusion layer 7, In other words, the base width WB can be made smaller, which characteristically increases the current amplification factor hFE, but as shown in FIG. However, there is a problem in that the constant current characteristics deteriorate when configured as follows.

The present invention was made to solve the above-mentioned problems, and it is possible to reduce the size of a semiconductor device.
Moreover, it is an object of the present invention to prevent the early voltage from decreasing as in the conventional case.

[0016]

[Means for Solving the Problems] A semiconductor device according to the present invention includes an epitaxial layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and an epitaxial layer of a first conductivity type formed on the epitaxial layer. a first diffusion layer; a trench formed in the epitaxial layer to surround the first diffusion layer and filled with a semiconductor layer and an oxide film; and a first trench formed in the epitaxial layer to surround the trench. It is characterized by comprising a conductive type second diffusion layer.

The manufacturing method also includes a step of forming an epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and forming a first oxide film, a nitride film, and a second oxide film on the epitaxial layer. a step of sequentially forming films; and a step of sequentially forming films;
forming a groove in the surface layer portions of the oxide film, the nitride film, the first oxide film, and the epitaxial layer so as to surround a predetermined region, and removing the second oxide film and forming a groove on the inner surface of the groove. a step of forming a first thermal oxide film; a step of depositing a semiconductor layer over the entire surface to fill the trench, and then leaving the semiconductor layer only in the trench;
covering with a thermal oxide film and then removing the nitride film;
The predetermined region surrounded by the groove of the epitaxial layer and the region surrounding the groove are each provided with a first conductive type,
It is effective to include a step of forming a second diffusion layer.

[0018]

[Operation] In the semiconductor device according to claim 1, the first
A groove is formed to surround the first diffusion layer, and a second diffusion layer is formed to surround the groove, so the base width, which is the distance between the first and second diffusion layers, is ) x 2 + (groove width)", and it is possible to reduce the width of the groove by making it deep enough so that it does not reach the substrate, resulting in a sufficient base The size of the semiconductor device can be reduced while maintaining the width, and the disadvantages caused by the drop in early voltage, which are conventional, can be prevented.

Further, each step in the manufacturing method according to the second aspect makes it possible to obtain the semiconductor device as described above.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a semiconductor device and a method for manufacturing the same according to the present invention, and is a sectional view of a lateral pnp transistor as a semiconductor device. In addition, in the same figure, Figure 1
The same symbols as 0 indicate the same or equivalent parts.

In FIG. 1, 21 is a groove formed in the epitaxial layer 3 so as to surround the emitter diffusion layer 8.
The inner surface of the groove 21 is filled with a first thermal oxide film 22 and a polysilicon layer 23 which is a semiconductor layer, and a collector diffusion layer 7 is formed to surround the groove 21.

At this time, the emitter diffusion layer 8 corresponds to the first diffusion layer, and the collector diffusion layer 7 corresponds to the second diffusion layer.

Next, FIGS. 2 to 7 show the above-mentioned horizontal PNP
3 is a partial cross-sectional view showing a manufacturing process of a transistor, and each of the following steps will be described. FIG.

First, as shown in FIG. 2, an n+ type buried diffusion layer 2 is formed on the surface of a substrate 1, and then an n- type epitaxial layer 3 is formed on the substrate 1 and the buried diffusion layer 2. On the surface of this epitaxial layer 3, a first oxide film 24 with a thickness of about 500 angstroms, a nitride film 25 with a thickness of about 1000 angstroms, and a thick second oxide film 26 for protection during trench formation are formed in sequence by CVD. be done. Thereafter, p+ type element isolation 5 is formed by a process similar to that described in the prior art section.

Next, as shown in FIG. 3, the second oxide film 26, the nitride film 25, the first oxide film 24, and the surface layer of the epitaxial layer 3 are subjected to RIE using a mixed gas of CCl4 and O2. Accordingly, a depth of 0.
A groove 21 of about 5 to 2 μm is formed, and after the second oxide film 26 on the uppermost layer is removed, a first thermal oxide film 22 is formed on the inner surface of the groove 21. At this time, the groove 21 is set to a depth that does not reach the substrate 1.

Then, as shown in FIG. 4, a non-doped polysilicon layer 23 is deposited on the entire surface to a thickness of about 5000 angstroms to fill the groove 21, and then SF6
The polysilicon layer 23 is selectively removed by RIE using a mixed gas of CCl4 and CCl4, and as shown in FIG.
Further inside the first thermal oxide film 22 formed on the inner surface of the trench 21, a polysilicon layer 23 is filled.

Furthermore, the polysilicon layer 23 is formed by thermal oxidation.
After a relatively thick second thermal oxide film 27 of 2000 to 3000 angstroms is formed on the surface of B, the nitride film 25 is removed as shown in FIG.
is ion-implanted and subjected to heat treatment to form a p+ type collector diffusion layer 7 and emitter diffusion layer 8. After that, a base diffusion layer 9 is formed by the same process as described in the prior art section, and the PSG is Membrane 13 and each electrode 10,1
1 and 12 are formed.

Therefore, a groove 21 is formed to surround the emitter diffusion layer 8, and a collector diffusion layer 7 is further formed to surround this groove 21, so that the conventional field oxide film 4 between the two diffusion layers 8, 7 is formed. Instead, a groove 21 is formed,
This situation is shown in FIG. 8 in a plan view.

By the way, with such a configuration, the effective base width WB (the distance between the emitter diffusion layer 8 and the collector diffusion layer 7) is the depth d of the groove 21 shown in FIG.
is determined by the width w of the groove 21, and the base width WB is (2・d+
w), the groove 21 is made to the extent that it does not reach the substrate 1.
By ensuring a sufficient depth d of the groove 21, the width w of the groove 21 can be
As a result, the width w of the groove 21 can be reduced.
By reducing , the size of the transistor can be reduced, and a sufficient value can be secured for the base width WB, which reduces the constant current due to the drop in early voltage when configuring a current mirror circuit, as in the conventional case. Deterioration of characteristics can be prevented.

Furthermore, since the groove 21 filled with the first thermal oxide film 22 and the silicon layer 23 is formed between the collector and emitter diffusion layers 7 and 8, it is possible to increase the reversal voltage of the epitaxial layer 3 to p-type. It is not necessary to form a thick field oxide film 4 as in the conventional method, and the step difference in the oxide film can be made smaller than in the conventional method to improve flatness, and the reliability of the metal wiring can be improved.

FIG. 9 is a sectional view of another embodiment of the present invention. In this figure, the difference from FIG. 1 is not only between the emitter and collector diffusion layers 8 and 7 but also between the base diffusion layer 9.
A similar trench 21 was also formed between the two layers, and instead of the conventional thick field oxide film 4 (see FIG. 10), a trench 21 filled with a first thermal oxide film 22 and a polysilicon layer 23 was formed. That's true.

In this way, all the field oxide films 4
When is replaced with the trench 21, there is no need to consider the mask alignment between the field oxide film 4 and the trench 21 compared to the case of FIG. 1, and since the trench 21 is deeper than the field oxide film 4, the isolation ability of the diffusion layer 1, and the transistor can be further miniaturized than in FIG.

Furthermore, even with the thin oxide films 24 and 27, it is possible to secure a sufficiently high voltage for inverting the epitaxial layer 3 to p-type, and to suppress the step difference on the surface of the oxide film compared to FIG. It can make your sex even better.

Although both of the above embodiments have been described with reference to the application to a lateral pnp transistor, the present invention is not limited to this, and it goes without saying that the present invention can also be applied to, for example, a lateral npn transistor.

Further, the semiconductor layer filling the trench 21 is of course not limited to the polysilicon layer.

[0036]

As described above, according to the semiconductor device according to the first aspect, the groove is formed so as to surround the first diffusion layer, and the second diffusion layer is formed so as to surround the groove. Therefore, the first
, the base width, which is the distance between the second diffusion layers, is equal to "(groove depth) x 2 + (groove width)," making the groove deep enough not to reach the substrate. This makes it possible to reduce the width of the groove, and as a result, it is possible to downsize the semiconductor device while ensuring a sufficient base width, and to prevent the disadvantages caused by the drop in early voltage as in the conventional method. It is possible to provide a semiconductor device that is small in size and has excellent characteristics.

Further, according to the manufacturing method according to claim 2, it is possible to obtain a semiconductor device that is small and has excellent characteristics as described above, and is extremely effective for manufacturing lateral pnp transistors, npn transistors, etc. be.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device and a method for manufacturing the same according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1;

3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

4 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1;

6 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

7 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

8 is a plan view of the semiconductor device shown in FIG. 1. FIG.

FIG. 9 is a sectional view of another embodiment of the invention.

FIG. 10 is a cross-sectional view of a conventional semiconductor device.

11 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

12 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

13 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

14 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

15 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

16 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

17 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

18 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 10. FIG.

FIG. 19 is a relationship diagram between base width and Early voltage in a general semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 3 Epitaxial layer 7 Collector diffusion layer (second diffusion layer) 8 Emitter diffusion layer (first diffusion layer) 21 Groove 22 First thermal oxide film 23 Polysilicon layer 24 First oxide film 25 Nitride film 26 Second oxide film 27 Second thermal oxide film

Claims (2)

[Claims] 1. An epitaxial layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a first diffusion layer of a first conductivity type formed in the epitaxial layer; a groove formed to surround a first diffusion layer and filled with a semiconductor layer and an oxide film; and a second diffusion layer of a first conductivity type formed in the epitaxial layer to surround the groove. A semiconductor device characterized by: 2. Forming an epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and sequentially forming a first oxide film, a nitride film, and a second oxide film on the epitaxial layer. a step, the second oxide film, the nitride film,
forming a groove in the surface layer of the first oxide film and the epitaxial layer so as to surround a predetermined region; and removing the second oxide film and forming a first thermal oxide film on the inner surface of the groove. a step of depositing a semiconductor layer over the entire surface to fill the trench, and then leaving the semiconductor layer only in the trench; and a step of covering the surface of the semiconductor layer with a second thermal oxide film by thermal oxidation, and then a step of removing a nitride film; and a step of forming first and second diffusion layers of a first conductivity type in the predetermined region surrounded by the groove of the epitaxial layer and in a region surrounding the groove, respectively. A method for manufacturing a semiconductor device, characterized in that: