JPH04217056A - Automatic connection detecting method - Google Patents

Abstract

PURPOSE:To exactly check all connecting lines of a connector even if a pull-up resistance (or a pull-down resistance) is used on an output side of a processor or an input side of a unit, in the method for detecting whether the connection of the processor and each extension unit is correct or not. CONSTITUTION:This method is constituted so that two fixed data whose logic is inverted each other are stored in advance in a unit 2, the two data concerned designated by two addresses whose logic is inverted each other from a processor 1 are read out of the unit concerned 2, and it is decided that the connecting state is normal, when there is no error in the two data concerned.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic connection detection method, and more particularly to a method for detecting whether the connection between a processor and each expansion unit having an operating section is correct or incorrect.

[0002] When a new unit having an operating section is added and connected after the processor (MPU) is powered on, the communication line and connection signal line between the unit and the processor must be properly connected. It is necessary to be able to determine if there is a problem, but it is desirable that this determination be made automatically without bringing down the service of the device system.

0003

2. Description of the Related Art Conventionally, as shown in FIG. 4, a connection signal (for example, RS2
32C), the processor 1 constantly monitors the connection signal and starts communication after detecting this connection signal.

However, processor 1 and unit 2
Figure 5(a) shows a form of poor connection between the connector 3 and the connector 3.
As shown in (b), there are cases where the pin lengths of the connectors 3 are slightly different, and there are cases where one connector 3 is inserted at a slight angle as shown in (b), so it may be incorrect to judge based only on the connection signal. Causes judgment.

Therefore, as shown in FIG. 6, a method has conventionally been adopted in which an address is given from processor 1 via microcomputer buses 31 and 32 and data is read from unit 2 to confirm the connection. In this case, fixed data is prepared corresponding to one address on the unit 2 side, and the processor 1 periodically reads the data of this address and starts communication when it matches the fixed data. I have to.

[0006]

[Problems to be Solved by the Invention] In the case shown in FIG. may not be connected properly and the logic level may become "H" level even though it is actually "L" level. It is not possible to check the connection wires, and there is a problem in that they are determined to be normal even though there is a poor connection, causing malfunctions.

Accordingly, the present invention provides a method for detecting whether the connection between a processor and each expansion unit is correct or not, in which a pull-up resistor (
The purpose of the present invention is to enable accurate checking of all connection lines of a connector even if pull-down resistors (or pull-down resistors) are used.

[0008]

[Means and operations for solving the problems] FIG. 1 shows the principle of the configuration of the automatic connection detection method according to the present invention.
In the present invention, two pieces of fixed data that are inverted to each other are stored in the unit 2, and the two pieces of data specified by two addresses that are logically inverted to each other are read out from the unit 2 from the processor 1, and the two data are made to contain errors. The connection status is determined to be normal when there is no.

[0009] To explain this more clearly with reference to Figure 1,
First, the illustrated addresses ■ and ■, and these addresses ■
The fixed data ■ and ■ corresponding to and ■, respectively, are set in a logically inverted relationship with each other, and the fixed data ■ and ■ are stored in the unit 2 in advance. First, fixed data ■ is read out from the processor 1 at address ■, and if this matches in processor 1, fixed data ■ is further read out at address ■. As a result, when the two fixed data (1) and (2) match in the processor 1, it can be determined that the connection state is normal regardless of the presence or absence of the pull-up resistor (or pull-down resistor) as described above.

Further, in the present invention, third fixed data is further stored in the unit 2 at a third address from the processor 1, and in the unit 2, the stored third fixed data matches the own station data. It is also possible to open the communication line only when this happens, and then determine that the connection is complete when the fourth fixed data stored in the unit 2 is read out from the processor 1 at the fourth address.

[0011] To explain this more clearly with reference to Figure 1,
When fixed data ■ is written from processor 1 to unit 2 at address ■, and when this fixed data ■ matches unit 2's own data, unit 2 starts actual operation between processor 1 and unit 2 ( In this state, when the address (2) is given from the processor 1 to the unit 2 and the fixed data (2) read from the unit 2 match in the processor 1, it is assumed that the connection is completed.

[0012] As a result, from processor 1 to unit 2
This means that it is possible to determine whether the connection state is correct or not, including the write operation.

[0013]

Embodiment FIG. 2 shows an embodiment of the unit 2 used in the automatic connection detection method according to the present invention. In this embodiment, 20 indicates a read (RD) signal and a write (WR) signal.
) signal and an address signal; 21 is a memory that stores fixed data (2) in advance and is accessed by the decoder 20; 22 is a memory that stores fixed data (2) in advance and is accessed by the decoder 20; 23;
24 is a memory that is accessed by the decoder 20 and is used to write data (fixed data in the normal case), 24 is a data comparator that compares the data written in the memory 23 and the own data, and 25 is a data comparator 24 of the data comparator 24. 26 is a circuit that prohibits writing/reading of actual data based on the comparison result; 26 is an operating unit that causes the unit 2 to perform an actual operation (for example, ON/OFF operation of a relay); and 27 is a memory that stores fixed data (2) in advance and is accessed by the decoder 20. Note that processor 1 and unit 2 are connected by a 1-bit line through which the above-mentioned read signal and write signal pass, respectively, and an 8-bit bus through which address signals and data signals pass, respectively. do.

FIG. 3 shows the processing procedure of the processor 1. Hereinafter, referring to this FIG. 3 and the above-mentioned FIG. 1, FIG.
The operation of the embodiment will be explained.

First, the processor 1 sends out an address (for example, "AA" in hexadecimal) along with the read signal RD (step S1), and in the unit 2, the decoder 20 accesses the memory 21 corresponding to the address. The data is read and sent to processor 1.

The processor 1 determines whether the read data is fixed data (for example, "33" in hexadecimal) (step S2), and if it is fixed data, the next address is ■ (for example, "55" which is the logical inversion of the above address ■ in hexadecimal) is sent to the unit 2 together with the read signal RD (step S3).

In the unit 2, the processor 1 determines whether the data read out from the memory 22 accessed by the decoder 20 is fixed data (for example, "CC" in hexadecimal) (step S4
).

As a result, when the read data is fixed data (2), it is determined that the connection state of the write/read line, address bus, and data bus is normal.

At this point, a certain amount of automatic connection detection has been performed, but it is desirable to perform the following operation in order to determine whether or not the write operation is also performed normally.

That is, along with the write signal WR, the processor 1 sends the address (■) (which may be any address as long as it does not overlap with the above-mentioned addresses (■) and ()) to the unit 2 (
In step S5), fixed data (this may be arbitrary) is written in the memory 23 accessed by the decoder 20 using this address ().

Here, in the unit 2, the data comparator 24 compares the fixed data written in the memory 23 with the own station data.

As a result, only when the two match, the data write/read inhibiting circuit 25 releases the inhibited state, and the operating section 26 becomes operable.

In this state, when the processor 1 sends the address ■ (which may also be arbitrary) and the read signal RD to the unit 2 (step S6), the data is read from the memory 27 accessed by the decoder 20 of the unit 2. The data is read and sent to the processor 1 via the data write/read inhibit circuit 25.

Therefore, the processor 1 checks whether or not this data is fixed data (step S
7), it can be determined whether or not actual operation with the unit 2 is possible, and if the fixed data is (2), communication between the processor 1 and the unit 2 is started (step S8).

If the fixed data (2) can be read out in this way, it means that the write signal connection is performed normally.

[0026]

As explained above, according to the automatic connection detection method according to the present invention, two pieces of fixed data that are logically inverted to each other are stored in a unit, and specified by a processor using two addresses that are logically inverted to each other. Since the configuration is configured so that the connection status is determined to be normal when the two pieces of data are read from the unit and there are no errors in the two pieces of data, a pull-up resistor (pull-down resistor) is connected to the processor side and the unit side. Even if the connectors are connected to each other, it is possible to accurately determine the connection state of both connectors, and malfunction of each unit can be prevented.

Further, in the present invention, third fixed data is further stored in the unit at a third address from the processor, and the unit stores the third fixed data only when the stored third fixed data matches the own station data. The configuration is such that it is determined that the connection is complete when the unit is enabled for actual operation and then the fourth fixed data stored in the unit is read from the processor at the fourth address. The connection state of each unit, including its operation, can be determined.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of an automatic connection detection method according to the present invention.

FIG. 2 is a block diagram showing one embodiment of each expansion unit used in the automatic connection detection method according to the present invention.

FIG. 3 is a flowchart showing an embodiment of a processing procedure of a processor according to the present invention.

FIG. 4 is a diagram for explaining detection of a connection signal between a processor and a unit in the related art.

FIG. 5 is a diagram showing a form of connector connection failure.

FIG. 6 is a diagram for explaining detection of a connection signal via a bus between a processor and a unit in the related art.

[Explanation of symbols]

1 Processor 2 Unit 20 Decoder 21-23, 27 Memory

Claims (2)

[Claims] Claim 1: In a method for detecting whether the connection between a processor (1) and each expansion unit (2) is correct or not, two fixed data logically inverted from each other are sent to the unit (2).
When the processor (1) reads out the two data specified by the two logically inverted addresses from the unit (2) and there is no error in the two data, the connection state is normal. An automatic connection detection method characterized by determining that. 2. Further, third fixed data is stored in the unit (2) at a third address from the processor (1), and in the unit (2), the stored third fixed data is the own station data. The corresponding unit (2) only when it matches
After that, the processor (1
2. The automatic connection detection method according to claim 1, wherein the connection is determined to be complete when the fourth fixed data stored in the unit (2) is read out from the unit (2) at a fourth address.