JPH04207426A - Frame synchronization system - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to decrease the operation by collating feedback signals of an aligner, a secondary detection circuit and a control section while shifting a data in the unit of STM-1 and detecting synchronization when synchronization pattern bits of a frame are coincident. CONSTITUTION:A serial parallel conversion circuit 1 converts a serial data into a parallel data, an aligner 2 receives the parallel data to shift the data in the unit of bits or bytes and outputs a parallel data, and a primary detection circuit 3 detects deviation in bits from a frame synchronizing signal in the input or output of the aligner 2. Then a 1st control means 15-1 controls the aligner 2 with an output of the primary detection circuit 3, a secondary detection circuit 4 detects a border of a frame synchronization pattern of a serial data being an output of the aligner 2 controlled by the 1st control means 15-1 from a signal corresponding to plural consecutive bytes of the serial data, and a 2nd control means 15-2 controls the aligner 2 with an output of the secondary detection circuit 4. Thus, the circuit scale is reduced and the operation speed is decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame synchronization system, more specifically, to G, 707 to G, 7 of the Consultative Committee for International Telegraph and Telephone (CCITT).
The present invention relates to a frame synchronization signal detection method for multiplex transmission data in the sTM-N7 format recommended in 2009.

[Prior Art] The network interface for digital synchronous hierarchy, which has been internationally standardized by CCITT, uses STM-1 as a data transmission format, in which the basic frame is STM-1, and N basic frames are multiplexed in byte units.
The processing target is N-frame format multiplex transmission data. As will be explained in detail later, the STM-N frame includes a frame synchronization pattern of 2N×3 bytes and channel identification information of N bytes in the section overhead (SOH) of the frame. In frame synchronization of STM-N multiplex transmission data using these byte information, the transmission speed of STM-N multiplex transmission data is high, so the circuit device for frame synchronization must be slowed down.

Naturally, it is necessary to realize this using an economical circuit.

As a frame synchronization method that can be realized with a low-speed and economical circuit, the inventors of the present application proposed an STM-N frame as shown in FIG. A synchronization method was announced. This method separates and expands received data in the STM-N frame format into N sequences in byte units using arbitrary bit positions as delimiters, and detects bit position shifts in the received data using a byte signal of one sequence #n. After the detection, the frame synchronization pattern A1 is detected by comparing the bit states at a predetermined bit position corresponding to the amount of position shift from the end position of the frame synchronization pattern A1 in the bit position shift state between the N output signal series. It detects the break between A2 and performs frame synchronization based on the break information.

[Problems to be Solved by the Invention] Although the frame synchronization method circuit announced by the above inventors has a small number of bits in the synchronization detection block When N is large, the circuit scale increases.

Also, byte synchronization detection, that is, frame synchronization pattern A1
, A2 in order to correctly detect the break between 3×N A1 and 3×N A2 in the serial signal.
In some cases, it is necessary to detect the first A2.

The main purpose of the present invention is to provide STM-N frame transmission.
It is an object of the present invention to realize a frame synchronization signal detection circuit that is small in circuit scale and operates at low speed without depending on the number N of multiplexing.

Another object of the present invention is to provide STM-N frame transmission,
The object of the present invention is to realize byte synchronization and channel synchronization by economical and simple means.

[Means for Solving the Problems] In order to achieve the above object, the frame synchronization method of the present invention converts serially transmitted STM-N frame format transmission data into M (integer numbers) starting from an arbitrary bit. The bit shift state (focus) of each byte-based frame synchronization pattern A1 and A2 is determined by sequentially expanding the series in parallel and monitoring the parallel data corresponding to consecutive 8 bits of the serial transmission state from the data developed into the M series. After detecting the above-mentioned bit deviation state, the aligner performs aligner control (
bit shift operation), and further detects the state of deviation between STM-1 within the frame using the output from this aligner,
Feedback control is performed to the aligner to align each STM-1 in the frame, obtain an M-sequence output signal in frame synchronization state, perform reliable synchronization detection, and further protect with the synchronization state output signal. Perform detection.

[Operation] The frame synchronization signal F, which is sent at the same time as the information transmitted between transmitting and receiving devices in the synchronous transmission format recommended in CCITT G, 'IO'l~G, '709, is as shown in Figure 2. N frames of 270x9 bytes srM-1=1
．． ,, STM-1-N, time division multiplexing is performed in byte units, so after the frame synchronization pattern A1 continues for 3×N, the frame synchronization pattern A2 continues for 3×N. Therefore, S
TM N frame format transmission data is sequentially expanded in parallel into an M (integer) series starting from an arbitrary bit, and by monitoring the parallel data corresponding to consecutive 8 bits in the serial transmission state, the N Each of the output signal sequences of the series includes bit shift information. Therefore, using this bit shift information, the bit shift is corrected and byte synchronization is achieved in the aligners which input each of the N series of output signal series. By examining two output signal sequences of the N output signal sequences of the aligner in which byte synchronization is achieved, the boundary between 3×N A1 and 3×N A2 can be detected. Frame synchronization can be achieved by feeding back this boundary detection information to the aligner.

[Example] Examples of the present invention will be described below.

FIG. 1 is a block diagram of an embodiment of a frame synchronization system according to the present invention.

The transmission line 6 has the CCITT 0°70 explained in Fig. 2.
ST of synchronous transmission format recommended in 7-G, 709
MN frame format transmission data is serially transmitted. The serially transmitted STM-N frame input data is separated and distributed in bit units to M lines 11 by the serial-parallel conversion circuit 1. Of the data separated by M lines 11, bit information corresponding to consecutive 8 bits when it is serial data is input to the primary detection circuit 4 from the parallel lines M-7, , M, and detects the deviation within 1 byte. The bit position is corrected by the aligner 2 via the control section 5 and the control line 15-1. The corrected aligner output is output to output line 12. Of the output line 12, the bit information corresponding to even multiples of consecutive 8 bits when it is serial data is taken into the secondary detection circuit 4, and the synchronization pattern A1 included in the STM-N frame is taken into the secondary detection circuit 4.
, A2 are detected and the data is output in the order in which the aligner output 12 is byte-multiplexed. The details of each part will be explained below.

Figure 3 shows A1 and A2 of the frame synchronization pattern in Figure 2.
is shown using a specific code pattern.

STM-1 frame (STM-1--1,, STM-
The STM-N frame, which time division multiplexes 1-N) in byte units, has 2430 x N bytes of data in 125 μsec, and the frame synchronization patterns AI and A2 are set at the beginning of the frame to achieve frame synchronization. 3×N
This is followed by a channel identification number (I
D) C1 has N bytes. The synchronization pattern is CCIT
Due to the notification, A1 is “11110110” and A2 is “0”.
0101000”.

In this embodiment, frame synchronization patterns A1, A2
Synchronization detection is performed only in , and identification pattern C1 is not used.

The separation number M of the serial-parallel conversion circuit 1 is preferably a multiple of 8 in terms of the detection configuration, and if M = 8 x N, the output data 12 is output in multiplexed byte units. However, it is not necessary to have the relationship M=8×N.

FIG. 4 shows the output data of the serial-to-parallel conversion circuit 1 of FIG. 1, in particular, the state in which the bit shift is not corrected. Parallel number M: For convenience, the line 11 is 8.9 to 16.17 to 24 degrees, 25 to 32. , M-7
-M are shown separately.

Since the serial-parallel conversion circuit 1 starts separation from an arbitrary bit in the received data, two types of synchronization patterns A are available.
Synchronization detection is performed from the separated states of A1 and A2. In the case of the embodiment shown in FIG. 1, consecutive 8 of the parallel data 1 to M
The primary detection circuit 3 detects a bit shift using signals from the output lines M-7 to M-M. As shown in FIG. 5, the primary detection circuit 3 detects the shift state of the synchronization pattern, that is, the number P of bit shifts in one byte. CCITT G, 707~G
, 709, the two types of synchronization patterns A1 in the synchronous transmission format can detect all bit deviations by adjusting the 8-bit bit pattern. In the example shown in Figure 5, the bit pattern of the upper 8 bits is rllollo.
llJ, and it can be seen from FIG. 5 that this is shifted 2 bits to the left.

- The control circuit 5 calculates the number of bit deviations P detected by the water detection circuit 3.
A control signal to correct the bit misalignment condition is sent to line 1.
5-1 to the aligner 2. The aligner 2 performs intra-byte alignment.

As a result, as shown in FIG. 6, the output data of the aligner 2 is arranged such that it consists of the first bit of one byte from the beginning. That is, a synchronization pattern A], .A2 appears.

At this stage, the output data 12 of the aligner 2 is ts in STM-1 units that constitute STM-N in one frame.
l, #2. #3. ... Since the serial-parallel conversion circuit 1 starts separation from an arbitrary position in the order of #n, the position of the frame unit #1 in the output data 12 of the 5 aligner 2 cannot be specified.

Next, the output data of the aligner 2 is checked byte by byte in the secondary detection circuit 4, and the data is outputted from the aligner in the multiplexed order. That is, output lines 1 to 8.9 of aligner 2
16.17-24.25-32,. From 0M7 to 0M, Ax and A2 are made to occur three times at the same time.

As shown in FIG. 1, the signals of the output lines 1 to 8 and M7 to M of the aligner 2 are input to the secondary detection circuit 4, so that
In the case of simultaneous 16-bit consecutive verification of 1 and A2, STM-
16 between the last A1 of #n and the first A2 of #1 in 1 unit
Verify bits.

When the aligner output data 12 is correctly separated by bytes, A1 is set from M-7th to Mth output, and 1 is set from A1.
A2 at the 1st to 8th aligner outputs that are delayed by the clock.
is detected. Therefore, while shifting in STM-1 units, the aligner 2. Feedback verification is performed between the secondary detection circuit 4 and the control section 5, and when the 16 bits of A1 and A2 match, synchronization detection is performed.

As a result, the output of the aligner 2 becomes as shown in FIG. 8, and since the matching pattern is uniquely determined, synchronous detection is possible, and the aligner outputs are output in the order in which they were multiplexed.

Furthermore, the second detection circuit can directly perform forward protection detection.

FIG. 8 is a diagram showing the configuration of another embodiment of the frame synchronization method according to the present invention, in which the primary detection circuit 3 and the secondary detection circuit 4 of FIG. 1 are combined to form a synchronization detection circuit 8 on the output side of the aligner 2. With this configuration, the aligner 2 directly outputs the separated data as the aligner output 12 until a bit shift is detected. Bit deviation is detected and the aligner 2 is controlled via the control unit 5.
is controlled, and the fifth synchronization pattern detection circuit 8 is operated in the same manner as the secondary detection circuit 4 in FIG.
Controls the arrangement of bytes until the boundary is detected. The bit shift is detected and corrected by the aligner 2. By controlling in this manner, data is output from the aligner output 12 in the order in which the bytes were multiplexed.

FIG. 9 is a diagram showing the configuration of still another embodiment of the frame synchronization method according to the present invention. In this embodiment, in order to improve the accuracy of bit shift detection, the input of the primary detection circuit 3 is
The circuit is similar to that shown in FIG. 1, except that many of the output lines of the separation circuit 1 are utilized.

[Effects of the Invention] According to the present invention, even when the number N of multiplexing of STM-H increases, the configuration of the circuit required for frame pattern detection is almost the same as the configuration when N is small, and the same verification is possible. Since the circuit scale only changes depending on the number of bits, it is possible to prevent an increase in the circuit scale and an increase in the size of the device even when the number N of multiplexing becomes large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the frame synchronization method according to the present invention, FIG. 2 is a diagram showing the STM-N transmission frame format and the position of the synchronization pattern, and FIG. - A diagram showing A1 and A2 of the system synchronization patterns in concrete code patterns, Figure 4 is a diagram showing the smallest detection configuration and the lower side, Figure 4 is a diagram showing the output data of the serial-parallel converter circuit 1 in Figure 1, Figure 5 is a diagram showing the output data of the serial-parallel conversion circuit 1 of Figure 1 The figure shows the relationship between bit patterns and bit deviations, Figure 6 shows the code pattern of the output signal sequence when bit deviation is corrected, and Figure 7 shows the code of the output signal sequence when frame synchronization is performed. The pattern diagram, FIGS. 8 and 9 are all block diagrams showing the configuration of other embodiments of the frame synchronization method according to the present invention, and FIG. 10 is a diagram showing the frame synchronization method which is a known technique. DESCRIPTION OF SYMBOLS 1... Separation circuit 52... Aligner, 3... Synchronization pattern, 4... Detection circuit following the synchronization pattern, 5... Aligner control section, 6... Input serial data, 11... Separation data, 12 ... Aligner output data, 13... Bit deviation number information, 14... Synchronization pattern - number information, 15.
・Aligner control signal. Representative Patent Attorney Susuki 1) Toshiyuki Figure 1 Figure 2 Figure 3 Figure 4 Figure 1 Bang! Il! Figure 5 Figure 6 Figure 7) Figure 8

Claims (1)

[Claims] 1. CCITTG. 707~G. A serial-to-parallel conversion circuit that converts STM-N frame format transmission data in the synchronous transmission format recommended by G.709 from serial data to parallel data, and inputs the parallel data, shifts bits or bytes, and outputs it in parallel. an aligner; a first detection means for detecting a bit shift from a frame synchronization signal input or output from the aligner;
a first means for controlling the aligner according to the output of the first detecting means, and a boundary between frame synchronization patterns A1 and A2 in the serial data from the output of the aligner controlled by the first means; A frame synchronization method comprising: a second detection means for detecting signals corresponding to a plurality of bytes; and a second means for controlling the aligner based on the output of the second detection means. 2. In the frame synchronization method according to claim 1, the first
The detection means inputs a signal corresponding to a continuous 1-byte signal of the serial data at the output of the serial-parallel conversion circuit or a signal corresponding to a continuous 1-byte signal of the serial data at the output of the aligner. Frame synchronization method. 3. The frame synchronization method according to claim 1 or 2, wherein the number of parallel output lines of the serial-to-parallel conversion circuit and the aligner is 8×N (N is the number of frame multiplicity). 4. The frame synchronization method according to claim 1, 2 or 3, wherein the plurality of bytes input to the second detection means is 2 bytes. 5, CCITTG. 707~G. This is a method of synchronously distributing the STM-N frame format transmission data in the synchronous transmission format recommended by G.709 into N output signal sequences, and in which the serial data of the STM-N frame format transmission data is divided into bytes. converting into N-series output signal sequences in units, detecting bit position deviations from byte unit frame synchronization patterns A1 and A2 included in at least a part of the N-series output signal sequences, and detecting bit position deviations; is used to correct the bit position shift of the N series of output signal series, and detect the boundary between the synchronization patterns A1 and A2 from the signals of two adjacent series among the N series of output signal series that have been corrected. Then, the above STM- found from the above boundary
A frame synchronization method that obtains N output signal sequences in a frame synchronization state based on the frame head position of N frame format transmission data.